A New Concept of PWM Duty Cycle Computation Using the Barycentric Coordinates in a Three–Dimensional Voltage Vectors Arrangement

The paper presents a novel approach to the Pulse Width Modulation (PWM) duty cycle computing for complex or irregular voltage vector arrangements in the two (2D) and three–dimensional (3D) Cartesian coordinate systems. The given vectors arrangement can be built using at least three vectors or collections with variable number of involved vectors (i.e. virtual vectors). Graphically, these vectors form a convex figure, in particular, a triangle or a tetrahedron. The reference voltage vector position inside that figure can be expressed by the barycentric coordinates, which are calculated using the second (2D case) or the third–degree determinant (3D case) – without trigonometry and angles. Thus, the speed of the PWM duty cycle computation rises significantly. The use of the triangle area or the tetrahedron volume, instead of the standard vector projection also permits for a well–defined and universal approach to identifying the reference vector position, especially for converters with complex and/or deformed space–vector diagrams (i.e. floating DC–link, multisource DC–link). The proposed computation scheme is based on simple instructions without trigonometry thereby, the DSP processor, or digital solution for field–programmable gate array, can fast–perform this operation using atomic operations. The aim of the presented considerations is not a novel PWM modulation, but a computable idea of a general calculation scheme for cases in which the distribution of vectors is non-trivial. A detailed algebraic and geometric analysis, as well as mathematical proofs on the total consistency of the results with the standard projection method, are also included. Subsequently, the Three–Dimensional Space Vector Modulation (3D–SVM), is considered as a special background to present a novel approach.


I. INTRODUCTION
The development of industrial power electronic applications is currently associated with multilevel inverters [1]- [5]. It results from the need for quality of formed voltages, currents and EMI, as well as the necessity to work with multiple sources and higher voltages. To meet these requirements Voltage Source Inverters (VSI) topologies, become more complex with the increasing number of voltage levels The associate editor coordinating the review of this manuscript and approving it for publication was Zhilei Yao . and inverter legs. Growing complexity of VSI topologies entails a significant increase in the complexity of Pulse Width Modulation (PWM) methods suitable for these inverters. This paper addresses the above problem by proposing an effective 3D-SVM computing algorithm based on barycentric coordinates [6] for 3-level 4-leg diode-clamped VSI. The proposed algorithm can be applied for 4-wire 3-phase applications such as DSTATCOM, multi-source Hybrid Energy Storage Systems, Active Power Filter [4], [7]- [13], local small power PV generation plant, uninterruptible power supply of various factories, offices, residential houses, etc.
According to the simple modulation algorithms, several references propose transformations of the space-vector diagrams from the Cartesian (or αβ) coordinates to other frames. The gh [14], the 60 • [15], mn coordinates [16] or α β coordinate system proposed in [17] are attempts to simplifying the modulation algorithm. However, all of them relies on balanced DC-link voltages. Moreover, none of the mentioned space-vector diagram transformations are applicable to 4-wire, 4-legs inverters. Analysis and comparison of the mentioned transformation methods with barycentric coordinates for 3-wire system can be found in [6]. One of the few attempts (applicable for 4-wire systems) to compute the duty cycles of the actual (i.e. non-ideal) component vectors for the three-level NPC inverter was presented in [18]. The authors proposed an extension of the gh frame method of [14] to include accurate duty cycle calculations under the DC-link imbalance. The idea, called the method of projections, is quite complex and is derived after a complex analysis of geometric relationships between the basic vectors displaced by the DC-link voltage imbalance. The approach is hardly extendable to other cases, for instance, a different type of component vectors (e.g. virtual vectors) or different inverter topologies (e.g. 4-leg inverters or inverters with more than 3 levels).
A more universal method was proposed in [19]. The calculations of duty cycles are performed in a frame called abc coordinates. This frame is made of three axesa, b and c -corresponding to the respective three phases of the inverter, but forming a three-dimensional orthogonal system rather than the standard planar system with the abc axes rotated by multiples of 2π/3. It permits for quite simple representation of DC-link voltage imbalance and computation of duty cycles under imbalance. The method can be used for multilevel 3-leg and 4-leg inverters however, considering DC-link voltages imbalance requires an additional transformation of coordinates and allows to synthesize voltage only in a three-phase system according to its orthogonal nature.
This paper also proposes a computational approach supporting explicit space-vector PWM computations for multilevel inverters with possible DC-link voltage imbalance. The key idea in the proposed arithmetic is the use of barycentric coordinates for the duty cycle computations and the selection of the modulation triangle/tetrahedron (2D/3D). Unlike the method of [19], which uses a special coordinate frame, the proposed method is applied directly to space-vector diagrams in the natural Cartesian coordinates (αβ) and can be implemented to multiphase systems. The method can be applied to all types of multilevel inverters.
To achieve a better understanding of the proposed concept, the discussion was divided into smaller sections. The new general computation formula for two-dimensional space is presented in detail in Section I. The next section contains analogous considerations for the three-dimensional coordinates system. Section III contains a brief introduction the used 3D-SVM modulation and barycentric coordinates in the modulation algorithm. Proposed modulation algorithm is based on [20] but developed by balancing DC-link voltages [21]- [24], accurate generation of output voltages regardless of unbalanced capacitor voltages [18], [19], fast duty cycles calculations algorithm based on barycentric coordinates [6] and optimal switching state sequence. Experimental results are introduced in Section IV to validate the effectiveness of the proposed duty cycle computation. The article closes with a summary and a brief discussion on the experimental results.

II. PWM DUTY CYCLES COMPUTATION IN A TWO-DIMENSIONAL COORDINATE SPACE
Let [ w 1 , w 2 , w 3 ] denote a three-element vector collection in the two-dimensional Cartesian xy coordinate system shown in Fig. 1(a). Coordinates of these independent vectors meet the following equation where α 1 , α 2 and α 3 are real numbers for scaling the length of the corresponding vector. The value of scaling coefficients from (1) can be obtained by constructing a graphic solution. However, it is not a suitable form for implementation in the Digital Control System (DCS). In order to formulate a more practical solution, the vectors arrangement in Fig. 1(a), can be transformed into a new equivalent collection represented by v 1 , v 2 , u vectors in a local pq reference frame, as shown in Fig. 1(b). Thus, updated coordinates can be calculated using the following formula Note that, all vectors in (2) are obtained by subtracting w 3 from the other vectors and the reference vector u can be represented in a similar way to (1) by where where the mark (•) designates the scalar product of two vectors. Both equations (7) and (8) are not satisfying and further optimization can be perform. Despite the elimination of trigonometric functions, they contain the square root operation. In order to obtain a simpler expression for d 1 and d 2 , vectors shown in Fig. 2, can be represented as a collection of points A, B, C, and D as illustrated in Fig. 3. Based on the Thales' theorem, d 1 as the ratio of the length of the segment a to the sum of segments a and b in Fig. 3(a), and analogically for the case ilustrated in Fig. 3(b).
As can be seen in Fig (11) If vertex A is located at the origin (0, 0) of a Cartesian coordinate system and the remaining vertices are represented by point B(v 1x , v 1y ), C(v 2x , v 2y ) and D(u x , u y ), the area of each required triangle can be computed as the absolute value of the determinant. Thus, the PWM duty cycle for vector v 1 can be written as and identically for vector v 2 The PWMDC for zero vector, which corresponds with point Fig. 3, is equal to The sum of all PWMDC, computed for each triangle (A, B, C) vertex, is equal to unity As pointed out, vectors' geometric arrangement depicted in Fig.2, has been transformed into the local triangular area, in which the reference vector u resides. Secondly, the PWMDC have been calculated using a simple rational function based on the triangle area, which can be fast computed using the absolute value of determinants. As is evident VOLUME 8, 2020 from the presented elaboration, only vectors coordinates are only needed. The proposed calculation scheme is widely used in mechanics problem solving and has been successfully adopted in the following paper for the unification of the PWMDC computation [25]. Graphically, all three selected vectors form a convex figure -the triangle -and the reference voltage vector position inside that figure can be expressed by barycentric coordinates, which are just calculated using (12)- (14).
If the sum (15) is greater then unity, as it is shown in Fig. 4, it means that point D lies outside the triangle (A, B, C) and the length of the reference vector u must be rescaled by factor ζ which can be expressed as follows Note, that lines m and n in Fig. 4 are parallel, and therefore, by the theorem of Tales and previous consideration, the ζ factor can be calculated based on the following equation, which can be easily implemented in PWM overmodulation algorithms. The proposed approach has a very useful additional property that their sum equals unity if it is computed for a point inside a triangle (as in Fig. 3), but it is greater than unity if the point lies outside the element (as illustrated in Fig. 4). This is a uniform and effective method to find the traingle in which the reference vector resides. In practice, due to floating-point numbers limited accuracy, the smallest sum (15), ideally equal to unity, is selected as a minimal element using optimized and fast DSP function.
The proposed approach based on geometrical relations, represented by (12) and (13), can be proved algebraically using the formula interpretation of the absolute value of a vector product as follows The proposed computing time of a routine based on the barycentric coordinates was compared with the time used by a routine based on the trigonometric functions and classified   as the method of projections described in [18]. The DSP processor code used in the comparison, which correspondes to illustration in Fig. 5, is shown in Listing 1. The comparison conditions are specified in Table 1, while the comparison results are presented in Table 2.
As might be seen, the proposed arithmetic is more than tentimes faster than the conventional approach. The rationality behind applying barycentric coordinates to calculate PWMDC is that it quickly performs the forward analysis of the effects associated with the given set of selected base vectors in the reference voltage synthesis with small computing overhead. The presented approach can be extended to the three-dimensional space divided into irregular tetrahedrons. The word 'irregular' has been used to emphasize the impact of DC voltage asymmetry in multi-level inverters on the actual output voltage of the NPC converter.

III. PWM DUTY CYCLES COMPUTATION IN A THREE-DIMENSIONAL COORDINATE SPACE
It is assumed that the vector p in Fig. 6, is located inside the tetrahedron V with vertices A, B, C, and D. The reference vector p can be expressed as the following sum where the vectors u, v, and w are the effect of a reference vector p projection on the base vectors − → AB, − → AC, and − → AD respectively The PWMDC from (21) can be written as ratio of appropriate lengths VOLUME 8, 2020  To find a more practical form of (22), the case illustrated in Fig. 6(b) and more detailed in Fig. 7 is considered. The triangle (A D , B D , C D ), which contains a point P (the end of reference vector p), is parallel to the base of tetrahedron V (A, B, C, D), which is the triangle (A, B, C). Moreover, the line n is passing through the vertex D and is normal to the surfaces represented by triangles (A, B, C) and (A D , B D , C D ). Based on the geometric layout in Fig. 7, the PWMDC for vector w can be finally described by the following formula Considering that both tetrahedrons V (A, B, C, D) and V (A, B, C, P) have the same base triangle (A, B, C), the duty cycle d D can be expressed in barycentric coordinates as the ratio of the volume of these figures Analogous results can be obtained with respect to the other verticles Tetrahedron volume can be represented in barycentric coordinates as a ratio of absolute values of determinants. Thus, finally the PWMDC can be expressed as follows where If the given reference vector p resides inside the tetrahedron V (A, B, C, D), the sum of all duty cycles is equal to one, but if point P lies outside the tetrahedron, as it is shown in Fig. 8, the length of p has to be rescaled by factor ζ The following tetrahedrons V (A, B, C, D) and V (B, C, D, P) have a common base triangle (B, C, D). In addition, straight line n is perpendicular to the triangle (B, C, D) surface. Therefore the scaling factor ζ can be also calculated based on Thales theorem There are two tetrahedrons shown in Fig. 9. Selection of the appropriate tetrahedron strongly depends on checking the result of duty cycle summation. Only if point P is inside the tetrahedron, the sum (31), by definition, is equal to unity.

IV. THREE-DIMENSIONAL SPACE VECTOR MODULATION FOR THREE-LEVEL FOUR-LEG DIODE CLAMPED INVERTER
A three-dimensional fast algorithm in abc coordinates has been proposed in [4], [19], [26] but that representation limits the potential of space vector modulation. The DC-link voltage balancing [18], [21]- [24], [27], [28] is omitted though it is a critical task, especially in the Active Power Filter application [10], [13], [29], [30]. In addition, the overmodulation aspect of converter control is also not considered [31]. By using the proposed method of PWMDC calculation, balanced and unbalanced systems can be realized with balanced or unbalanced DC-link voltages. Moreover, during the DC-link voltage balancing process, the output average voltages are precisely synthesized and no output current distortion is observed [18]. The main advantage of accurate control of the DC-link voltages, is that it allows to use smaller capacitors in the DC-link. Note that the main purpose of this section is to demonstrate the abilities of the proposed approach of duty cycle computing. In order to achieve a better understanding, the discussion is divided into smaller subsections.

NOMENCLATURE
For the clarity in further consideration, the following nomenclature is proposed:    4 ] T neutral-point flags matrix.

PRINCIPLE OF OPERATION
The 3-level 4-leg Diode-Clamped inverter is presented in Fig. 10. A general k-switching state of each converter leg can be characterized using three following quantities u lk , h lk , b lk The first u l is the l-leg output voltage value, the second one h l describes the combination of gate signals of power switches s il , and the b l informs whether the load is connected to the neutral-point (NP), marked as a square ''1'' in Fig. 10. The total number of possible switch state vectors is equal 3 4 . An appropriate description can be found in the Table 5 and  Fig. 11. In reference to the publications [20], [32] the three-dimensional space contains 24 base tetrahedrons.  There are four base tetrahedrons 1 , 2 , 3 , and 4 per one sector. An example of a base tetrahedron 1 resides in sector s1 as is illustrated in Fig. 12. Each base tetrahedron can be divided into 8 smaller tetrahedrons, which correspond to an appropriate switch states matrix H in Table 3. Due to the DC-link voltage unbalance phenomena, the n-type and p-type switch state matrix can be used for capacitor voltage balancing. The flowchart of the proposed algorithm is presented in Fig. 13 and described in next subsection.

THE ALGORITHM FLOWCHART
The position of the reference vector p is defined by one sector {s1, s2, s3, s4, s5, s6} and one base tetrahedron { 1 , 2 , 3 , 4 }. At step 1 the position of p is calculated according to the solution given in [20] and is based on a few conditional operations. Next, the six float vertex coordinates for n-type and p-type H, from Table 3, are calculated at step 2 using Clarke transform as follows can be used for the selection of the one right candidate from 8-element set. If the sum (37) is a minimal element, ideally equal unity, the right switch state matrix H will be selected. The fifth step is the selection of the most appropriate switch state matrix H p or H n respectively. The decision can be based on the comparison of the predicted influence of the choice on the NP imbalance voltage A simple analysis of the four possible combinations of the signs of the imbalance voltage and the average neutral point  current leads to the conclusion that it is sufficient to compare the following quantities where i NPn and i NPp are estimates of the expected average neutral point currents corresponding to their respective types of bias If ε n is greater than ε p then H p should be selected; otherwise, the better choice is negative bias represented by H n . Finally, at step 6, the selected pair {H, d} is sent to the pulse pattern generator implemented in a programmable logic device.

V. EXPERIMENTAL RESULT
An experimental prototype of an inverter is presented in Fig. 14, while the parameters are presented in Table 4. The digital control system (DCS) contains a DSP (Texas  Instruments TMS320C6672) and a field-programmable gate array FPGA (Cyclone V). The DC-link is supplied by two adjustable dc-voltage sources U DC1 and U DC2 with additional switch S for voltage balancing experiments. Schematic of the experimental setup is illustrated in Fig. 15. The experimental research plan included the following issues: • DC-link capacitors active voltage balancing ability using redundant switch states (Fig. 16), • Preserving the sinusoidal output currents during the DC-link voltages asymmetry (Fig. 17), • Proper generation of constant gamma component in output currents by adding the common signal (Fig. 18), VOLUME 8, 2020 • Selected higher-order current harmonic injection (Fig. 19), • The phase current asymmetry generation (Fig. 20).

VI. CONCLUSION
The proposed algorithms using barycentric coordinates based on area -2D case, solved by (12), (13) -or volume -3D case, solved by (26)-(30) -are proposed as a tool for PWMDC computations, especially for complex and unbalanced lattices of inverter vectors. Results of benchmark presented in Table 2 show the main advantage of the proposed computation idea -a short time of code execution, what leads to the conclusion, that this method is particularly useful for complex systems (multilevel, multiphase inverters, high-frequency systems, virtual vector methods). The concept permits building the modulation algorithms by referring straight to the converter switch state vectors. Thus, the presented computation idea is suitable for multilevel inverters of different types (diode clamped, flying capacitors or matrix converters). The proposed algorithm enables precise voltages and currents forming during unbalanced capacitor voltages (Fig. 17), as well as it allows to balance DC-link voltages (Fig. 16) using redundant vectors. Comparing currents in Fig. 16 and Fig. 17 it is notable, that considering DC-link unbalanced voltages leads to a better quality of output currents. Possibility of injecting chosen harmonics (Fig. 19) and generation of asymmetry (Fig. 20) or constant gamma component (Fig. 18) in currents show that the proposed algorithm can be a suitable tool for Active Power Filters. The use of barycentric coordinates helps in the development of computation schemes. Note that the method does not influence the results of the PWM duty cycle computations at all, so further analysis of formed voltages and currents in this paper seems pointless, because this kind of research is widely reported in the literature. The presented article shows that trigonometric functions can be eliminated from the modulation algorithm. The presented elaborations lead to the conclusion, that the PWM duty cycle computation can be realized using the simple rational functions and voltages coordinates (in most cases calculated using the Clarke transform). In general, this approach does not give the new spectacular PWM features observed in the frequency spectrum of voltages and currents. The obtained simplification permits for using the low costs FPGA devices because the core of calculation can be based on the parallel add/subtract and multiply operation. If we take into account a very high operating frequency of the GaN or SiC power switches and the limitations of the one-core processors, the undertaken research is purposeful and justified [33]- [36]. The proposed solution is particularly useful when considering the irregular space of voltage vectors. Presented solutions also add uniformity and transparency to the description of PWM-related problems.
The paper authors demonstrated that the proposed PWM duty cycle computation can be successfully applied to the three-dimensional space vector modulation for a three-level four-leg NPC inverter where the volume-based rational functions have been used.

APPENDIX
See Tables 5 and 6. PAWEŁ SZCZEPANKOWSKI (Member, IEEE) received the Ph.D. degree in electrical engineering from the Gdańsk University of Technology, Poland, in 2009. He has authored or coauthored more than 30 scientific and technical articles. His research interests include design, control, diagnostics, modeling, and simulation of power electronic converters, including multilevel and matrix topologies, and signal processing with the use of advanced DSP nad FPGA devices. He is a member of the LINTE 2 Laboratory.
NIKOLAI POLIAKOV received the B.S. and M.S. degrees in electrical engineering from ITMO University, Saint Petersburg, Russia, in 2009 and 2011, respectively. He defended the Ph.D. thesis at ITMO University, Russia, in 2016. He is currently an Associate Professor with the Faculty of Control Engineering and Robotics, ITMO University. His current research interests include power converters design, power electronics, power efficiency, wireless power transfer systems, and control theory and its applications.
DENIS VERTEGEL received the B.S. and M.S. degrees in electrical engineering from ITMO University, Saint Petersburg, Russia, in 2016 and 2018, respectively, where he is currently pursuing the Ph.D. degree with the Faculty of Control Engineering and Robotics. His research interests include power converters, power electronics, multilevel topologies, and multiphase electric drives.
KRZYSZTOF JAKUB SZWARC received the M.S. degree in electrical engineering from the Gdańsk University of Technology, Poland, in 2008. His current research interests include power converters controls, power electronics, coupled reactors theory and applications. He is a member of the LINTE 2 Laboratory.
RYSZARD STRZELECKI received the degree in industrial electronics from the Kyiv University of Technology, in 1981, the Ph.D. degree, in 1984, and the Habilitation (D.Sc.) degree from the Institute of Electrodynamics, Academy of Sciences of the Ukrainian Soviet Socialist Republic, Kiev, in 1991. His D.Sc. thesis was on Prediction Control of the Self Commutation Power Electronics Converters. In 1999, he received the title of Professor of technical sciences. He is currently a Full Professor with the Gdańsk University of Technology, Poland, the Co-Head of the Laboratory of Power Electronics and Automated Electric Drive, ITMO University, Saint Petersburg, Russia, and a Professor of the Łukasiewicz Research Network-Electrical Engineering Institute, Warsaw/ Gdańsk, Poland. He is the author of more scientific articles as well as monographs and patents. His interests focus on topologies and control methods as well as industrial application of power electronic systems. He is a member of the LINTE 2 Laboratory. VOLUME 8, 2020