Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits

Three-dimensional (3-D) integration offers a promising solution to the technology scaling barriers. Reliability of the 3-D Integrated Circuits (ICs) is highly dependent on the integrity of the underlying interconnect. Through Silicon Via (TSV) based 3-D ICs would suffer from low yield due to the faults in TSVs. In addition, TSVs introduce stress and noise in the substrate. Adding redundant TSVs for repairing the faulty ones has commonly been proposed to improve the yield of TSV-based 3-D ICs. The existing TSV repair approaches employ a number of spare TSVs in a group of signal TSVs. We propose a TSV virtualization based repair architecture which utilizes a single redundant TSV to repair multiple faulty TSVs. The proposed architecture relies on transmitting multiple bits through a single TSV using multi-level voltage quantization. It makes efficient use of the TSV redundancies in repairing the faulty TSVs. With less number of spare TSVs, the proposed architecture can reduce the area overhead by more than 70%. Reduction in the TSV count allows greater interconnect density and helps to mitigate the TSV-induced noise and stresses. Alternatively, for a similar number of spare TSVs, the proposed method can enhance the fault tolerance capability of the conventional approaches thus leading to an enhanced chip yield. The eye diagram simulations using an electrical model of the TSV show a reduction of less than 5% in noise margin when using a 16-level voltage quantization at a data rate of 5 Gbps which is typical for 3-D integration applications.


I. INTRODUCTION
Semiconductor device scaling is aimed at performance enhancement by reducing the interconnect delays, increasing density and decreasing power dissipation [1]. Technology scaling is limited by several factors such as process The associate editor coordinating the review of this manuscript and approving it for publication was Cristian Zambelli.
variations, tunneling current leakage, increasing parasitics and interconnect power dissipation constraints [2], [3]. These limitations are hampering the continuation of the technology scaling trend. Three dimensional (3-D) integration offers a viable solution to overcome some of these problems and continue the integration trend [4]- [6]. 3-D integrated circuits (ICs) come with a variety of benefits such as higher density, reduced interconnect delays and low power VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see http://creativecommons.org/licenses/by/4.0/ operation. In addition, the 3-D ICs can help meet the increasing input-output (I/O) pins demand. Memory systems are becoming increasingly critical to the computing performance especially with the introduction of multi-core processor architectures. 3-D ICs, with short interconnects and more channels, can help achieve greater memory bandwidth to keep pace with the other factors in improving computing performance [5], [6]. The yield of 3-D ICs depends on the integrity of all the required TSVs. As presented in [7], with the increase in TSV count, there is a significant reduction in yield. The TSV fabrication process introduces tensile stresses in silicon and can result in undesired stress fields [8]. In addition to utilizing the silicon area, TSVs can be a major source of noise in the substrate which increases with the reduction in spacing between the TSVs [9]. The fabrication of TSVs requires additional components such as landing pads and bumps. All these factors limit the overall number and density of the TSVs.
TSVs are vulnerable to several faults introduced during the manufacturing process. These include misalignment, added impurities and random open defects [10], [11]. The pre-bonding test prior to die stacking is used to prevent the yield loss due to stacking of the faulty dies [12], [13]. A postbonding test is used to verify the stacked 3-D IC. Although the probability of failure in an individual TSV is low [14], however, without a repair mechanism, a single defective TSV can lead to the failure of an entire chip. Therefore, several TSV repair mechanisms have been proposed to improve the yield of 3-D ICs, thus saving the cost incurred due to yield loss [14]- [19].
The existing TSV repair architectures use multiple redundant TSVs to replace the faulty ones. In these architectures, a group of signal TSVs along with some redundant TSVs are used. The proportion of redundant TSVs in a group depends on the reliability of the manufacturing process. Not all the redundant TSVs are utilized in the repair process and many of the TSVs are reduced to mere additional metal lines in the substrate, a fact known as the inefficiency in TSV redundancy utilization [20]. Keeping in view the challenges posed by TSV based 3-D integration technology, we propose a TSV virtualization based repair architecture utilizing multi-bit transmission through a single TSV channel. With the proposed method, a single TSV can be used to repair multiple defective TSVs in a group. The proposed architecture offers a low cost and efficient TSV repair solution while reducing the overall TSV count, thus allowing greater interconnect density. Eye diagram simulations are performed to evaluate the impact of the proposed multi-level voltage quantization on the noise margins. Compared to the existing TSV repair architectures, the proposed architecture is efficient in utilizing the spare TSVs and also requires less area overhead.
The remainder of the paper is organized as follows. Section II summarizes existing TSV repair techniques. The proposed TSV repair architecture is presented in Section III. In Section IV, we present an evaluation of the proposed  [15]. (c) Signal shifting [14]. (d) Crossbar [7]. and (e) NoC type repair architecture [16]. architecture with results from the eye diagram simulation along with a comparison of the proposed method with conventional TSV repair architectures. Section V concludes the paper.

II. PREVIOUS WORKS
For TSV repair, most of the existing works require hardware redundancy architectures to enhance the yield of 3-D ICs [14]- [19], [21]. In these approaches, spare TSVs are included along with the signal TSVs and the faulty TSVs can be replaced with the spare ones to improve the overall yield during testing. The ratio of the spare TSVs to the signal TSVs in a group is decided based on the acceptable yield and the quality of the manufacturing process. A more reliable manufacturing process requires less number of spare TSVs (for a given number of signal TSVs) to be specified in design [20]. Figure 1(a) shows a generic TSV repair architecture consisting of n signal TSVs with m spares. The difference in various repair schemes lies in the rerouting architectures.
Rerouting can be implemented using either the fuse technology or switching [20].
TSV repair architectures can broadly be classified into either one dimensional (1-D) or two dimensional (2-D). In the 1-D repair schemes, TSVs are arranged in the form of a chain. Two popular approaches using this scheme are the signal switching [15] and signal shifting [14], shown respectively in Figure 1(b) and Figure 1(c). Switching is based on rerouting of the faulty TSVs to the spare ones without involvement of other working TSVs. In shifting, all the TSVs in group are shifted from fault location to the spare TSV. Signal switching requires less overhead for the rerouting logic and involves rerouting only the faulty TSVs but leads to greater timing imbalance.
In the 2-D repair approaches, the TSVs are arranged in the form of a grid. In [7], a 2-D crossbar architecture has been proposed, in which the signal TSVs and the spare TSVs are arranged in the form of a crossbar. Either rows or columns of spare TSVs are added in this approach. As the Figure 1(d) shows, a row of spare TSVs has been added. Through the crossbar, every spare TSV is linked to the signal TSVs in the corresponding column and it can repair any faulty TSV in that column by shifting the signals from fault location in the direction of the spare TSV. Another popular repair technique, among 2-D approaches, is a network-on-a-chip (NoC) type architecture proposed in [16], in which the faulty TSVs are repaired using the redundant TSVs that are farther apart. Signal rerouting to a spare TSV is achieved through a network of switches which are implemented using multiplexers. The NoC type repair architecture is shown in Figure 1(e). As shown in the figure, a switch can route the signal to either the working TSV in the absence of a fault or towards either East (E) or South (S) direction where redundant TSVs are located. This kind of repair approach is particularly useful for repairing the clustered faults since the faulty TSVs can be replaced by a group of spares that are located at a distance. However, the hardware overhead in this approach is large and many signals get re-routed even without faults leading to additional delays. In general, the 2-D repair techniques lead to greater yield, however, it may require more area overhead and routing complexity.
All the existing TSV repair approaches use multiple spare TSVs. The fact that many of the spare TSVs are not utilized highlights the inefficiency in existing approaches. Based on this observation, the authors in [20] proposed an online testing and soft error detection architecture for further enhancing the reliability of 3-D integrated circuits by utilizing the redundant TSVs that are left unused in the repair process. In this architecture, response compactors at the input and output of the TSVs are used for error detection. The redundant TSVs are used for transmitting the input side compactor's response to the output side for comparison.
Efficient utilization of the TSV redundancies and reduction in the TSV count are desirable to mitigate the TSV induced stresses and noise while still enhancing the overall yield. Less number of repair TSVs also allow for more signal TSVs to be incorporated in a 3-D IC, thus increasing the interconnect density. With this motivation, we propose the TSV virtualization based repair approach which can provide the same amount of repair capability with the reduced number of spare TSVs. With proposed architecture, the redundant TSVs are efficiently utilized. Additionally, the soft error detection mechanism proposed in [20] can still be applied for further enhancing the reliability of 3-D ICs.
A recent work [22] has introduced an adaptive faulttolerance structure generation method. In this method, a TSV repair structure is adaptively generated. It considers varying the fault-tolerance of TSV repair groups and assigning spares from a large number of candidates while minimizing the hardware-cost and efficiently utilizing the spare TSVs. The proposed vritualiztion-based TSV repair concept is applicable to the adaptive fault-tolerance structure generation methods such as [22] for more efficient utilization of the spare TSVs. As such, the proposed method enhances the fault-tolerance capability of an individual spare TSV and is, therefore, orthogonal to the conventional techniques which focus on effective spare TSVs placement topologies.

III. THE PROPOSED ARCHITECTURE
TSV virtualization is an idea of utilizing a single TSV to serve the purpose of multiple interconnects between different dies. It involves multi-bit transmission of data using a single physical channel. This technique can be used for low overhead TSV repair. In Section III-A, the idea of multi-level voltage quantization for TSV virtualization is discussed. The proposed repair architecture has been described in Section III-B. In order to evaluate the impact of proposed quantization technique with respect to noise margins, this work performs eye diagram simulations using an electrical model of the TSV. Section III-D describes the TSV model used for signal analysis.

A. MULTI-LEVEL VOLTAGE QUANTIZATION BASED TSV VIRTUALIZATION
TSV Virtualization for multi-bit transmission can be realized by using a digital to analog converter (DAC). The DAC converts n bit data into a single analog signal having n levels of voltage quantization. In this way, n-bit information is transmitted using a single TSV channel. On the receiving side, an analog to digital converter (ADC) converts the analog signal back to n bit data. Figure 2(a) shows the architecture for TSV virtualization using DAC and ADC and Figure 2(b) illustrates the idea of voltage quantization to send two-bit information using 4 levels. With the proposed TSV virtualization concept, a single TSV can be used in place of multiple TSVs. This helps to reduce the TSV count and improve the utilization of spare TSVs in a redundancy-based TSV repair architecture.

B. TSV VIRTUALIZATION BASED REPAIR ARCHITECTURE
The proposed TSV virtualization scheme helps in reducing the overall number of TSVs compared to the conventional approach. In the proposed repair architecture, the TSV count can be adjusted based on the application at cost of varying overhead. Figure 3(a) illustrates the generic architecture for virtualization based TSV repair. The comparison between the proposed architecture ( Figure 3(a)) and the conventional one ( Figure 1(a)), reveals the potential benefit of the proposed method. The requirement of m spare TSVs in previous approaches translates into just one TSV and m bit resolution of the DAC and ADC used for TSV virtualization. This leads to utilizing one spare TSV for repairing up to m failing TSVs in group of n TSVs. The rerouting logic for repairing the faulty TSVs can be implemented by using the pass transistor logic, fuse technology or multiplexers-based signal switching [16], [20], [23]- [25]. After identifying the defective TSVs, they can be rerouted to the spare TSV, thus improving the overall yield of the 3-D ICs. Unlike the conventional approaches, in the proposed architecture, there's less probability of a redundant TSV being left unused. However, with the presence of multi-bit DACs and ADCs, any online testing mechanism which makes use of the residual repair resources, such as that proposed in [20], can still be applied for enhanced reliability. The proposed architecture can be utilized in any of the configurations of the prior TSV repair architecture to address various kinds of faults including both the clustered faults and distributed random faults. The corresponding overhead for the rerouting logic would also be similar. The main benefit of the proposed architecture is a reduced number of spare TSVs and improved spare TSVs utilization in a repair architecture. However, the use of multi-level voltage quantization may impact the noise margins in the transmitted signals. Therefore, it is important to analyze the impact of proposed TSV virtualization on signal quality.

C. CHOOSING AN OPTIMAL CONFIGURATION
The choice of an appropriate value of n (TSVs in a group) and m (resolution of DAC and ADC) depends on the probability of defective TSVs and the tolerable overhead for implementing the DAC and ADC. This might vary depending on the application. Figure 3(b) shows an ideal scenario in which n equals m and the proposed method is used to reduce the number of signal TSVs as well as the spares. The shown example case uses only two TSVs for n signal TSVs and has a higher degree of reliability due to 100% TSV redundancy. It also uses a simple routing logic with only one 2-1 multiplexer. However, in some applications, it may not be economical to use a single TSV to replace a large group of signal TSVs at cost of high-resolution DAC and ADC circuit. In general, higher value of m increases the area overhead for implementation of corresponding DAC and ADC.
Another important factor that limits the value of m is the reduction in noise margin for the transmitted signal due to the multi-level voltage quantization. The noise margin also depends on the transmitted data rate and the TSV channel characteristics.
Eye diagram simulations are frequently used in communications to analyze the channel response in the presence of noise and inter-symbol interference. An eye diagram is obtained by overlapping various bit transitions. Such a pattern can be used for measuring noise margins and various timing parameters. In this paper, to analyze the decrease in noise margin by the proposed quantization technique, eye diagram simulations are performed using an electrical model of the TSV. A test input consisting of random bit sequence with random transitions to different quantization level is used. Eye diagrams are obtained by overlapping plots of the corresponding output response. The decrease in noise margins is measured by using the minimum eye openings corresponding to different responses. The electrical model of the TSV used for these simulations is discussed next.

D. TSV MODELING
To analyze the response of the TSV channel to an input signal, electrical modeling of TSV has been actively researched. Modeling is also important for designing of I/O channels in modern 3-D integrated circuits. Various equivalent electrical models of the Through Silicon Via have been proposed in the literature [26]- [29]. To evaluate the impact of the proposed method on noise margins, we use the electrical model of TSV proposed in [26] which is experimentally verified. It's a high frequency scalable electrical model which considers most of the parasitic components associated with the TSV as well as the interconnecting bumps and redistribution layer (RDL). The bumps act as joints for the TSV while the purpose of redistribution layer is to distribute the signals over different locations [26]. As these are essential components in 3-D ICs, it is necessary to consider them in electrical modeling of the TSV. By using the analytic RLGC equations for the given model, the value of different patristics can be obtained. Additionally, using the equivalent electrical circuit, the TSV channel response to a given input can be analyzed.
To verify the response of TSV channel with the proposed quantization technique, we consider a ground and signal TSV pair along with a redistribution layer (RDL). Figure 4(a) and 4(b) respectively show the cross-sectional and the side view of the TSV and RDL schematic used in simulation. Figure4(c) illustrates the detailed dimensions of the TSV, bump and RDL. These dimensions have been adopted from [26]. The equivalent electrical circuit for this model is VOLUME 8, 2020 shown in Figure 5. The modeling of various parameters of the TSV using equivalent electrical components, is summarized next.
TSVs are electrically isolated from the silicon substrate through a silicon dioxide (SiO 2 ) insulation layer. This is equivalently modeled by C insulator capacitance which can be expressed using the coaxial-cable capacitance model. At the bottom end of the TSV, the capacitance between the bump and substrate, represented as C Bump , is added to the C insulator . C Bump can be derived using parallel plate capacitance model. The two capacitances namely the C imd and the C bottom , represent the capacitances between the signal and ground TSVs through the top inter-metal dielectric (IMD) layer and the bottom silicon dioxide (SiO 2 ) insulation layer. These are modeled using the parallel wire capacitance model. Using the same principle the capacitance between the bumps through the underfill layer is modeled as C underfill . The capacitance and conductance between the TSVs through the silicon substrate are modeled as C Sisub and G Sisub , respectively, using the parallel wires model. The resistances of both the TSV and the bump are given as R TSV and R Bump , respectively. The derivation of these resistances takes the skin effect due to alternating current into consideration. At high frequencies, the inductance impedance becomes prominent, therefore it is necessary to consider the inductance of the TSV and bump modeled as L TSV and L Bump .
In a manner similar to that described for the TSV, various parameters associated with the redistribution layer (RDL) are modeled as C RDL , L RDL , R RDL , C sub and the G sub . Material properties used in the calculations have also been adopted from [26].
The aforementioned electrical model is used for the eye diagram simulations (discussed in next section) to evaluate the impact of proposed voltage quantization on noise margins.

IV. EVALUATION
We use eye diagram simulations to confirm the viability of the proposed architecture and to analyze the reduction in signal noise margin by the proposed multi-level voltage quantization. We also evaluate the various aspects such as yield, number of TSVs and area overhead for the proposed method compared to the conventional TSV repair approaches.

A. EYE DIAGRAM SIMULATIONS
Eye diagrams are helpful in analyzing a communication channel's response. The signal degradation and noise margin can easily be estimated from the eye patterns. For the proposed method of multi-level voltage quantization, eye diagram simulations have been performed to measure the expected reduction in noise margin. To obtain the eye diagrams, the electrical model shown in Figure 5 is used. With the dimensions given in Figure 4(c), the values of various circuit elements are calculated by using the RLGC equations in [26]. The test input consists of random bit sequence of 20 Kbits. Four different transmission schemes are considered i.e. 1-bit, 2-bit, 3-bit and 4-bit using 2, 4, 8 and 16 levels of quantization, respectively. The input eye diagrams have been shown in Figure 6. These eye diagrams are obtained by overlapping multiple input transitions. For each input to the test model of the TSV, there's a corresponding output transition. Output eye patterns are obtained by overlapping the output responses. Figure 7 shows the corresponding output eye diagrams against the test input. Different diagrams are obtained by varying the input data rate between 1 Gbps, 5 Gbps and 10 Gbps. By measuring the minimum eye opening in each case, the corresponding noise margin is estimated.
As Figure 7 shows, the noise margin from eye diagrams decreases as multiple bits are transmitted by using more number of levels for voltage quantization. Furthermore, it is  observed that the reduction in noise margin is proportional to the input data rate. The measured values of minimum eye openings for different cases are listed in Table 1. The reduction in noise margin when employing multi-bit transmission, compared to the single bit transmission using 2 levels, is also listed in the table. By varying the input data rate as well as the V dd voltage level, different measurements are obtained. As seen from Table 1, for the input data rate of 1 Gbps, the reduction in worst-case noise margin remains below 0.25% as the V dd voltage varies from 1.2 V to 2.1 V. The results also show that altering the V dd voltage does not significantly impact the noise margins. A slight improvement in noise margin is observed for higher values of V dd . Increasing the data rate, however, causes a more significant decrease in the noise margin. At the input data rate of 10 Gbps, the eye opening and hence the noise margin decrease from about 97.5% for 2-level voltage quantization to a minimum of 61.3% for 16-level voltage quantization. Therefore, the maximum reduction in noise margin is about 36.2% at a data rate of 10 Gbps. Considering 4-bit transmission with 16 voltage levels, the noise margin reduction remains below 5% for the data rate up to 5 Gbps, which shows possibility of transmitting even more bits at this data rate.
For a practical application, we consider the TSV-based 3-D DDR4 SDRAM presented in [30]. The IO speed of the 3-D SDRAM is 2.4 Gbps at a supply voltage of 1.2 V. Based on our experimental results, for this memory, the proposed TSV repair architecture can easily be incorporated with a 16-level voltage quantization with less than 5% reduction in noise margin. With a data rate below 5 Gbps, even higher levels of voltage quantization can be used to reduce the overall redundant TSVs and enhance the efficiency of the repair architecture.
The results from eye diagram simulations confirm that the proposed multi-level voltage quantization technique is viable for efficient TSV repair. The reduction in noise margins is within acceptable range for practical implementations. The number of levels used, depends significantly on the data rate. The other factors include characteristics of the TSV channel and the acceptable overhead for DAC and ADC. Therefore, based on application, different variants of the proposed TSV repair architecture may be considered.

B. COMPARISON WITH CONVENTIONAL TSV REPAIR ARCHITECTURES
In comparison with the conventional schemes, the proposed virtualization-based TSV repair architecture decreases the number of spare TSVs for a given level of reliability. Alternatively, for the same number of spare TSVs, by increasing the virtualization, the proposed architecture can have increased fault tolerance capability. However, if the TSV count is kept same, the proposed architecture would require additional cost of ADC and DAC. Different topologies for placing and routing spare TSVs, such as the ones shown in Figure 1, can be considered with the proposed virtualization method. This architecture can cover both the clustered faults as well as the random faults. Considering a similar overhead for rerouting logic, we next compare the proposed architecture with conventional approaches in terms of yield and hardware cost. Since the proposed architecture can be used in any of the configurations of the existing repair architectures, we compare the proposed method with the conventional methods in terms of number of TSVs, chip yield and area of TSVs and DACs / ADCs.

1) YIELD ANALYSIS WITH RESPECT TO NUMBER OF TSVs
The proposed architecture can reduce the TSV count for a similar level of TSV repair capability as the conventional TSV repair architectures. Alternatively, with a fixed number of signal and spare TSVs, the proposed method can improve the fault tolerance of the repair architecture by using multi-level voltage quantization. Increasing the number of faulty TSVs handled by a repair approach can enhance the chip yield. To analyze the impact of proposed multi-level voltage quantization on chip yield, we consider a probabilistic model. The failure rate of a TSV has been reported to be 10 −4 to 10 −5 [20]. Considering a failure rate of 10 −4 , we analyze the chip yield for different schemes assuming that a single spare TSV is used for repair. The results are shown in Figure 8. In the figure, Virtualization-n indicates an n-bit virtualization scheme in which 2 n voltage quantization levels are used. Figure 8 shows that for a given number of TSVs, the proposed method can considerably improve the yield compared to conventional methods. For example, with Virtualization-4 scheme, the proposed method has more than 99% yield for over 12K TSVs. For the same number of TSVs, the conventional repair methods achieve only 63% yield (36% less). This analysis also shows that for a given level of yield requirement, the proposed method can allow more signal TSVs to be used by simply increasing the level of voltage quantization. The area overhead by increasing the virtualization level will not be as significant as adding more spare TSVs with additional routing logic. For a given target yield, a Virtualization-n scheme requires n times less spare TSVs. The reduction in TSVs also reduces the area overhead as discussed next.

2) COMPARISON OF AREA OVERHEAD
Reduction in TSV count by the proposed virtualization architecture comes at cost of overhead for DAC and ADC circuits. We compare the chip area of conventional TSV repair architectures to that of the proposed architecture based on the prior works on practical TSV-based 3-D ICs and efficient implementations of ADC and DAC circuits. Exploring efficient implementations of a DAC or an ADC is beyond the scope of this research and there has been much research about efficient implementations of DAC and ADC [31]- [36]. We therefore refer to the existing works on practical implementations of DACs and ADCs. Although different technology nodes are considered for practical implementations, however, in comparing the area overhead, we adopt a conservative approach, in which 180nm technology is considered for the DAC circuit in the proposed architecture and a 50nm technology is considered for TSVs in the conventional architectures.
In practical 3-D ICs, TSVs are usually placed to form a grid with a minimum pitch (distance between two TSVs) requirement. Area overhead by the TSVs, therefore, depends on the pitch which varies depending on application. Considering a practical 3-D DDR3 DRAM using 50nm node DRAM process, presented in [15], the TSV pitch is 80µm. With this pitch, the footprint area overhead per TSV is 80 × 80µm 2 . Considering the fact that the TSVs are normally arranged in a grid, the overall volume of a 3-D TSV grid can be even higher. Nevertheless, reducing 1 TSV leads to at least 80 × 80µm 2 area saving in each of the dies stacked around TSV, providing room for proposed DAC and ADC circuits. The silicon substrate around TSVs, which is wasted because of minimum pitch requirement, can otherwise be used for useful logic in stacked dies. Although a practical implementation of the proposed architecture may use multiple smaller resolution DACs and ADCs, yet for the sake of area comparison we consider a 10-bit DAC presented in [32]. The 10-bit DAC in [32], using 180nm process technology, has a total die area of 110 × 94µm. A 6-bit ADC based on [31], using 40nm process technology, has a die area of 0.00058mm 2 . With a 10-bit DAC in the proposed architecture, 10 spare TSVs can be replaced by a single TSV. This would require an area overhead of 0.01674mm 2 . The corresponding area overhead for 10 TSVs is 0.064mm 2 , showing a reduction of 74% in area overhead by the proposed architecture. It should also be noted that 180nm technology for the DAC circuit is considered. The area overhead for DAC would be even less when considering the DRAM technology node which is below 65nm. A similar analysis shows that the 6-bit ADC circuit of [31] along with a single TSV requires 82% less area compared to 6 TSVs in a conventional repair architecture. The DAC and ADC area is compared separately because reducing each TSV leads to less footprint area in two stacked dies, which can be used for DAC and ADC circuit. Considering the area comparison based on 10-bit DAC, Figure 9(a) compares the area overhead of the proposed architecture against that of the conventional TSV repair architectures with increasing number of spare TSVs. The practical 3-D DDR3 DRAM [15] considered for area comparison has 150 spare TSVs. With 150 spare TSVs, the proposed architecture requires 74% less area overhead.
Area overhead for the conventional TSV repair architectures depends on the TSV pitch. The above comparison considers TSV pitch of 80µm, based on the practical DDR3 DRAM. However, if the pitch is very small, the area overhead for the proposed ADC and DAC may be dominant. Figure 9(b) compares the area overhead by varying the TSV pitch. In this comparison, the number of spare TSVs is fixed at 150 while the TSV pitch is varied from 10µm to 100µm. The results show that the proposed architecture reduces the chip area compared to conventional TSV repair architectures when the TSV pitch is more than 33µm. With more recent technology, TSV pitch could be even smaller to offset the hardware cost of ADC and DAC in the proposed architecture.

3) TIMING OVERHEAD
The use of DACs and ADCs in the proposed TSV repair architecture introduces additional timing overhead for conversion from digital to analog and analog to digital. However, for typical applications such as a 3-D memory, with the sampling rate of DACs and ADC of a few Gs/s, the latency would not be critical. This is especially true for the emerging memory technologies that have considerably higher access latencies compared to conventional memories. Moreover, the additional latency can be completely hidden when data buffering is used which is typical in practical memory systems.

4) POWER AND ENERGY OVERHEAD
Using the electrical equivalent model of TSV considered in this work, the power dissipation and propagation delay for VOLUME 8, 2020 TSVs have been estimated in [37]. Based on these estimations, Cu-based TSVs dissipate a few µW power and the equivalent energy is of the order of 10 −16 ∼ 10 −17 J. Depending on implementation, ADC and DAC [31]- [36] have conversion energies ranging from a few fJ/conversion-step to a few tens of fJ/conversion-step. Although, the conversion energy of ADC and DAC is higher compared to energy dissipated by the TSVs, however, a part of this energy overhead is compensated by the reduction in number of TSVs (from hundreds to tens) using the proposed TSV repair architecture. Moreover, the energy overhead would be added only when the data is transferred between different dies of a 3-D IC and for those TSVs groups where faulty TSVs have been repaired.
Considering practical 3-D ICs such as high-density memories, depending on the memory technology, the per bit programming energy varies from a few fJ to tens of pJ [38]. Emerging memory technologies such as a multi-level cell Phase Change Memory can have per cell programming energy in hundreds of pJ [39]. Considering the overall programming energy for a large number of bits, the overhead of the ADC and DAC conversion energies would be negligible.

V. CONCLUSION
Hardware redundancy is the widely used approach to improve the yield of 3-D integrated circuits. Spare TSVs are used to replace the failing TSVs. The existing repair architectures require several redundant TSVs, thus causing greater TSV-induced stresses and noise. Many of the spare TSVs are not utilized during the repair process. We introduce a new TSV repair architecture based on the TSV virtualization to transmit multiple bits through a single TSV using multi-level voltage quantization. Using the proposed repair technique, a single redundant TSV can be used to repair multiple failing TSVs in a group. This leads to an efficient utilization of the TSV redundancy, thus avoiding the existence of unused spare TSVs in a working chip. It can help improve the interconnect density and also mitigate the TSV-induced stresses and noise. Depending on the application, data rate and the characteristics of the TSV channel, the resolution of voltage quantization can be adjusted. The results from eye diagram simulations show less than 5% decrease in noise margin at a data rate of 5 Gbps He has been with the SoC Design Team, Samsung Electronics, South Korea. He is also a part of the team developing high performance CPU and GPU for Samsung mobile SoC products. His research interests include high-performance processor architecture, low power CPU and GPU implementations, high-bandwidth memory, and reliable architectures for emerging memory technologies.