Analysis of Logic Gates for Generation of Switching Sequence in Symmetric and Asymmetric Reduced Switch Multilevel Inverter

Analysis of logic gates for the switching sequence operation of reduced switch multilevel inverter (MLI) is introduced in this paper. Two variants of MLI with reduced switches are considered for the analysis of the logic gates to obtain proper output voltage level. One MLI is with the symmetrical voltage, and the other is with the asymmetrical voltage. The analysis of the proposed logical operation is presented through the single-phase seven-level output voltage for both symmetrical and asymmetrical inverters. Input pulse pattern for the operation of the logic gates are chosen from the multi carrier pulse width modulation (PWM) techniques as phase disposition (PD), phase opposition disposition (POD), and alternate POD (APOD). The analysis for the generation of the required pulse pattern to operate the switches in MLI is presented as logical equations. The simulation work is performed and evaluated with the MATLAB/Simulink. The real-time simulation is performed for the required pulse pattern and generated with the support of dSPACE 1104. The THD comparative analysis is analyzed with a modulation index and various PWM methods.


I. INTRODUCTION
Binary logic consists of various logical operations which represent a logical meaning for various conditions based on the output of systems. In many computer and processor operations, computational analysis and decision making systems, binary logic operations play the key role for system control. Binary logic mainly depends on two values with different names like 'True and False', 'Yes and No', 'On and Off' etc. In this paper, the values with '1' and '0' are preferred for convenience. '1' assigned for 'On' condition of the switch and '0' assigned for 'Off' condition. The combination of binary logic and a proper logical operation called Boolean algebra.
Boolean algebra basically consists of three logical operations, which are called basic logic gates: AND, OR and NOT. Each logical operation produces a binary output based on their operation presented as truth table in Table 1 for two input signals. These logic gates are electronic circuits which The associate editor coordinating the review of this manuscript and approving it for publication was Yang Han.  operate on two or more input signals and generate desired output based on the logical operation except NOT gate. NOT gates operate with one signal and its truth table is given in Table 2. Input signals may be a communication signal, electrical voltage or current signal, etc. The output signal of the logic gates are used to On/Off a switch in the proposed work. An exclusive gate is available for the critical situations of the switching operations. EXOR and EXNOR gates are mostly used for the operation of switches and the truth tables are given in Table 1 for both. OR gate is represented with '' +'', AND gate with '' •'', NOR gate with ''+'', NAND gate with ''•'', EXOR gate with '' ⊕ '', EXNOR gate with '' '' and NOT gate with '' − '' [1].
Several Reduced Switch Multilevel Inverters (RSMLI) are proposed to achieve the cost minimization, optimal voltage stress, reduced power losses, frequency operations, less harmonic distortions. Cascaded H-Bridge, Neutral Point Clamped, Diode Clamped, and Flying Capacitors are the Conventional MLI. Operation of these conventional MLI's are performed with the support of gating signals (Pulses) to the power switches of respective inverter design [2]. Generation of gating signals is achieved by various pulse modulation techniques. Different pulse modulation techniques are proposed by researchers for the operation of MLI. Control and estimation of switching losses and the total harmonic distortion is obtained by modulation techniques [3], [4]. Switching frequency is an important criterion for the operation of MLI. Based on the value of frequency modulation, techniques are categorized into two major types. Fundamental frequency with less number of cycles and high switching frequency has repeating signal per cycle.
The sequence of switching operation of various RSMLI's are presented in many research works with one of the modulation methods. But, to obtain the required sequence of the pulse pattern is a critical part of the presented works. Level shifting and phase shifting multi carrier sinusoidal PWM methods are widely used in the previous works [3], [5], [6]. Obtained pulse pattern from the traditional modulation method is not exactly matching with the required pulse pattern of MLI operation. To achieve the required pulse pattern, basic logic gates are used and convert the generated pulse pattern to the required pulse pattern. Analyzing the logic gates for the generation of the required pulse pattern is the major task of the MLI operation. Using the logic gates for the operation of various MLI's are not properly explained in many researchers work [7]- [16].
Design of multilevel inverter with reduce switch is the novel content of many researchers. To obtain the desired output voltage level of reduced switch MLI, a different type of switching operations are performed for the switches.
Microcontrollers, microprocessors, real-time simulators are used for the switching operation [17]- [22]. Among these methods, the boolean algebra and logic gates are preferred for the operation of switches in this work as per the switching sequence is shown in Table 4 and 5 [23], [24]. This paper is organized into six sections as, multilevel inverters in section 2, Pulse width modulation methods in section 3, Analysis of logical equations for switching operations in section 4. The results obtained from MATLAB/ Simulink and dSPACE 1104 for proposed work are presented in section 5 and section 6 which conclude the present work.

II. MULTILEVEL INVERTER
The inverter is a power electronic circuit which can convert AC to DC with a basis of two level voltages. The basic inverter is having many issues with its distortion factors, switching losses, and less efficiency. To overcome these issues, multilevel inverters are designed and analyzed by many researchers to provide better features. In the early decades, the integration of inverted power from many power electronic applications is difficult because of distortions in the converted power. The problems causing due to the voltage and current distortions, multilevel inverters are highly preferable from the family of power electronic circuits [25]- [27]. The multilevel inverter is having a starting level with three voltage values. Multilevel inverters have been preferred with various levels like 3, 5, 7, 9, 11, 27, etc. Multilevel inverters are having many features and are mostly required for the domestic, commercial and industrial applications based on the selection of voltage and connectivity.
Based on the operation of the multilevel inverter, three topologies have been presented in many research works. Diode clamped and flying capacitor are operated with single DC voltage source and Cascaded Multilevel Inverter (CMLI) is operated with (L-1)/2 DC voltage sources where 'L' is the level of CMLI. Usage of power semiconductor switches, numbers of DC sources, linear and nonlinear elements are more as given in Table 3. To perform the specified and desired operation of the selected multilevel inverter, various modulation methods have been analyzed [28]- [30].
Many researchers are working on the reduced switch multilevel inverter. Among many researchers work, the most reduced switch multilevel inverter is preferred. Based on observations, 5 switch seven level multilevel inverter [24] and 8 switch seven level multilevel inverter [23] is considered for the research work.    Figure.1(a) and 8 switch seven level multilevel inverter is shown in Figure.1(b). 5 switch seven level multilevel inverter is with four symmetrical DC voltage sources. Three switches S 1 , S 2 , and S 3 are doing an operation of level shift for the output voltage. Switches S 4 and S 5 are operating for the positive half cycle and negative half cycle which leads to the generation of AC voltage and current to the load. 8 switch seven level multilevel inverter is structured with two asymmetrical DC voltage sources. If the first voltage source is of V volts, then the second voltage source should be the double of the first voltage source (2V). Switches S 1 , S 2 , S 3 , and S 4 are used for the positive half cycle and negative half cycle operation of the output. Switches S 5 , S 6 , S 7, and S 8 are presented as DC link module for the operation of output level shift. Switching sequences of both the inverters are given in Table 4 and 5.    Multiple carrier modulation techniques are divided into level shifting and phase shifting techniques. Level shifting technique is divided into constant switching frequency multi carrier signal and variable switching frequency multi carrier signal techniques. PD, POD, and APOD are the subdivisions of switching frequency techniques.

III. PULSE WIDTH MODULATION TECHNIQUES
In this work, a sinusoidal modulating signal for SPWM with triangular multi carrier signals are used to produce     shown in (2) and (3) [29].
For the operation of seven level multilevel inverter, (7-1) carrier signals are considered. Six triangular waveforms as carrier signals with amplitude of 1 for each signal. Switching frequency equals to the carrier signal frequency. The relational operator is used for the comparison of the modulating signal and carrier signal to produce pulses. Modulating signal TABLE 11. Binary representation switching operation for S 4 and S 5 in 5 switch module. and carrier signal arrangement is shown in Figure 2. Pulses generated are equals to the number of carrier signals. The number of pulses produced are six which are not equal to switch count. It's a challenge to operate the switches to produce proper output with the available pulses. For 5 switch module, more pulses are present and for 8 switch module, fewer pulses are present which is not in the required switching sequence. To operate these switches, the basic logic gates are considered for the operation and are presented in the design of logical equations section.

IV. LOGICAL EQUATIONS FOR SWITCHING SCHEME
As explained in the previous Section, L-1 numbers of carrier signals are needed for L level output voltage. For 7 level output voltage, 6 triangular carrier signals are needed. For 7 level output voltage of MLI, the total time of one cycle is to be distributed for one cycle of 7 level output voltage as shown in Figure. 3. The total number of divisions per cycle and time interval of each division is given in (6) and (7).
In many research works for the reduced switch multilevel inverter, the switching sequence pattern is provided for the successful operation of the proposed work for obtaining the outputs as expected. But, the generation of the pulse pattern which is required for the switching sequence is not provided. The technical explanation and the logical relation between pulses generated by the PWM method and pulses required for the switching sequence are properly presented in this section.
With the help of binary representation of pulse pattern for 6 triangular carrier signals and zero carrier signal are shown in Table 6 and 7. For the generation of pulses required for  the switching, the sequence is the main objective. Use of logical gates is the major role for switching sequence pulse generation. In this section, various conditions are considered  as a case. Each case provides a proper logical operation of the system to produce a proper pulse for the switch. In order to explain logic equations for 5 switch module and 8 switch module, the switches S 2 and S 6 have been chosen.

A. LOGICAL EQUATION FOR SWITCH S 2 IN 5 SWITCH MODULE
In this analysis, one full cycle is considered. The time duration of one full cycle equals to the time duration of the modulating signal. For this proposed work, the sinusoidal modulating signal time period is 0.02 seconds for one cycle i.e., frequency of 50Hz. Carrier signal frequency is 1.5KHz. One full cycle is the combination of a positive half cycle and negative half cycle with time duration of 0.01seconds each. Positive half cycle starting period is 0.00 and the ending period is 0.01seconds and the negative half cycle starts at 0.01 and ends at 0.02 seconds. Application of the logical gate is considered for each half cycle as per the switching sequence. Finally, both half cycle operations are logically combined for the final switching sequence. Operation of switch S 2 in 5 switch module is expressed in the following steps.
Step 1: All obtained pulse patterns are expressed in binary representation form as shown in Table 6.
Step 2: For seven level output, 16 stages of time duration is considered. 1 to 8 stages are for the positive half cycle and 9 to 16 stages are for the negative half cycle. Each stage time interval is 0.00125seconds.
Step 3: Observe the positive half cycle binary representation of switching sequence S 2 . Use the required pulses from the binary representation of pulse pattern. P 2 and P 3 are the required pulse pattern for the positive half switching sequence of S 2 with the EXOR gate.
Step 4: Similar to the positive half cycle of S 2 , the negative half cycle switching sequence is obtained with the EXOR gate of pulse pattern N 2 and N 3 .   Step 5: Total switching sequence of switch S 2 is obtained by the OR gate of two switching sequences obtained from step 3 and step 4. The resultant logical equation for switching sequence S 2 is given in (8). Binary representation operation is shown in Table 9.
Similarly, logical equations for switch S 1 , S 3 , S 4, and S 5 have obtained the step by step operation as presented for switch S 2 . Binary representation operation of switches S 1 , S 3 , S 4 and S 5 are given in Tables 8, 10 and 11 respectively. Resultant logical equations of switches S 1 , S 3 , S 4, and S 5 are given in equations (9), (10), (11), and (12). Individual switch logic gate representations are shown in Figure.4. Switch S 5 is directly connected with pulse pattern P 1 , no logic gate representation is presented.   operation of 8 switch module. Required operation of switch S 6 is presented with the support of binary representation.
Step 1: The binary representation of all pulse patterns is to be expressed along with the pulse pattern of the zero sequence carrier signal shown in Table 7.
Step 2: Positive half cycle of switching operation is obtained with the combination of three pulse patterns. EXOR combination of P 1 and P 2 , then the output is combined with P 3 to obtain the switching sequence operation for the positive half cycle of switch S 6 . Combination of P 1 and P 2 with EXOR gate is used for the operation of switch S 7 .
Step 3: For the operation of switch S 6 negative half cycle pulse patterns N 1 and N 2 are combined with EXOR gate then, its output is combined with N 3 . The output of a sequence of EXOR gate with N 1 and N 2 is used for the negative half cycle operation of switch S 7 .
Step 4: Complete switching sequence of switch S 6 is obtained by EXNOR of the positive half cycle and negative half cycle switching sequences which are given in the above two steps. Resultant logical equation of switching sequence for switch S 6 is given in (13) and represented in Table 15.
Step 5: Switches S 1 and S 2 are operated for the response of the positive half cycle. S 3 and S 4 are for the negative half cycle. Switching sequence of these switches are obtained by  zero sequence carrier signal which provides a pulse pattern of PN 0 and PN 0 .
A similar method of logical analysis is applied as given in the above steps to obtain the logical equations for switch S 1 , S 2 , S 3 , S 4 , S 5 , S 7, and S 8 . Resultant logical equations are given in (14), (15), (16), (17) and (18). Binary representation operation is given in Tables 12, 13

V. RESULTS
Operation of 5 switch module is performing with the help of seven pulse pattern obtained by multi carrier PWM method. A major task of the proposed work is to obtain the pulse pattern for switches of reduced switch multilevel inverter.
Obtained pulse patterns are more in number as compared with the 5 switch module and less in number as compared with 8 switch module. The selected switch is operated as switching sequence pattern presented in Tables 4 and 5. Pulse pattern has to match with the switch sequence pattern to generate the desired level output of the multilevel inverter.
Analysis to obtain the logical equations for the 5 switch module and 8 switch module is explained in section 4. Generation of basic pulse patterns from multi carrier PWM is shown in Figure 7 and 8. Results of switching sequence pulse pattern for 5 switch module and 8 switch module are shown in Figure 9 and 10. All presented results in this work are   Figure. 6. 5 switch module is symmetric MLI with input DC voltage of 90V each. Four input voltages sources are used for the operation of 5 switch module to obtain 7 level output voltage for R load of 100 . A result of 270V Peak is obtained with the simulation of the proposed MLI and the switching control operation by logic gates. 8 switch module is asymmetric MLI with two input DC voltages. V 1 is with the voltage of 72V and V 2 is with 144V. 7 level output voltage of 216V peak is obtained with the simulation of 8 switch module for R load of 100 .
Comparative THD analysis of 5 switch module and 8 switch module are presented with respect to various modulation index values for APOD, POD, and PD PWM methods. Obtained %THD values of the two proposed modules are clearly mentioned in Table 17 and 18. As per IEEE 519 harmonic distortion standards, the allowable %THD is of 15 to 25% without a filter in the inverter design. The modulation analysis of switching sequence is obtained for THD values which are less by 6% in the case of over modulation. The least harmonic content of 0.52% in resultant voltage is achieved. THD values provided in Table 17 and 18 are the values generated without a filter of the proposed design. If the proposed modules are operated with filter, then they may achieve better results than the previous condition. Based on IEEE 519 standards, 5%THD is allowed for the inverter design with filter. To obtain better results, the designing of the filters are to be focused for the proposed inverters. FFT analysis of the 5 switch and 8 switch module under APOD PWM method is given in Figure 11 and 12 for the output voltage. 5 switch symmetric module and 8 switch asymmetric module are operated with R load. The resultant peak voltage VOLUME 7, 2019 of 270Volts for 5 switch module and peak voltage of 216Volts for 8 switch module are obtained with a constant fundamental frequency of 50Hz. The input voltage, switching frequency, modulating frequency, output RMS voltage, current and power of the proposed modules are mentioned in Table 19.

VI. CONCLUSION
In this study, a new analysis is proposed for the operation of various reduced switch MLI with the logical gates. The proposed analysis of logical operation is flexible and reliable for the various reduced switch MLI inverter with seven level output voltage. Generated pulse pattern from the analysis is most relevant for the operation of switches based on the switching pattern of the MLI. Main constraints of the proposed work are to present the pulse pattern of multi carrier PWM in binary representation form and analyzing with the basic logic gates to obtain the logical equation for each switch in MLI. Proposed analysis can also be applied for various MLI circuits which are not in this work. This analysis is most useful for the researchers who are presenting their work on novel reduced switch MLI. The simulation work done with MATLAB/Simulink is presented for the considered MLI with their THD analysis. Real time simulation is performed for the generation of pulse pattern of the switching sequences with the help of dSPACE 1104. All obtained results and THD values are compared with various multi carrier sinusoidal PWM methods with respect to various modulation index. Results obtained are satisfying the IEEE 519 standards of the harmonic content.