A Novel Submodule Voltage Balancing Scheme for Modular Multilevel Cascade Converter—Double-Star Chopper-Cells (MMCC-DSCC) Based STATCOM

A novel capacitor voltage balancing scheme for modular multilevel cascade converter—double-star chopper-cells (MMCC-DSCC)-based STATCOM is proposed in this paper. Compared with the conventional software voltage balancing methods, the proposed scheme has three main advantages. First, only six voltage sensors are needed, and other voltage sensors have been removed. Then, the control framework can be simple without sort and select process, or some balancing control loops. Additional delay process caused by the sampling and control signals transmission is also mitigated. Finally, the faster capacitor balancing speed can be obtained. In addition, compared with some other hardware voltage balancing schemes, there are superior characteristics in terms of the reduced number of switches and only the popular power modules in the additional units are applied. For these additional modules, the parameters design guide of the proposed scheme has been discussed. Verified results from the 13-level simulated system and 9-level experimental platform for the MMCC-DSCC based STATCOM show the effectiveness of the proposed scheme. By the proposed scheme, both DC capacitor voltage balancing control and reactive power compensation are simultaneously realized for the MMCC-DSCC-based STATCOM even in balanced and unbalanced load.


I. INTRODUCTION
With the development of medium and high voltage converters, it raises a series of harsh requirements for the high-power converters. Modular Multilevel Cascaded Converter (MMCC) has many advantages such as modularity, scalability, high fault-tolerant ability, and so on [1], [2]. Consequently, MMCC has been considered as one of the most attractive topologies for HVDC [3]- [5], high-voltage voltage source converter (VSC) [6], [7], active power The associate editor coordinating the review of this manuscript and approving it for publication was Tariq Masood. filter (APF) [8], [9], STATCOM [10], energy storage system [11], [12], and so on.
As one of the most important applications for reactive power compensation, Modular Multilevel Cascade Converter -Double-Star Chopper-Cells (MMCC-DSCC) based STAT-COM is gaining much more attention to generate the dynamic reactive power, improve power factor and power quality of grid [13], [14]. For the STATCOM, a lot of studies have been conducted on various improvements about the operation performance [15]- [17].
For MMCC-DSCC based STATCOM, the capacitor voltage balancing control for the floating submodules (SMs) 83058 This work is licensed under a Creative Commons Attribution 3.0 License. For more information, see http://creativecommons.org/licenses/by/3.0/ VOLUME 7,2019 in each arm remains to be a challenging issue, which is a common problem in the multilevel converters [18]. The mainstream of the balancing method can be divided into three categories, an additional injection of modulation wave for each SM, voltage sorting and select methods, and hardware balancing schemes. For the first category, reference [19]- [22] inject an additional component to the modulation wave of each module according to the voltage derivation of capacitors from the voltage reference. Reference [23] reveals the quantitative relation between the capacitor voltage of SM and other operating parameters. Based on this, the additional injection is calculated and injected to balance the capacitor voltages according to the equation derived in this paper. Another voltage balancing method switching at grid frequency is proposed [24]. By assigning the low-frequency pulses with different pulse widths, the charges of the capacitor are controlled for keeping the capacitor voltage balancing in MMCC-DSCC. Furthermore, reference [25] manages to decouple the SM capacitor voltages balancing process from the DC bus voltage balancing. The SM voltage is controlled with a better result than traditional balancing control methods. However, these methods introduce the feedforward of capacitor voltages in the modulation, which lowers the voltage utilization of modulation wave [26].
For the second category, reference [27] propose the hierarchical control method. All SMs in one arm are grouped, and the sorting algorithm of the voltage balancing in each group is implemented in a decentralized control unit, and the balancing between different groups is realized by an additional injection component. To lower the computation burden of conventional model predictive control (MPC) method reference [28] and [29] propose an improved MPC based sorting and balancing approach which reserves the system performance, especially in high voltage systems. On the basis of these two papers, a priority sorting approach based on simplified MPC is proposed for MMCC in reference [30]. Reference [31] proposes an improved balancing approach based on space vector pulse width modulation (SVPWM). This method simplifies the complexity of balancing control by avoiding the sorting algorithm of all the voltages in one arm. The comparison between different modulators is further performed [32]. It also discusses the priority of each modulator. However, the relationship between sorting frequency and switching is not discussed in detail. Therefore, an adaptive method is proposed to achieve a trade-off between the switching losses and the balancing effect through closed-loop control of the alternating number of the SMs [33]. Reference [34] further proposes an improved balancing method based on the estimation of the current direction, which reduces the current sensors. Despite the flexibility and widely application of software balancing methods, the number of voltage sensors, the extra calculation burden and the signal delay caused by sampling and transmission is still the disadvantage of the software balancing methods. In order to decrease the number of voltage sensors and reduce the influence of control delay, hardware balancing methods are gaining popularity [35]- [39]. A simple and low-loss capacitor static voltage balancing method based on self-power supplies is adopted in [35]. Considering the influence of self-power supplies on capacitor voltages, this method can keep the capacitor static voltage balanced by controlling the input characteristic of the self-power supplies. However, this method increases system cost with an additional controller on self-power supplies. In [36], a diode-clamped MMCC topology is proposed, the balancing control between the first and the last module in each arm is realized through an additional transformer. The control of the additional transformer requires a certain resource for this control system, and this will enlarge the volume of the whole device. Based on this paper, reference [37] proposes a parallel-connected improved diode-clamped topology where each arm is composed of two parallel clusters. The rated current of the topology also increases at the same time. However, the structure is much more complex where more switches are needed. In [38], a voltage balancing topology with fault ride-through ability is proposed. Although this topology can operate under DC fault and only need only 3 voltage sensors, the structure is a little complicated. Besides, the power exchange between the upper and the lower arm through hardware may lead to bigger power loss in the additional circuits. Another novel local balancing topology, especially for hybrid SM of half-bridge and full-bridge, is proposed in [39]. For the two adjacent modules, the voltage balancing can be realized within them. It is noted that this presented topology has increased power capacity and the fault ride-through ability. However, only half of the voltage sensors are reduced, and more switches are needed.
In order to achieve SM capacitor voltage balancing control, a novel MMCC-DSCC topology is proposed. It can significantly reduce the number of SM voltage sensors and VOLUME 7, 2019  [36], (b) Parallel-connected diode-clamped topology [37]. (c) Balancing topology with fault ride-through ability [38]. (d) Local voltage balancing topology with increased power capacity [39].
mitigate additional delay process caused by the sampling and control signals transmission. The rest of the paper is organized as follows. In Section II, the proposed topology and its working principle are described, and some comparisons with conventional schemes are presented. Section III introduces its modeling and control method. The parameters selection guide of the proposed scheme and cost analysis are discussed in Section IV. Simulations and experimental results verify the effectiveness proposed topology in Section V and Section VI. The conclusion is presented in Section VII.

II. DESCRIPTION OF THE PROPOSED MMCC-DSCC
In this section, firstly, some conventional topologies for voltage balancing are presented. Then, the proposed scheme and working principle are described. Finally, detailed comparison results are presented.
The topology of MMCC-DSCC is shown in Fig. 1. It is composed of three identical phase legs, each of which includes the upper arm and the lower arm. The inductor L arm is series-connected in each arm, each of which contains n modules. The output terminal of each phase leg is connected to the grid through a filter inductor L ac . U sa , U sb , and U sc are three-phase grid voltages. i La , i Lb , and i Lc are the three-phase currents of the load, i a , i b, and i c are output currents of MMCC and i sa , i sb , and i sc are currents of the grid. i uj and i lj (j = a, b, c) are the output currents of the upper and the lower arm.

A. CONVENTIONAL TOPOLOGIES
Four main conventional MMC topologies for SM voltage balancing in each arm are shown as Fig. 2 [36]- [39]. Fig. 2 (a) shows the presented diode-clamped topology [36], where some additional transformers must be added to achieve SM voltage balancing. Then, Fig. 2 (b) describes the parallel-connected diode-clamped topology where each arm is composed of two parallel clusters [37]. In addition, a novel topology with SM voltage self-balancing and DC fault ride-through ability is described in Fig. 2 (c) [38], where the full bridge SMs are removed from the original topology. Finally, a local voltage balancing topology with bigger power capacity is presented in Fig. 2 (d) [39].

B. THE PROPOSED MMCC-DSCC TOPOLOGY
The proposed MMCC-DSCC topology is shown in Fig. 3. It consists of MMCC-DSCC and n − 1 additional series units. Each unit includes two parallel branches. Branch 1 is a series-connected diode and inductor, and Branch 2 is the reversed series-connected diode, inductor, and switch (IGBT and reversed parallel diode). For these switches of n units, no additional switching signals are needed where each switch (S 2,i−1 ) can be controlled by the corresponding IGBT (S 2 i ) PWM signals.
The basic working principle is described in detail as follows. It is assumed that all the switches in the proposed topology in Fig. 3 are ideal devices. There are two situations (Situation 1 and Situation 2) are introduced, and the corresponding equivalent circuit are respectively described as Fig. 4 (a) and Fig. 4

(b).
Situation 1: When the capacitor voltages of the two adjacent capacitors satisfy the constraint U dc,i+1 > U dci , Fig. 4 (a) can be simplified as Fig. 4

(c).
Situation 2: When the capacitor voltages of the two adjacent capacitors satisfy the constraint U dc,i+1 < U dci , the equivalent circuit in Fig. 4 (b) can be simplified as Fig. 4 (d). The switching signal of S 2,i−1, and detailed working principle are discussed later in this Subsection.  Based on KVL law, the equivalent voltage in Fig. 4 can be expressed as where U e and C e represent the equivalent voltage and capacitor, respectively. In addition, the basic function of total units for every two branches can be introduced as Branch 1 of all units: Branch 2 of all units: Therefore, voltage balancing control of SM capacitors can be achieved where the relationship between switching status and balancing operation can be listed in Table 1.
With the proposed topology, S 2,i can be controlled by the corresponding IGBT (S 2(i+1) ) PWM signals. In situation 2, when S 2(i+1) is turned on, the negative sides of the two adjacent capacitors are connected. Then, S' 2i should be turned on simultaneously to connect the positive sides of the two adjacent capacitors at the same time. When both S 2(+1) and S 2,i are on, the capacitor can exchange the power freely, and capacitor voltage balancing is thus realized.
It is also noted that with the proposed SM balancing method, only 6 voltage sensors (one in each arm) are needed to detect and regulate the arm voltage balancing for the following reason.
In order to precisely control the output currents, the arm voltage has to be regulated. As the SM capacitor voltages in the same arm have been already balanced with the proposed balancing method, only one SM capacitor voltage in each arm are needed to monitor the arm voltage.

C. COMPARISONS BETWEEN DIFFERENT TOPOLOGY
For the MMCC-DSCC, comparison results in each arm of different topologies are listed in Table 2. Based on these analysis results, compared with the conventional software balancing or some improved balancing control methods, the proposed topology has some advantages: 1) It significantly reduces the number of SM capacitor voltage sensors. 2) Control framework can be simple without sort and select process, or some balancing control loops. Additional delay process caused by the sampling and control signals transmission is also mitigated.
In addition, compared with the presented hardware balancing schemes, some main advantages of the proposed scheme can be found as follow.
1) Based on some additional popular diodes insertion, the IGBT number (n < 5) can be reduced, and a transformer can be removed [36].
2) The number of power modules including IGBT, diodes, clamping inductors can be greatly reduced, and no additional arm inductor integration [37].
3) The number of IGBT, diodes are reduced, and no additional resource is needed to regulate the voltage of the first module [38]. 4) The number of IGBT and voltage sensors are significantly reduced. Besides, instead of local voltage  balancing [39], no sorting algorithm is needed for SM balancing.

III. MODELING AND CONTROL STRATEGY OF MMCC-DSCC BASED STATCOM
This section includes two parts. Firstly, the modeling of MMCC-DSCC is presented. Then, a simple control method is applied.

A. MODELING OF MMCC-DSCC
The equivalent circuit of MMCC-DSCC in Fig. 1 is shown in Fig. 5(a), where the equivalent circuit of the AC and DC paths are respectively as Fig. 5(b) and Fig. 5(c). The AC part can be characterized as (4), where R eq and L eq are expressed as (5). In equation (5), R arm and L arm are arm resistor and arm inductor, R ac and L ac are AC output resistor and arm inductor.
Then, the DC part can be characterized as B. CURRENT CONTROL Fig. 6 illustrates the overall control diagram of MMCC-DSCC based STATCOM. The control diagram can be divided into three parts. The first part controls the active and reactive power in positive and negative sequence dq frames, which can be applied in unbalanced power condition. The second part is adopted to control the sum voltage of each arm. The third part generates the voltage references of each arm and the drive signals of each switch. The positive and negative sequence current can be transformed into a DC component through an individual transformation in positive and negative sequence dq frame. As a result, the DC component can be accurately tracked by simple PI controllers. The derivation process is exhibited as follows.
The positive sequence and negative sequence is expressed as The transfer matrix of the positive and negative sequence dq frame can be expressed as With the transformation of C dq/abc , it can be concluded from (10) that the positive sequence current is transferred into the DC component and the negative sequence current is transferred into the second order component.
With the transformation of C * dq/abc , it can be concluded from (11) that the negative sequence current is transferred into the DC component and the positive sequence current is transferred into the second order component.
The similar design principle of PI controllers can be found in the reference [40], and it is not be discussed in this paper.

C. ARM VOLTAGE CONTROL
The second part is adopted to regulate the sum voltage of SMs in each arm. The SM voltages within each arm have already been balanced through the proposed topology. It can be easily seen that the arm voltage can be reflected from the measurement of a single SM voltage in (12). Thus, this capacitor voltage balancing process significantly reduces the number of voltage sensors.
where U up dci1 and U low dci1 (i = a, b, c) are the capacitor voltages of the first SM in the upper and the lower arm respectively. It's noted that only one SM voltage sensor in each arm is needed. In this paper, the first SM in each arm is applied.
The arm voltage is regulated by control of circulating current. The circulating current reference to regulate the arm voltage includes two components. The first component is to control the sum voltage of two arms in the same phase and the second component is used to control the voltage difference between the upper and the lower arm. According to [39], the reference values of circulating currents can be expressed as In order to control the circulating currents, the PIR controller is adopted. The PI controller is used to control the DC component of the circulating currents. In addition, the other two resonant (R) controllers are adopted to respectively achieve the fundamental current control and suppress the second order components of circulating currents. For the control parameters design guide of this PIR controller can also be found in reference [41].

D. MODULATION
In this paper, the popular phase shifted carrier (PSC) PWM is used [40], and the final voltage reference of each arm can be expressed as where V uj and V lj (j = a, b, c) are the voltage reference of the upper and the lower arm.

IV. DISCUSSION
In this section, the parameters design guide for the proposed scheme is discussed first, including clamping inductor, diodes, and IGBT switches. Then, the cost of the proposed balancing scheme is analyzed.

A. PARAMETER SELECTION OF THE CLAMPING INDUCTOR
As the balancing analysis principle of situation 1 and situation 2 is identical, situation 1 is used as an example to describe the parameter selection process. According to Fig. 4 (a), when the switch S 2,(i+1) is on, based on KVL law, the following equations can be calculated as    L e C e d 2 U e dt + U e = 0 L e = L 1i = L 2i (15) Thus, it's clearly shown that it is a second-order system and the solution of the linear differential equation can be expressed as where U 0 is the initial voltage of U e , i L1i is the clamping current of the diode-clamped circuit, and γ is system eigenvalue.
The solution can be further expressed as  It is clearly seen that the waveform of U e fluctuates as the sine wave and the period of fluctuation T osc is closely related to the value of clamping inductor L e . L e has a close relationship with system performance. That is to say, if L e gets larger, the T osc will be larger, and the SM voltage balancing effect will be worse. However, if L e gets smaller, T osc will be smaller, and the possibility of oscillation VOLUME 7, 2019 and extra power loss may be higher. Thus, it is very necessary to give the constraint for the inductor selection.
Assuming U dc,i+1 > U dci , the relationship of the voltage U e and the clamping current i L1i is shown as Fig. 7 according to (18). Thus, T , the active period of the switch S 2(i+1) , is supposed to be smaller than 0.25T osc . However, it is unrealistic to keep each T smaller than 0.25T osc in the real application. In a word, an average of T can be described 83066 VOLUME 7, 2019 as T = λmT sw < 0.25T osc (20) where m is the modulation index, λ is the average coefficient (0 < λ < 1), and T sw is the reciprocal of the switching frequency. Therefore, based on the last two equations, the constraint can be presented as

B. PARAMETER SELECTION OF CLAMPING DIODE AND SWITCH
As the manufacture errors, PSC modulation, and other disturbances in the real SM circuits, power unbalance among SMs in each arm occurs. Each SM power and power difference among SMs in each arm can be respectively defined as where σ , γ , and δ are power difference proportion values caused by the manufacture errors, PSC modulation, and other disturbances respectively. The system can be in a balanced condition when exchange power between two adjacent SMs is equal to about half of the power difference P dif . Based on the energy conservation law, it can be described as (24) where i DCC_ave is the average clamping current through the Branch 1.
In order to withstand this clamping current, the forward current of clamping diodes is i DF = αi DCC_ave (25) where α is large than 1 for enough current margin of diodes. Besides, the maximum reverse voltage on diodes is the voltage difference between two adjacent SM and can be expressed as where ε is usually less than 10%. Based on these analysis results, the diode can be selected. In addition, IGBT switch selection is discussed as follows.
For the switch, the maximum conduction current is the same as (25).
The maximum value of the reserved voltage for the switch is described as v RSF = U dc n (28) Based on the above analysis results, the diode and switch can be selected considering some real constraints.

C. COST ANALYSIS OF THE PROPOSED BALANCING TOPOLOGY
Compared with traditional software balancing method, the reduced resources and additional resources are listed below.
2) ADDITIONAL RESOURCES 6n-6 IGBTs, 6n-6 drivers, 12n-12 diodes and 12n-12 inductors. The additional cost of the proposed method can be calculated through the following equation. where cost is the total additional cost. IGBT and peri are the cost of IGBT and its peripheral cost (including drivers and other auxiliary costs). dio and ind are the cost of diodes and inductors. sens , send , rece , and cab are the cost of the voltage sensors, optical senders, optical receivers, and optical fiber cables respectively. According to reference [42], the cost of IGBT can be expressed as IGBT = σ chip A chip + pack (30) where σ cost is the specific price per chip area and A chip is the chip area. pack is the package price. The peripheral cost can be roughly expressed as Substituting (30) and (31) into (29), the total additional cost can further be expressed as

V. SIMULATION RESULTS
To verify the effectiveness of the proposed MMCC-DSCC scheme, the same topology in Fig. 3 in MATLAB/Simulink is used. The simulation parameters are shown in Table 3. Three simulation scenarios are shown in Table 4, where Scenario 1 describes the balanced load condition, Scenario 2 describes the unbalanced load condition, and Scenario 3 compares the balancing effect between software balancing method and the proposed balancing method under balanced and unbalanced load.
Scenario 1 Fig. 8 shows the simulation results for the proposed MMCC-DSCC based STATCOM under balanced load. The output currents of MMCC-DSCC, the load currents and three-phase grid currents after reactive power compensation  are shown in Fig. 8 (a). It's clearly seen that good control performance can be achieved where three-phase grid currents are balanced and the power factor is nearly 1. Then, as shown in Fig. 8 (b), the proposed topology has realized similar SM voltage balancing control of individual capacitors, compared with the software balancing method. However, SM capacitor voltage remains unbalanced without balancing control. In addition, internal currents of Branch1 and Branch2 are very small in the upper five, and the lower five units are respectively depicted in Fig. 8 (c) and Fig. 8 (d), indicating that they are much smaller than AC output currents of this MMCC. Scenario 2 Fig. 9 depicts the simulation results for the proposed MMCC-DSCC based STATCOM under unbalanced load. The output currents of MMCC-DSCC, the load currents, and three-phase grid currents after reactive power compensation are shown in Fig. 9 (a). It's easily seen that similar simulation results as balanced load in Scenario1, where balanced grid currents are maintained, and effective reactive power are compensated. Then, as shown in Fig. 9 (b), similar simulation performance in Scenario1 under balanced load with SM voltage balancing control can be adopted under unbalanced load. But SM voltages are unbalanced without balancing control. In addition, internal currents of Branch1 and Branch2 are very small in the upper five, and the lower five units are respectively depicted in Fig. 9 (c) and Fig. 9 (d), showing that they are much smaller than AC output currents of this MMCC-DSCC. Based on these simulation results of Scenario 1 and Scenario 2, the proposed scheme for MMCC-DSCC based STATCOM is always effective in balanced and unbalanced load. Scenario 3 Fig. 10 exhibits the comparison results of the proposed voltage balancing method and the software balancing method [40]. The simulation results include two cases: balanced load and unbalanced load. It should be noted that in order to vividly demonstrate the advantages of the proposed method, an artificial initial deviation of SM voltages is set before 0.6s.
For balanced load, the SM voltages are shown in Fig. 10  (a), where both the proposed balancing method and the software balancing method are activated at 0.6s. As is shown in the figure, the proposed method has the faster balancing speed than the software balancing method during the dynamic process indicating the proposed balancing method can lower the effect brought by sampling and control delay. For unbalanced load, the dynamic SM voltages are shown in Fig. 10 (b), where both the two balancing methods are activated at 0.6 s. It clearly shows that the proposed balancing method has a faster balancing speed than the software balancing method, indicating that the proposed balancing method can reduce the effect of sampling and control delay.

VI. EXPERIMENTAL RESULTS
A laboratory prototype based on nine-level MMCC-DSCC based STATCOM has been implemented in the laboratory as shown in Fig. 11. The experiment parameters are given in Table 5. The two experiment scenarios are given in Table 6. The proposed control are implemented with TMS320F28335 and 10M02SCE144C8G. The Agilent scope VOLUME 7, 2019  DSO5014A is used to display and record the experimental waveforms.

Scenario 1
The experiment results of the proposed MMCC-DSCC under balanced load are shown in Fig. 12. The grid voltage and three-phase currents before and after compensation are shown in Fig. 12 (a) and (b), respectively. The output currents of MMCC-DSCC is shown in Fig. 12 (c). It can be clearly seen that the proposed MMCC-DSCC can effectively compensate the reactive power. The capacitor voltages and currents in Branch 1 or Branch 2 in the upper 3 units and the lower 3 units are shown in Fig. 12 (d), (e) and (f) individually. With the limitation of scope signals, only one 83070 VOLUME 7, 2019 clamping current between two adjacent SMs is displayed. As shown in Fig. 12 (d), the individual capacitor voltage of each SM is well balanced. The results in Fig. 12 (e) and Fig. 12 (f) indicates that the internal currents are much smaller than output currents.

Scenario 2
The experiment results of MMCC-DSCC under unbalanced load are shown in Fig. 13. The grid voltage and three-phase currents before and after compensation are shown in Fig. 13 (a) and (b), respectively. The output currents of MMCC-DSCC is shown in Fig. 13 (c). It can be easily showed that reactive power compensation can be achieved by the proposed MMCC-DSCC. The capacitor voltages and currents in Branch 1 or Branch 2 in the upper 3 units and the lower 3 units are shown in Fig. 13 (d), (e) and (f) individually, showing SM capacitor voltages has been well balanced and internal currents are much smaller than the output currents of MMCC-DSCC.
According to the above experimental results of Scenario 1 and Scenario 2, the proposed scheme for MMCC-DSCC based STATCOM is always effective in balanced and unbalanced load.

VII. CONCLUSION
For MMCC-DSCC based STATCOM, a new voltage balancing control scheme for all the SM capacitors is proposed. Compared with conventional software balancing control methods, the number of capacitor voltage sensors by the proposed scheme has been greatly reduced, especially in the higher voltage or more SMs in each arm. Both Simulation waveforms and experimental results verify the effectiveness of this control scheme even under two operation conditions of three-phase balanced and unbalanced load. For the inserted additional units, the design guide of these corresponding components has been described. By the proposed scheme, both DC capacitor voltage balancing control and reactive power compensation are simultaneously realized for MMCC-DSCC based STATCOM even in power unbalanced condition.
More effective combination of the improved controller and this proposed hardware topology will be further developed in the future work.
QIAN XIAO received the B.S. and M.S. degrees in electrical engineering from the Hebei University of Technology, Tianjin, China, in 2011 and 2014, respectively. He is currently pursuing the Ph.D. degree in electrical engineering with Tianjin University, Tianjin. Since 2018, he has been a Visiting Researcher with the Department of Energy Technology, Aalborg University, Aalborg, Denmark.
His research interests include multilevel converters, DC/DC converters, and power electronics for distributed generation, microgrid, and HVDC. His current research interests include the modeling and control of bidirectional converters and battery energy storage systems. 83072 VOLUME 7, 2019