High Gain Transformer-Less Double-Duty-Triple-Mode DC/DC Converter for DC Microgrid

High-gain DC/DC converters with high efficiency are needed in dc microgrid owed to the low voltage of power sources, e.g., photovoltaic-cell and fuel-cell. This paper proposed a new high-gain double-duty-triple-mode (DDTM) converter for dc-microgrid applications. The proposed DDTM converter operates in three modes to achieve higher voltage gain without utilizing transformer, coupled inductor, voltage multiplier, and multiple voltage lifting techniques, e.g., triple, quadruple voltage lift. The modes of operation of the converter are controlled through three switches with two distinct duty ratios (double duty) to achieve wide range duty ratio. The operating principle, voltage gain analysis, and efficiency analysis of the proposed converter are discussed in detail and to show its benefits comparison is provided with the existing high-gain converters. The boundary operating condition for continuous conduction mode (CCM) and discontinuous conduction mode (DCM) is presented. The prototype of the proposed converters with 500-W power is implemented in the laboratory and experimentally investigated, which validate the performance and feasibility of the proposed converter. Due to double duty control, the proposed converter can be controlled in different ways and the thorough discussion on controlling of the converter is provided as a future scope.

INDEX TERMS DC/DC, double duty, high gain converter, dc microgrid, transformer-less, triple mode, wide duty range. NOMENCLATURE S 1 , S 2 , and S 3 Active switches R S1(ON ) , R S2(ON ) , and R S3 (ON ) On state resistance of switches S 1 , S 2 , S 3 P 1 and P 2 Input and output power η Efficiency P S1−SW , P S2−SW , and P S3−SW Switching power loss of switches S 1 , S 2 , S 3 P S−SW Total switching power loss t f −S1 , t f −S2 , t f −S3 Falling switching time for switches S 1 , S 2 , S 3 t r−S1 , t r−S2 , t r−S3 , Rising switching time for switches S 1 , S 2 , S 3 The associate editor coordinating the review of this manuscript and approving it for publication was Yijie Wang. Lower peak of current through inductor L 1 and L 2 I L1 and I L2 Peak to peak current ripples of inductor L 1 , L 2 v C1 and v C2 Voltage across capacitor C 1 , C 2 V C1 and V C2 Average voltage across capacitor C 1 , C 2 v D1 and v D2 Voltage across diodes D 1 , D 2 V D1 and V D2 Average voltage across diodes D 1 , D 2 i S1 , i S2 , and i S3 Current through switches S 1 , S 2 , S 3 v S1 and v S2 Voltage across switches S 1 , S 2 v AB Voltage across AB junction (diode D + switch S 3 ) v 1 and v 2 Input and output voltage (average value of V 1 and V 2 ) R 1 Series resistance of input voltage i 1 and i 2 Input and output current I 1 and I 2 Average value of Input and output current v GS1 , v GS2 , and v GS3 Voltage magnitude of gate pulse for switches S 1 , S 2 , S 3 I, II and III (in superscript) Defines the values in Mode I, II and III χ B Boundary normalized inductor time constant χ Normalized inductor time constant

I. INTRODUCTION
Due to penetration of renewable energy sources, the power converter configurations are gaining more attraction in DC microgrid [1]. Owing to the low terminal voltage of power sources e.g. photovoltaic-cell (PV cell) and fuel-cell, high gain DC/DC converters with high efficiency are needed in DC microgrid [2], [3]. Fig. 1 shows the typical block diagram of a DC microgrid system where DC-DC converter and proposed configurations are employed to uplift the low generated voltage (12-48V) to an adequate voltage level (200-400V) [4]. Practically, in present, the classical boost converter is not a suitable solution to accomplish high step-up voltage gain due to the effect of the series resistance of capacitor and inductor, effective electromagnet interference (EMI), and high rating components and semiconductor devices. Additionally, the reverse recovery of the diode problem is arising when the converter operates at a high duty ratio to achieve high voltage gain [5], [6]. In literature, to overcome these issues, several DC/DC converter configurations are recently proposed with high gain, high efficiency, and small volume etc., e.g. [7], [8]. The isolated DC/DC converters e.g. push-pull, half and full bridge, flyback, and forward converters are proposed in that high voltage gain is achieved by adjusting the turn of the transformer [8]- [11]. Nonetheless, due to the leakage inductance of the transformer, these configurations are suffered from high power dissipation and a high spike in voltage across switches [4]. Therefore, to overcome these issues, additional active clamping technique and snubber circuits are used [12], [13]. Nevertheless, high side driver and additional control switches increase the cost of the circuitry. Furthermore, transformer core saturation is the other problem associated with isolated converters. In [14], the interleaved converter technique is employed to achieve high gain, reduce filter size, and high efficiency using a reduced number of control switches. Nevertheless, complexity and drive circuitry is increased due to the parallel connection of several converters. Moreover, high loss of energy, high voltage/current stress, and complex switching control logic are other drawbacks of this technique. Therefore, transformer-less DC/DC converters can be a solution where galvanic isolation is not necessary and to achieve high voltage gain, reduced size and cost [15], [16]. The cascaded boost converters (CBC), quadratic boost converter (QBC), switched capacitor and switched inductor integration with classical converter, voltage multiplier are utilized to achieve higher voltage gain [17]- [20]. However, a large number of reactive components, semiconductor, switched capacitor and switched inductors stages increase the complexity and price of the converter. In cascaded configurations, it is noteworthy that the requirement of high rating components is increased as the number of cascaded cells increases. Moreover, complex driver circuitry is required to control several switches [16], [21]. In [22], switch voltage stress is reduced by employing additional semiconductor devices and capacitor in a quadruple converter configuration. In [23], nonisolated coupled inductors based converter is proposed to achieve high efficiency and high voltage gain. Using this techniques energy recovery leakage inductance, high efficiency, high voltage, reduced switch stress is achieved by adjusting the turns and coupling factor of coupled inductors. Nevertheless, the large time is required for diode reverse recovery due to coupled inductor leakage inductance. Moreover, the complexity, size, and price of the converter circuitry are increased due to the utilization of coupled inductors. In coupled inductor based converters, the high ripple in the input current is a result of high turns ratio of coupled inductor. Therefore, the stage of the input filter is needed to minimize current ripples, which additionally increases the circuitry and cost of the converter [24]. In [25], capacitor and diode circuitry i.e similar to the switched capacitor is utilized to achieve higher voltage gain with a minimum number of inductor and control switches. In this technique, the capacitors perform similarly to serially connected voltage sources. Later, in [26] active network is combined with a switched capacitor with n cell structure to increase the voltage gain. However, the use of converter is restricted in practical application due to size, low efficiency, high cost, and several components in each cell. Moreover, complex control drive circuitry, additional inductor and active control switch are the other drawbacks of this configuration. Voltage-lift is another boosting technique in which the voltage gain is increased by utilizing the structure of capacitors and inductors, the technique is well presented in [27]. In this technique, inductors are serially discharged with a charged capacitor to increase the voltage at the output side. The main benefits of this structure are high power density, simple structure, less cost, minimum control switches (thus, simple control), small output voltage ripple, and higher efficiency. In [28], three different converters are proposed in that when switches are turned ON and OFF inductors are charged and discharged in parallel and series, respectively. Although using two switches and two inductors along with additional capacitor and diodes, the voltage gain is sufficiently high. In [29], the new non-isolated converter is proposed to achieve high gain for microgrid application.
The voltage gain of this converter is adjusted by two duty ratios. However, the voltage gain is limited even though using three high voltage switches and two inductors. To increase the voltage gain, the inductor structure is replaced with stages of the switched inductor [30]. However, the voltage gain is restricted due to the use of several inductors and diodes.
In this structure, the energy is transfer to load via multiple loops which degrade the efficiency and performance. Moreover, unequal inductances in the converter affect the characteristics of the converter. In this paper, a new high gain Transformer-less Double-Duty-Triple-Mode (DDTM) converter is proposed for DC microgrid application. The proposed configuration is capable to provide high voltage gain with wide duty range and reduced switch voltage stress. Moreover, the converter is designed without using transformer, voltage multiplier, and multiple switched capacitor and switched inductor. The main benefits of the proposed configuration are flexibility in selection of duty ratios, the operating range is increased due to double duty ratio, and converter can be controlled in several ways when the input side voltage is perturbed. Moreover, the energy is transfer from input to output without using multiple energy transfer loops which increases the efficiency and performance. Wide duty range and high voltage gain with higher efficiency make proposed converter promising topology for DC microgrid applications.
The paper is organized as follows. Power circuitry of the proposed converters is explained in section II. The steady state analysis in CCM, DCM mode with boundary operating condition is given in section II. The effect of non-ideality of inductors and semiconductor devices on voltage gain and efficiency of the proposed configurations is analyzed in section III. The comparison of DDTM with existing converters is provided in section IV. The experimental investigation results are provided in section V. The thorough discussion on controlling of the converter is provided as a future scope in section VI. Finally, the conclusion is provided in section VII.

A. POWER CIRCUIT
The power circuit of DDTM converter is depicted in Fig. 2. The power circuit is designed with the help of two switches S 1 and S 2 , one unidirectional current switch S 3 (diode D is connected in series to make unidirectional), two identical inductors L 1 and L 2 , two capacitors C 1 and C 2 , and two diodes D 1 and D 2 . The output voltage is taken across the capacitor C 2 and power is delivered to load (R). Based on the operation, both inductors L 1 and L 2 considered as identical inductors and have inductance L. Therefore, L = L 1 = L 2 . Ideal components and semiconductors devices are considered VOLUME 7, 2019 in order to explain the characteristics and operating principle. Let's consider, one switching cycle time period and switching frequency for all the switches are T S and f S , respectively. Switches S 1 and S 2 are controlled by the same gate pulse with duty ratio d 1 and the switch S 3 is controlled by gate pulse with duty ratio d 2 with time delay d 1 T S . Using these pulses, the converter is operates in three modes.

B. CCM OPERATION AND ANALYSIS
The CCM operation of the converter is explained as follows, Fig. 3 depicts the typical characteristics of DDTM converter. Let's consider α I 1 , α II 1 and α I 2 , α II 2 are the inductor L 1 and L 2 magnetizing angles; where superscript is defines the mode of operation (I and II) and subscript defines the inductor. Also consider β III 1 and β III 2 are the inductor L 1 and L 2 demagnetizing angles in mode III. The typical inductor current and voltage waveforms are shown in Fig. 4. Due to same characteristics of inductor L 1 and L 2 , the areas covered by both inductor voltage waveforms are same. In Fig. 4, A, B, and C are the areas under voltage waveform of inductor L 1 and L 2 for modes I, II, and III, respectively.    and the switch S 3 is turned OFF. In this mode, inductors L 1 and L 2 are magnetized by input voltage v 1 through switches S 1 and S 2 , respectively. Also, capacitor C 1 is charged by the input voltage v 1 through diode D 1 and switch S 1 . Throughout this mode, diodes D 1 and D 2 are forward biased and reversed biased, respectively and the capacitor C 2 is discharged through load (R). The average inductor L 1 , L 2 and capacitor C 1 , C 2 voltage and average input current can be 36356 VOLUME 7, 2019 expressed as follows, The ''I '' is expressed in the superscript for mode I. It is noteworthy that the current waveform of inductors L 1 and L 2 is linearly increased with slope tan (α I 1 ) and tan (α I 2 ). Moreover, the magnetizing angle of inductors L 1 and L 2 current is same and expressed as follows, Fig. 5(b) depicts the mode II equivalent power circuitry of DDTM converter in which switches S 1 and S 2 are turned OFF and the switch S 3 is turned ON. In this mode, inductors L 1 and L 2 are magnetized in series by input voltage v 1 through switches S 3 . In this mode, diodes D 1 and D 2 are reversed biased due to capacitor C 1 and C 2 voltages, respectively. Throughout this mode, the capacitor C 2 discharged through load (R). The average inductor L 1 , L 2 and capacitor C 1 , C 2 voltage and average input current can be expressed as follows, The ''II'' is expressed in the superscript for mode II. It is noteworthy that the current waveform of inductors L 1 and L 2 is linearly increased with slope tan (α II 1 ) and tan (α II 2 ). Moreover, the magnetizing angle of L 1 and L 2 current is same and expressed as follows, Fig. 5(c) depicts the mode III equivalent power circuit of DDTM converter in which all the switches S 1 , S 2 , and S 3 are turned OFF. In this mode, the series connection of input voltage v 1 , inductor L 1 and L 2 , and capacitor C 1 supplied power to load (R) and also charges the capacitor C 2 . Hence, inductor L 1 and L 2 are demagnetized and capacitor C 1 is discharged serially through load (R). Throughout this mode, diodes D 1 and D 2 are reversed biased and forward biased, respectively. The average inductor L 1 , L 2 and capacitor C 1 , C 2 voltage and average input current can be expressed as follows, The ''III'' is expressed in the superscript for mode III. It is noteworthy that the current waveform of inductors L 1 and L 2 is linearly decreased with slope tan (β III 1 ) and tan (β III 2 ). Moreover, the demagnetizing angle of L 1 and L 2 current is same and expressed as follows, From Fig. 4, the area covered by the inductor L (i.e L 1 and L 2 ) voltage waveform in Mode I, II, III are relates as follows, By substituting (1), (3), and (5) in (7), the voltage gain for CCM is obtained as follows The plot of voltage gain versus duty ratio d 1 and d 2 is shown in Fig. 6. It is noteworthy that the proposed converter gives high voltage gain by selecting appropriate duty ratios d 1 and d 2 . The region is shaded in which the proposed DDTM converter provides a voltage gain in the range 10 to 20. Further to explain Fig. 6, the effects of each duty ratio d 1 and d 2 on voltage gain are shown in Fig. 7(a) and 7(b). It is noteworthy that Fig. 6 is a combined version of Fig. 7(a) and Fig. 7(b). In Fig. 7(a), the plot of voltage gain in CCM versus duty ratio d 1 is given by considering the different values for the duty ratio d 2 . It is observed that in each case the voltage gain is increased if duty ratio d 2 is constant and duty ratio d 1 is increased. When addition of duty ratios d 1 and d 2 i.e d 1 +d 2 is constant in between 0 to 1, it is observed that the voltage gain is increased if duty ratio d 2 is decreased (The example is shown in Fig. 7(a) for d 1 + d 2 = 0.8 and d 1 + d 2 = 0.9). In Fig. 7(b), the plot of voltage gain in CCM versus duty ratio d 2 is given with considering the different values for the duty ratio d 1 . It is observed that in each case the voltage gain is increased if duty ratio d 1 is constant and duty ratio d 2 is increased. When addition of d 1 and d 2 i.e d 1 + d 2 is constant in between 0 to 1, it is observed that the gain is decreased if duty ratio d 1 is decreased (The example is shown in Fig. 7

C. DCM OPERATION AND ANALYSIS
The DDTM converter DCM operation is divided in four modes. Fig. 8 depicts the typical DCM characteristics of DDTM converter. Let's consider δ I 1 , δ II 1 and δ I 2 , δ II 2 are the inductor L 1 and L 2 magnetizing angles; where superscript is defines the mode of operation (I and II) and subscript defines the inductor. Also consider γ III 1 , γ III 2 are the inductor  L 1 and L 2 demagnetizing angles in mode III. The typical inductor current and voltage waveforms in DCM are shown in Fig. 9. Due to same characteristics of inductor L 1 and L 2 , the areas covered by both inductors voltage waveforms are same. In Fig. 9, M, N, O and P are the areas under voltage waveform of inductor L 1 and L 2 for modes I, II, III, and IV, respectively. The DCM operation of the DDTM converter is explained as follows, The equivalent circuit is same as mode I of CCM ( Fig. 5(a)). In this mode, switches S 1 and S 2 are turned ON and the switch S 3 is turned OFF. For this mode, the maximum amplitude of current through inductor L 1 and L 2 can be expressed as follows, The equivalent circuit is same as mode II of CCM ( Fig. 5(b)).
In this mode, switches S 1 and S 2 are turned OFF and the switch S 3 is turned ON. For this mode, the maximum amplitude of current through inductor L 1 and L 2 can be expressed as follows, The equivalent circuit is same as mode III of CCM ( Fig. 5(c)).
In this mode, all the switches S 1 , S 2 and S 3 are turned OFF and at the end of this mode (at t = t 3 ), the inductor L 1 and L 2 currents reached to zero. For this mode, the maximum amplitude of current through inductor L 1 and L 2 can be expressed as follows,

4) MODE IV [t 3 TO t S ]
In this mode, all the switches S 1 , S 2 and S 3 are turned OFF and inductor L 1 and L 2 currents are zero. The equivalent circuitry for this DCM mode is shown in Fig. 10. Throughout this mode, the inductor L 1 and L 2 energy is zero and capacitor C 2 discharged through to load. Using (10) and (11), the value of d 3 is can be obtained as follows, The average capacitor C 2 current can be expressed as follows, At steady state, the average current through any capacitor is zero. Therefore, Using (14), the voltage gain for DCM is obtained as follows where, parameter χ is the normalized inductor time constant. The plot of voltage gain in DCM versus duty ratio d 1 and d 2 is shown in Fig. 11(a). It is noteworthy that the required voltage gain in DCM of proposed converter can be achieved by selecting appropriate duty ratio d 1 and d 2 . The region is shaded in which the proposed converter provides a voltage gain in the range 8 to 12. Further to explain Fig. 11(a) more clearly, the effects of each duty ratio d 1 and d 2 on DCM voltage gain are shown in Fig. 11(b) and 11(c). It is noteworthy that Fig. 11(a) is combined version of Fig. 11(b) and Fig. 11(c). In Fig. 11(b), the plot of voltage gain in DCM versus duty ratio d 1 is given by considering different values for duty ratio d 2 . It is observed that in each case of Fig. 11(b), the voltage gain is increased if duty ratio d 2 is constant and duty ratio d 1 is increased. When addition of d 1 and d 2 (i.e d 1 + d 2 ) is constant in between 0 to 1, it is observed that the voltage gain is increased if duty ratio d 2 is decreased (The example is shown for d 1 + d 2 = 0.9). In Fig. 11(c), the plot of voltage gain in DCM versus duty ratio d 2 is given by considering different values for duty ratio d 1 . It is observed that in each case of Fig. 11(c), the voltage gain is increased if duty ratio d 1 is constant and duty ratio d 2 is increased. When addition of d 1 and d 2 (i.e d 1 + d 2 ) is constant in between 0 to 1, it is observed that the voltage gain is decreased if duty ratio d 1 is decreased (The example is shown for d 1 + d 2 = 0.9). Using (8) and (15), the boundary for CCM and DCM can be obtained as follows, where boundary normalized inductor time constant is χ B . In Fig. 12(a), the plot of χ B versus duty ratio d 1 is shown by considering various value of duty ratio d 2 . This graph clearly explained the effect of duty ratio d 1 on χ B . It is investigated that after attaining the peak value there is decrement in normalized inductor time constant χ B when duty ratio d 1 is increased. Moreover, at constant d 1 , the magnitude of χ B is reduced when duty ratio d 2 is increases. In Fig. 12(b), the plot of χ B versus duty ratio d 2 is shown by considering various value of duty ratio d 1 . This graph clearly explained the effect of duty ratio d 2 on χ B . It is investigated that after attaining the peak value there is a decrement in normalized inductor time constant χ B when duty ratio d 2 is increased. Moreover, at constant d 2 , the magnitude of χ B is reduced when duty ratio d 1 is increases.
The boundary surface of DCM and CCM is dependent on duty ratios d 1 , d 2 , and χ B . Hence, to understand the combined effect of duty ratio d 1 , d 2 , and χ B on boundary of DCM and CCM, the surface plot of χ B versus duty ratios d 1 and d 2 is plot in Fig. 13(a). In Fig. 13(a), the area under the drawn surface is DCM region and area outside the surface is CCM region. Additionally, DCM region is shown in Fig. 13(b) by varying duty ratio d 1 for various values of duty ratio d 2 .
It is clearly visible that DCM region is reduced when the value of duty ratio d 2 is increased. It is also investigated that the DCM region becomes narrow when the duty ratio d 2 36360 VOLUME 7, 2019 is increased and duty ratio d 1 is constant. DCM region is shown in Fig. 13(c) by varying duty ratio d 2 for various values of duty ratio d 1 . It is clearly visible that DCM region is increased when the value of duty ratio d 1 is increased from 0 to 0.33 and reduced when the value of duty ratio d 1 is increased beyond 0.33. It is also investigated that the DCM region becomes narrow when the duty ratio d 1 is increased and duty ratio d 2 is constant. Hence, the DCM operation is dependent on the both duty ratios d 1 and d 2 , and χ B . When χ B is higher than χ then DCM occurs for DDTM converter. Nevertheless, the condition in order to operate converter in CCM is as follows,

III. EFFICIENCY INVESTIGATION OF DDTM CONVERTER
The non-idealities are considered in order to analyze the efficiency of DDTM converter. The power circuit of DDTM converter is shown in Fig. 14 with non-idealities. The series resistances R L1 and R L2 are considered as non-ideality of inductor L 1 and L 2 , respectively. The resistance R 1 is considered in series with input voltage as a non-ideality of input voltage source. The switches S 1 , S 2 and S 3 nonideality is shown by ON state resistance R S1(ON ) , R S2(ON ) , and R S3(ON ) , respectively. For simplicity, non-ideality of diode D is neglected. The diode D 1 and D 2 non ideality is shown by forward resistance R F−D1 , R F−D2 and threshold voltage V D1−TH and V D2−TH , respectively.

A. MODE I [t 0 TO t 1 ]
The average current and voltage through/across inductor and capacitor is obtained as follows, The average current and voltage through/across inductor and capacitor is obtained as follows, The average current and voltage of inductor and capacitor is obtained as follows, To design the DDTM converter, identical inductor The current through inductors L 1 and L 2 can be expressed as follows, The output voltage is obtained as follows, Let's assume, power loss due to switching of switches S 1 , S 2 , and S 3 is P S1−SW , P S2−SW , and P S3−SW , respectively. The total switching power loss P S−SW can be calculated as follows, where falling and rising switching time for switches S 1 , S 2 , and S 3 are represented by t f −S1 , t f −S2 , t f −S3 , and t r−S1 , t r−S2 , t r−S3 , respectively. The average current and voltage through/across switches is represented by I S1 , I S2 , I S3 and V S1 , V S2 , V S3 , respectively. The total power at input and output port is obtained as follows, The efficiency of the DDTM converter is calculated as follows,  stage (capacitor and diode) is utilized to boost the voltage; it's obvious utilization of additional reactive components offer higher gain. Moreover, practically increasing the reactive components and operate such a converter at a higher duty ratio is not a feasible solution. Theoretically, using classical boost converter (case 1) and existing converter (case 2 to 7) which uses single duty ratio, very higher voltage gain can be attained at duty ratio closer to unity (infinity at duty ratio = 1). However, practically the converter suffer to achieve high stepup voltage gain due to the effect of the series resistance of capacitor and inductor, electromagnet interference (EMI), and need high rating components and semiconductor devices. Moreover, the switches of the converter (case 1 to 7 in table 1) continuously ON when operates at higher duty ratio. Hence there is requirement of large heat sink. In [29], high gain converter is proposed with two inductors, three switches and two types of duty ratios. However, the converter provides a low voltage gain compared to proposed DDTM converter. Moreover, among converters discussed in Table 1, the proposed DDTM converters provide high gain at given duty ratio and have higher duty range and required low voltage switches (except case 7; however, the converter mentioned in case 7 is restricted by duty ratio). It is noteworthy that the DDTM converter provides a option to adjust voltage gain by selecting appropriate duty ratios which is not possible from any converter (case 1 to 7) that is operated on single duty ratio.

A. PROTOTYPE DESCRIPTION
The prototype is developed in the laboratory to investigate and validate the performance and theoretical analysis of the DDTM converter. The designed prototype is shown in Fig. 15 and the parameters are shown in Table 2. The prototype is built with considering the parameters: power 500W, output/input voltage 400V/38V, and typical duty ratio d 1 =  50% and d 2 = 35%. Two ferrite core identical inductor L 1 and L 2 with inductance 500µH, capacitor C 1 with 100µF/50V (two 50µF/50V capacitors in parallel), capacitor C 2 with 100µF/450V (two 50µF/450V capacitors in parallel), Flat-type heat sink for diodes (STTH30R04) and switches FDP19N40 are used to design the circuitry of the DDTM converter. Fig. 16 depicts the block diagram of switching gate pulse generation scheme which is used to test the performance of the proposed converter at different set of duty ratios. The switching gate pulse generation scheme is designed by using multiplexer, comparator, logic, constant, and counter blocks. The waveform associated with pulse generation scheme is shown in Fig. 17. Two 8:1 multiplexers (Mux-1 and Mux-2) are used to select the value of duty ratio. Four different values (50%, 45%; 40%, 35%) are provided for the duty ratio d 1 and the required value is selected through Mux-1. Mux-2 is used to select the value of d 1 +d 2 from the given four different values (85%, 80%; 75%, 70%). Using counter block, sawtooth carrier waveform is generated and compared with output of Mux-1 to generate switching gate pulses (A in Fig. 17) for switches S 1 and S 2 . The output of Mux-2 is compared with generated sawtooth carrier to generate pulse with duty ratio d 1 + d 2 (C in Fig. 17). Finally, the waveform A is XOR with waveform C to generate pulse (B in Fig. 17) for switch S 3 . The 50kHz switching pulses with different 7 sets of duty ratios (d 1 = 50%, d 2 = 35% (typical set); d 1 = 45%, generated using FPGA in order to investigate the effect duty ratios on voltage gain, performance, and efficiency of the DDTM converter. According to logic, switches S 1 and S 2 are turned ON with same switching pulse whereas switch S 3 is turned ON when switches S 1 and S 2 are turned OFF. Therefore, in mode I, switches S 1 , S 2 , and S 3 are turned ON, ON, OFF, respectively. In mode II, switches S 1 , S 2 , and S 3 are turned OFF, OFF, ON, respectively. In mode-III; all the switches S 1 , S 2 , S 3 are turned OFF.  v 2 ) and input, output current (i 1 , i 2 ), (b) inductor L 1 and L 2 (i L1 and i L2 ) currents and input, output voltage (v 1 , v 2 ), (c) input current (i 1 ), output voltage (v 2 ), inductor L 1 and L 2 current (i L1 and i L2 ), (d) capacitor C 1 and C 2 voltages, inductor L 1 and L 2 (i L1 and i L2 ) currents, (e) voltage across switches S 1 , S 2 , S 3 , and inductor L 1 current, (f) voltage across diode D 1 and D 2 , input current (i 1 ), and output voltage (v 2 ).

C. EXPERIMENTAL RESULTS AT TYPICAL DUTY RATIO
The above discussed pulse generation scheme is utilized to generate two gate pulses; one for switch S 1 and S 2 with duty ratio 50% (d 1 ), and second for switch S 3 with delay 50% of T S (d 1 ), and duty ratio 35% (d 2 ). Fig. 18(a) shows experimental observed waveforms of input, output voltage (v 1 , v 2 ) and input, output current (i 1 , i 2 ). The observed average values of input voltage (V 1 ), output voltage (V 2 ), input current (I 1 ), and output current (I 2 ) is 38.2V, 400.32V, 1.24A, 13.61A, respectively. Fig. 18(b) shows experimental observed waveforms of inductor L 1 and L 2 (i L1 and i L2 ) currents along with input, output voltage (v 1 , v 2 ). The observed average value of inductor L 1 current (I L1 ), inductor L 2 current (I L2 ) is 9.23A and 9.17A, respectively. It is clearly visible that both inductors L 1 and L 2 are charged in mode I and mode II. In Fig. 18(b), it is practically seen that the magnetizing angles for both inductors in mode II are nearly half of the magnetizing angles for both inductors in mode I (i.e α I 1 = 2α II 1 = α I 2 = 2α II 2 ) which is expected according to theory. It is noteworthy that both the inductors are charging with same magnetizing angles (i.e α I 1 = α I 2 and α II 1 = α II 2 ). It is clearly visible that both inductors L 1 and L 2 are discharged in mode III with same demagnetizing angle (i.e β III 1 = β III 2 ). Fig. 18(c) shows experimental observed waveforms of input current (i 1 ), output voltage (v 2 ), inductor L 1 and L 2 current (i L1 and i L2 ). It is clearly visible that the both inductor currents (i L1 and i L2 ) in mode II and III are same as input current. In starting mode I, the transient current observed in the input current due to charging of capacitor C 1 as shown in Fig. 18(c). Fig. 18(d) shows experimental observed waveforms of capacitor C 1 and C 2 voltages along with inductor L 1 and L 2 (i L1 and i L2 ) currents. The observed value of capacitor C 1 voltage (V C1 ), capacitor C 2 voltage (V C2 ) is 37.7V, and 400.33V, respectively. It is notable that the voltage across capacitor C 1 is nearly equal to input and voltage across capacitor C 2 is equal to output voltage with is expected. Fig. 18(e) shows experimental observed waveforms of voltage across switches S 1 , S 2 and S 3 along with inductor L 1 current. The total average voltage across switch S 1 is 38.07V. The total average voltage across switch S 2 is 39.4V. The total average voltage across switches S 3 +diode D (V AB ) is 38.39V, respectively. The voltage across diode D 1 and D 2 , input current and output voltage is shown in Fig. 18(f). The total average voltage across diode D 1 and D 2 is −38.2V and −326.9V, respectively. It is observed that the diode D 1 and D 2 are forwards biased during mode I and III, respectively.
At constant load R = 320 , duty ratio d 1 = 35%, and input voltage 38V; the duty ratio d 2 is regulated from 35 to 50% with the interval of 5% in order to investigate effect duty ratio on voltage gain, performance, and efficiency of the DDTM converter. The obtained waveform of input, output voltage (v 1 , v 2 ) and input, output current (i 1 , i 2 ) is shown in Fig. 20. When d 1 = 35% and d 2 = 35% (W in Fig. 20), the average output voltage, output current, input current are 205.11V, 0.64A, and 3.77A, respectively. When d 1 = 35% and d 2 = 40% (X in Fig. 20), the average output voltage, output current, input current are 236.97V, 0.73A, and 4.95A, respectively. When d 1 = 35% and d 2 = 45% (Y in Fig. 20), the average output voltage, output current, input current are 282.83V, 0.88A, and 7.06A, respectively. When d 1 = 35% and d 2 = 50% (Z in Fig. 20), the average output voltage, output current, input current are 358.2V, 1.08A, and 10.76A, respectively. Based on the experimental investigation, the efficiency graphs are plots by considering the regulation of duty ratio. Fig. 21(a) shows the plot of efficiency versus power of DDTM converter where duty d 1 is varying and d 2 is constant (35%). Fig. 21(b) shows the plot of efficiency versus power of DDTM converter where duty d 2 is varying and d 1 is constant (35%). Highest 95.47% efficiency is reported at d 1 = 50% and d 2 = 35%. After conducting several tests, 93.43% is observed average efficiency of DDTM converter.

VI. FUTURE SCOPE-DIFFERENT CONTROL SCHEMES
The output voltage of proposed DDTM converter is based on the two duty ratios d 1 and d 2 . Owing to advantages of two duty ratios, when the voltage changed the operation of proposed converter can be controlled in three possible ways 1) fixed duty ratio d 1 and variation in duty ratio d 2 , 2) variation in duty ratio d 1 and fixed duty ratio d 2 , and 3) variation in both duty ratio d 1 and d 2 .
A. CONTROL SCHEME-1: FIXED DUTY RATIO d 1 AND VARIATION IN DUTY RATIO d 2 In this scheme, during perturbations of input voltage V 1 , the output voltage V 2 is controlled at constant value by variation in duty ratio d 2 . The pulses associated this operation is shown in Fig. 22, where duty ratio d 2 is changed by +/− d 2 to achieve required output voltage V 2 . The value of +/− d 2 is based on the perturbation in input voltage −/+ V 1 . In this scheme, during perturbations of input voltage V 1 , the output voltage V 2 is controlled at constant value by variation in duty ratio d 1 . The pulses associated this operation is shown in Fig. 23, where duty ratio d 1 is changed by +/− d 1 to achieve required output voltage V 2 . It is noticeable that the duty ratio d 2 is constant; however position is changed according to new duty ratio d 1 . The value of +/− d 1 is based on the perturbation in input voltage −/+ V 1 .  In this scheme, during perturbations of input voltage V 1 , the output voltage V 2 is controlled at constant value by variation in both duty ratios d 1 and d 2 . The pulses associated this operation is shown in Fig. 24, where duty ratios d 1 and d 2 are changed by +/− d 1 and +/− d 2 to achieve required output voltage V 2 . It is noticeable that the duty ratios d 1 and d 2 is varied as well as the position of duty ratio d 2 is changed according to new duty ratio d 1 . The value of +/− d 1 and +/− d 2 is based on the perturbation in input voltage −/+ V 1 . For this scheme, variation of both duty ratios d 1 and d 2 can be possible in six different ways (given in Table-3). It is noticeable that increment or decrement in one duty ratio and decrement or increment in another duty ratio also possible to achieved desired output voltage.  The control scheme-1 and scheme-2 can be called half or independent control schemes. Since during perturbation of input voltage v 1 , only one duty ratio is varied to achieve required output voltage V 2 and the value of another duty ratio is fixed throughout the operations (d 1 is fixed in scheme-1 and d 2 is fixed in scheme-2). The control scheme-3 is called full or dependent control schemes. During perturbation of input voltage v 1 , the value of both duty ratio d 1 and d 2 is varied and dependent on each other throughout the operation.
Due to high voltage gain, unidirectional power flow, wide duty range operation, and flexibility in control and selection of duty ratio, the proposed converter is more suitable and good choice for 400V DC microgrid PV application.
Additional advantages could be a scenario in that, in future the proposed converter provides an option that one may use one duty ratio for MPPT tracking and another to control output voltage.

VII. CONCLUSION
A new Double-Duty-Triple-Mode (DDTM) converter is proposed with high voltage gain for DC microgrid application. The proposed converter topology is transformer-less and has wide duty ratio range. The higher voltage gain is achieved without employing any complex techniques like multiplier, coupled inductor, and multiple lifting techniques. The operating principle, CCM and DCM characteristics waveform, and efficiency analysis is presented in detail. The main advantages of the DDTM converter is that the voltage gain is adjusted by controlling two different duty ratios and thus, offers wide operating duty range which is not possible through any single switch converter. The DDTM converter is compared with existing topologies and it is noteworthy that the proposed converter provides a good choice to attain high voltage with reduced voltage stress on semiconductor and component count. The future scope and advantages of two duty ratios in proposed circuit and its control is discussed. The experimental results are presented which validate the performance and theoretical analysis.
MAHAJAN SAGAR BHASKAR (M'15) received the bachelor's degree in electronics and telecommunication Engineering from the University of Mumbai, Mumbai, India, in 2011, the master's degree in power electronics and drives from the Vellore Institute of Technology, VIT University, India, in 2014, and the Ph.D. degree from the Department of Electrical and Electronic Engineering Science, University of Johannesburg, South Africa. He was an Assistant Professor and a Research Coordinator with the Department of Electrical and Electronics Engineering, Marathwada Institute of Technology (MIT), Aurangabad, India. He is currently a Visiting Researcher with the Department of Electrical Engineering, Qatar University, Doha, Qatar. He has published scientific papers in the field of power electronics, with particular reference to XY converter family, multilevel dc/dc and dc/ac converter, and high-gain converter. He has authored over 100 scientific papers and has received the Best Paper Cum Most Excellence Research Paper Award from IET-CEAT 2016 and IEEE-ICCPCT 2014, and five best paper award from ETAEERE 2016 sponsored by the Lecture Note in Electrical Engineering, Springer book series. He is a Professional Active Member of the IEEE Industrial Electronics Society, the IEEE Power Electronics Society, the IEEE Industrial Application Society, the IEEE Power and Energy Society, the IEEE Robotics and Automation Society, the IEEE Vehicular Technology Society, the IEEE Young Professionals, and various IEEE Councils and IEEE Technical Communities. He received the IEEE ACCESS Award Reviewer of Month, in 2019, for his valuable and thorough feedback on manuscripts and for his quick turnaround on reviews. He is a Reviewer Member of various international journals and conferences, including the IEEE and IET.