Fundamental Modeling of the Switching Transition in High-Speed Power Electronics

Recent advances in semiconductor technology have paved the way for ultra-fast switching capabilities. This increase in switching speed enhances efficiency, power density, and frequency but also increases overvoltage oscillations at the switching node. Existing methods that effectively suppress this overvoltage include slower switching and minimisation of inductance, but unfortunately, these methods become very difficult to implement as the switching speed increases. A new oscillation suppression method, Zero Overvoltage Switching (ZOS), has previously been developed in which the overvoltage is suppressed very effectively by increasing both the switching speed and inductance, contrary to mainstream expectation. This is the only oscillation suppression method that becomes more effective as the switching speed increases and is not constrained by the minimisation of inductance, yet this method has not gained widespread recognition. This is expected because Zero Overvoltage Switching is not explained within the context of existing knowledge, and the argument for implementing it is difficult in the very narrow window where the advantages outweigh the effort. This research develops a generalised fundamental model to better understand Zero Overvoltage Switching by describing the mechanics of fast and slow switching events. The model is also able to provide insights that lead to methods to apply Zero Overvoltage Switching over a broader range of voltages and currents.


I. INTRODUCTION
Modern wide bandgap (WBG) semiconductor devices offer numerous physical improvements compared to their silicon predecessors, such as higher electron velocity, energy gap, and electric field strength.These characteristics enable them to operate at higher voltages and switch much faster, making them increasingly popular [1], [2], [3].
Faster switching has several advantages, including increased switching frequency, energy density, and efficiency [4], [5], [6], [7].However, the higher switching speed, represented by higher dv/dt and di/dt, is also responsible for several unwanted oscillations in the circuit [8].These oscillations are then responsible for several negative con- The associate editor coordinating the review of this manuscript and approving it for publication was Fengjiang Wu .
sequences, including increased losses, EMI, and component stress, leading to eventual device failure.
Additionally, other characteristics of WBG devices, such as low parasitic capacitance and low on-resistance, can exacerbate these oscillations, presenting a significant hurdle in realising the full potential of WBG technology.
The most prominent type of oscillation that is caused by the fast switching transition is the overvoltage and ringing of the switching node, where the switching node (SN) is the node where the inductor is connected to the switch.An example of the switching node can be seen in the equivalent circuit of a boost converter below in Fig. 1: In this figure, the parasitic inductance and capacitance components can be seen as well.When the switch in Fig. 1 has been turned on for a long time and then turns off, the simplified plots for the current and voltage during a slow  turn-off and a fast turn-off switching transition can be seen in Fig. 2.
It can be seen that a voltage oscillation is created on the switching node during the transition, and the faster the turn-off transition of the switch, the larger the voltage overshoot will be.The equivalent circuit resistance will eventually dampen this oscillation.
This overshoot and ringing oscillation of the switching node is caused by the resonance between the parasitic components that are first seen in red in Fig. 1.The fast switching causes these parasitic components to become excited, and the more excited the components are, the larger the overshoot will be.After the switching transition has been completed, the circuit from Fig. 1 will progress to a simplified equivalent circuit that is different for the turn-on and turn-off transitions, as can be seen in Fig. 3.
The figure shows the resonance between the parasitic components, and the equivalent resistance eventually damps out the resonance oscillation.
This resonance during the switching event has been a problem in the field of power electronics almost since its inception, and over this time, several different effective methods have emerged to suppress this phenomenon.Even though these solutions have different approaches, in the end, they all address the same resonance problem.Generally, these methods fall into one of the following categories: minimisation of parasitic inductance, switching slower, ferrite beads, Active Gate Drivers (AGD) and RC snubbers, and they are discussed in more detail in Section II.
All of these existing oscillation suppression methods represent improvements based on well-established concepts and extensive research.These interdependent approaches form a comprehensive collection of knowledge, lending credibility to their individual effectiveness.
It is known that materials are the main driver in transistor development, and Ultra Wide Bandgap (UWBG, Eg > 3.4 eV) devices are on the horizon.As semiconductor materials' switching performance parameters increase significantly as the energy gap of a material increases, the rise in energy gap from WBG devices (GaN -3.4 eV) to UWBG devices (AlGaN 6.2 eV) is expected to enhance switching speed capabilities significantly [9].
Despite being able to accommodate the current switching speed of WBG devices while effectively suppressing oscillations, current solutions become much more challenging to implement effectively as the switching speed increases.

A. ZERO OVERVOLTAGE SWITCHING AS AN OSCILLATION SUPPRESSION METHOD
A new oscillation suppression method, known as ''Zero Overvoltage Switching'' (ZOS), has recently been described [10].This solution challenges mainstream assumptions and represents a departure from the two primary approaches of decreasing switching speed and decreasing inductance.Instead, ZOS simultaneously increases switching speed and inductance, leading to surprising and unexpected results, as illustrated in Fig. 4.
Fig. 4 shows the transition period is very small, with no overshoot and ringing, contrary to the expected results.These results were experimentally verified in [11] and [12].When compared to the other suppression methods, this method becomes more effective as the switching speed increases and not less effective as the others do.This approach is also not limited by the physical constraints to minimise the inductance to achieve optimal results, which suggests that this approach holds promise as an effective suppression method.
Despite this potential, ZOS has not gained widespread recognition, as there has not been much work in this area.
It is expected that ZOS has not lived up to its mainstream potential thus far for two main reasons.The first is that ZOS is only possible in a very narrow window, and a small deviation of any of the circuit parameters from the optimal values creates a very large overshoot, making the argument for implementing ZOS difficult.
The second expected reason is the disconnect between the existing, accepted body of knowledge and the theory behind ZOS, as the two are not discussed together.An example of this can be seen specifically in [8] and [13].These two papers provide a thorough and very deep review of the current position of oscillation suppression methods, fast switching in general, and even future trends, but ZOS is not mentioned.
Additionally, [14] presented the same results as [10] very recently as an optimization strategy but does not refer to it as ZOS, nor does it reference any papers referring to ZOS.This also demonstrates that ZOS is not known to the broader power electronics community.
However, this research aims to bridge these two issues mentioned above by developing a fundamental model that contextualises ZOS within conventional switching assumptions and explores its implications for very fast switching.This model is then able to provide a framework of the fundamental mechanisms and effects of very fast switching so that it can be understood.
This understanding then paves the way for methods to achieve ZOS at non-ideal and realistic switching speeds, as well as broadening the window period of ZOS so that it can be utilised over a larger design range.
This paper is not meant to be a design guide but, rather, a pathway to build upon and provide a fundamental contribution to the work that has already been done in ZOS and fast switching in general.The insights and principles produced by the model in this research are meant to assist the designer in the initial decision-making process when the converter is conceptualised.The model can then inform the designer of the influences that the target parasitic values and switching speed have on the overshoot before experimental results are produced.
The main contributions of this paper are: • A mathematical model that is able to describe the switching event and is then able to simultaneously explain the results of very fast switching and slow switching.
• An approach that can provide preliminary insights into the switching behaviour of a circuit.
• Insights on the use and application of existing oscillation suppression methods when switching very fast.
• Potential oscillation suppression methods when switching very fast but with a non-ideal switching transition.The layout of the paper is as follows: Section II reviews and compares the existing oscillation suppression methods with a focus on methods used for WBG devices.A summary table is presented with high-level advantages and disadvantages for each method.
Section III explains how the actual fundamental model was derived, and alternative equivalent circuit progressions are presented and named Fast-Mode and Slow-Mode.A discussion is presented on how to apply some of the derived equations to determine the anticipated overshoot of a switching circuit.
Section IV delves into an energy transfer representation through the switching transition and discusses how the energy transfer between the parasitic components can have varying levels of effectiveness, which causes the overshoot and ringing.From this approach, alternative prerequisites for ideal energy transfer are discussed and proposed.
Section V then uses insights from the mathematical model to discuss the implications of when existing oscillation suppression methods are implemented when switching in Fast-Mode circuit progressions and which methods will still be relevant.
Section VI then discusses alternative oscillation suppression methods that can be used in Fast-Mode to achieve energy balance through the switching transition and their trade-offs.
Section VII discusses the implications of this research on the field of power electronics in general.
Section VII provides the conclusion of the paper.

II. EXISTING OSCILLATION SUPPRESSION METHODS
As discussed above, several accepted oscillation suppression methods already exist to solve the very old problem.These solutions form a well-rounded collection of knowledge and are discussed in this section.

A. MINIMISATION OF PARASITIC INDUCTANCE
The primary cause of overvoltage is the resonance between the parasitic electromagnetic components.When the image in Fig. 3 above is considered, it can be seen that reducing parasitic inductance also reduces the overvoltage.Minimising parasitic inductance is an obvious and very effective approach and can be achieved mainly in three ways.The first is device selection.This is an easy approach to simply select a switching device that has the lowest parasitic inductance and this can be read from the datasheet [15], [16].
Second is the layout optimisation to reduce the power loop inductance, which can be achieved by many innovative approaches.Generally, the circuit is optimised by minimising the footprint and by creating lateral power loops, vertical power loops, or optimisation between the two.This approach has reported results of less than 1 nH [13], [17], [18], [19].
And lastly is the approach to optimise the device packaging.In this approach, only the die of the switching device is used, and the package in which the die is placed is designed and implemented.This method has also reported results of less than 1 nH parasitic inductance in experimental results [20], [21], [22].
However, even with a combination of all the approaches mentioned above, the parasitic inductance can only be decreased so much, and further improvements become challenging, especially as dv/dt and di/dt increase.

B. SLOWER SWITCHING
Lowering the dv/dt and di/dt by using a gate resistor or implementing a driver that can switch slower can suppress the excitation of parasitic components and increase the stability of the switching event.This is illustrated in Fig. 2, where the overshoot is lower for a slower switching event than for a faster switching event.However, this method leads to increased switching losses [23], [24].

C. FERRITE BEADS
Adding Ferrite beads to the circuit provides a frequencydependent resistor that can dampen high-frequency oscillations while allowing DC to pass.This method is more effective in reducing the oscillation duration than the peak but slightly increases conduction losses [23], [24], [25].

D. ACTIVE GATE DRIVER
An Active Gate Driver (AGD) refers to an umbrella term where a specific focus is placed on the gate driving circuit instead of the power loop circuit.With AGDs, the gate driver circuit can adapt the gate voltage, current, or impedance using an auxiliary circuit.The aim of how the switching device is turned on or off can vary greatly, but several different approaches have been effective in reducing the eventual voltage overshoot and ringing.

E. RC SNUBBERS
Adding an RC snubber is an effective method to suppress switching oscillations, which has been used in power electronics almost since the inception of the research field.This approach involves modelling a simplified RLC circuit for the turn-on and turn-off equivalent circuit and adding an RC bridge to dampen the oscillation, as shown in Fig. 5.The values of C snub and R snub can be calculated to create a critically damped system at the ringing frequency.Generally, this approach can be categorised into second-, third-, and high-order designs.The second-order design, based on the simplified model, is relatively easy to implement but has limited suppression effects and slightly increased losses [25], [42], [43].The third-order design involves a more complex circuit to account for additional parasitic parameters and determines the values of R and C using the root locus method of stability.It offers good suppression effects but comes with a slightly more complex design and slightly increased switching losses [44].High-order design, while more complex and difficult to solve, has similar drawbacks of slightly increased switching losses and complexity but can offer better suppression and stability than lower-order design [45], [46], [47], [48], [49].
In [50], a C-RC snubber is introduced.The calculation for the component values is complicated but effective in the ability to suppress the voltage overshoot.

III. REALISATION OF FUNDAMENTAL MODEL
A single model that is able to explain the results of ZOS and conventional expected results simultaneously is required to bring the two branches together.To achieve this, the switching node of a boost converter is investigated.This node of a boost converter is chosen as it is where the overshoot phenomenon is a major concern, and this node is applicable to other commonly used converter types, like synchronous buck converters.The equivalent circuit is seen in Fig. 1 above.
Several assumptions must be made to the circuit to be able to model the switching transition effectively.The first is the consideration of the intent of the model, which is to investigate the effect of both the parasitic components and the turn-off speed of the switch on the overshoot of the switching node votlage.Thus, the lumped circuit parasitic components and turn off of the switch are modelled explicitly.The turn-off of the switch is modelled by replacing the switch with a decaying current source from I in to zero.
Additionally, the assumption is made that the size of the input inductor and output capacitor is very large compared to the parasitic components and the time period of the investigation is very small, so the input inductor and output capacitor are replaced with a current source and voltage source, respectively.The circuit from Fig. 1 can then be converted into Fig. 6.In this circuit, the turn-off current of the switch is assumed to be linear, and the turn-off period can be adjusted as required to model the opening of the switch.An equation that satisfies these requirements can be seen below: In this equation, T Fall refers to the time required for the current through the switch to reach zero and thus is also the current transition period.The assumption that the current through the switch decays linearly is made to show underlying fundamental dynamics without clouding them with the higher-order effects of different semiconductor switching models.
This circuit can be seen to have six degrees of freedom, or variables that can be chosen by the designer, and it must be noted that the introduction of each additional degree of freedom greatly increases the complexity of the model.These Together, these variables form a circuit environment, and all the subsequent waveforms are interdependent on all of these variables.The equivalent resistance is not considered at this stage due to the complexity of the model and does not have a big influence on the overshoot magnitude.
To analyse this circuit in Fig. 6, a conventional approach of circuit analysis using Kirchoff's current and voltage laws is used to determine the time domain equations.The Laplace transforms are then used to solve the variables of V Switch (t), V Diode (t) and I LPar (t) and then converted back to the time domain using inverse Laplace transforms.This analysis starts when the switch starts to turn off.
As the voltage and current progress through the time domain, it is seen that the equivalent circuit that is relevant to the specific time period will change.The two events that will change the equivalent circuit and their effects are: 1) Clamping of the diode -As the diode becomes forwardbiased, C Diode will be short-circuited and can be ignored in the circuit analysis after the event.
2) The switch turns off fully -when the current through the switch reaches zero, the current source representing the switch becomes an open circuit and can also be removed from the equivalent circuit.The values at the end of a specific period are then used as the initial conditions for solving the variables in the following period.The math becomes very complicated as the equivalent circuits progress, and the full mathematical results can be seen in the appendix.
The results of this approach can be seen in Fig. 7 below.From the investigation, it is seen that, depending on the combination of choices of the variables mentioned above, either the diode can clamp first or the switch can fully turn off first.This means that depending on the variables, different equivalent circuit progressions will be followed.
The alternative circuit progressions from Period 1 (P1) to Period 3 (P3) are named Slow-Mode and Fast-Mode circuit progressions for simplicity.
In Slow-Mode circuit progressions, the diode clamps before the switch is fully turned off, and this progression is the equivalent circuit progression of mainstream conventional switching.
In Fast-Mode circuit progressions, the switch fully turns off and becomes an open circuit before the diode clamps.This is only possible in very fast switching transitions and is the circuit progression when ZOS is presented.A comparison of the switching events of a slow switching event of Slow-Mode and a very fast switching event of Fast-Mode can be seen in Fig. 8 and Fig. 9, respectively.
In these comparisons, it can be seen that the voltage overshoot oscillation will occur when the diode clamps and this happens at different time periods for Slow-Mode and Fast-Mode.
For Slow-Mode, the voltage overshoot will occur in Period 2 (P2), and for Fast-Mode, the overshoot will occur in Period 3 (P3).This means that the voltage rise of the switching node is not directly dependent on the turn-off time of the switch but rather dependent on the time it takes for the diode to clamp.
It must be noted that the time it takes for the diode to clamp (V Diode (t) to reach zero) naturally occurs and is a secondary effect of the choice of parasitic components and the turn-off time of the switch, but it is a very important occurrence in the progression.This point in time is referred to as T Clamp .
This overshoot oscillation will be dampened if equivalent resistance is included in the model.
When the turn-off period T Fall (Current switching period) is plotted against the maximum overshoot of a circuit on a logarithmic scale with the same parasitic components as used for the plots in Fig. 8 and Fig. 9, the plot can be seen in Fig. 10.
In Fig. 10, itSlow-Mode on the right-hand side of the plot is an example of conventional switching.In this part of the plot, it is seen that the overshoot decreases as the switching period increases, which is according to mainstream expectations.An example of the waveform of slow switching is seen above in Fig 8 .time for the diode to clamp, and this section  generally accounts for the largest overshoot of the entire plot.An example can be seen in Fig. 11: The left-hand side of the plot in Fig. 10 shows when the circuit is operating in Fast-Mode.It can be seen that the overshoot drastically decreases, and this decrease in voltage is against mainstream expectations.
The transition between Slow-Mode and Fast-Mode will occur when the turn-off time of the switch is equal to the time  the diode takes to clamp, or described mathematically below: This point in time is dependent on all six of the variables described above.This makes this point difficult to derive mathematically, so the roots of the function are solved analytically when all the variables are available.
It is important to note that this transition point between Slow-Mode and Fast-Mode exists for all combinations and ratios of positive values of the parasitic components.This means that eventually, and independent of the oscillation suppression method that is applied, all switching events will reach the transition point if the speed increases enough.Therefore, given that the switching speed of devices is increasing, a better understanding of Fast-Mode is required.Specifically, it is to fundamentally understand how the circuit parameters and switching speed translate to the overshoot.
These overshoot results of Fast-Mode are expected and are also experimentally verified in both [11] and [12].This difference between the overshoot expectations of Slow-Mode and Fast-Mode is fundamentally because of the alternative circuit progression, the different circuit conditions, and different stored energy values in the parasitic components when the overshoot occurs.

1) MODEL APPLICATION DISCUSSION
The resulting plot presented in Fig. 10 is a very good preliminary design tool that is able to predict the switching performance of a circuit with the chosen parameters of the designer long before the circuit has been built.The plot will be able to assist with decisions of switching speed or parasitic inductance and the trade-off thereof.
When the six circuit variables mentioned above have been estimated or chosen, the designer can slot the variables into the model equations presented in the appendix, and with the help of mathematical software, some important predictions of the circuit can be calculated.
The first step must always be to calculate if the chosen parameters would have the circuit operating in Slow-Mode or Fast-Mode to know which set of equations is applicable.This can be done by calculating the time taken for the diode to clamp (T Clamp ) under the chosen variables by calculating the roots of (2) using ( 13) in the appendix.
It is advised that the design must ensure that the switch turn-off time (T Fall ) is much faster or slower than the calculated (T Clamp ), as this is the largest predictor of the overshoot.
Once T Clamp has been calculated and the determination is made if the set of Slow-Mode or Fast-Mode equations must be used, the overshoot can be calculated.
When operating in Slow-Mode, the variables can be plugged into (16), and the maximum value of the oscillation can be calculated.When operating in Fast-Mode, the variables must be plugged in (9).It must be noted that the value of T Clamp must be recalculated if any variable is adjusted.
A similar graph to the one presented in Fig. 10 can be reproduced if desired, and all the model equations can be found in the appendix.

IV. THE UNDERLYING MECHANISM OF THE VOLTAGE OVERSHOOT
When the entire switching transition is considered, including the time before the switching transition and a long time after the switching transition, the waveforms below in Fig. 12 will be applicable in a fast-switching event for a circuit with damping in Fast-Mode.
When the period before the switch is considered, P0, it can be seen that the switch has been closed for a long time, and there are no oscillations.P4 is after the switch has been open for a long time and all the oscillations and resonance have been damped out.The equivalent circuit transition from P0 to P4 with an emphasis on energy storage of the reactive components can be seen below in Fig. 13.
It can be seen that in P0, only C Diode is storing the energy of the full value of V Out .In P4, C Diode has been short-circuited by the diode, and there is only energy stored in C Switch and L Par .
The investigation into the switching transition can, in essence, be seen as an attempt to effectively manage the process to get the energy stored in the passive components from P0 to P4 as well as possible, where what happens in P1 to P3 can be manipulated.
As the equivalent circuit progressions of Slow-Mode and Fast-Mode are different, the underlying mechanism of the overshoot and energy transition requirements are also different.These differences are investigated separately below.

A. EFFECTIVE ENERGY TRANSFER FOR IN FAST MODE
When the overshoot of Fast-Mode is considered with the relevant equivalent circuit, it can be seen that the overshoot oscillation starts when the diode clamps and the equivalent circuit progresses to a resonance circuit, which can be seen in P3.
When the resonance circuit is considered in isolation, as seen in Fig. 14, it is known that the amplitude of the resonance in a circuit is determined by the initial conditions of the period if the other circuit parameters are fixed.
This then means that if the initial conditions of P3 are such that the voltage over the capacitor is equal to V Out , and the  current through the inductor is equal to I in , at the exact time the diode clamps, no overshoot will happen.In essence, this means that the energy stored in both C Switch and L Par must be the same as the energy stored in the components in P4 (after oscillation) for no overshoot to occur.
If the assumption is made that the switching period is infinitely small and that the capacitors are equal, the conditions for the optimal energy transfer described above can be derived from the model, and the resulting equation can be seen: For this equation to hold, the values of C Switch and C Diode must be the same and is equal to C Switch .The value of n can be any integer larger than one and indicates the optimized point of operation will occur again when one of the variables changes.This equation is similar to those presented in [11] [12], and when this equation is applied to the parameters of the overshoot plot in Fig. 10 above, with the choice of inductance as the variable, the following plot of Overshoot vs Switching speed can be seen in Fig. 15.When two of the switching waveforms of the different points of operation from the graph above are investigated, the comparison of an ideal and ineffective energy transfer switching event can be seen in Fig. 16.From these waveforms, it can be seen that the mismatch in energy between the initial conditions of P3 and the required energy conditions of P4 produces the voltage overshoot, and the larger the mismatch, the larger the overshoot will be.As the inductance value is much larger than the capacitance value, the energy mismatch caused by a mismatch in the current of the inductor is punished much more severely than the energy mismatch in the voltage of the capacitor.

1) OPTIMISATION FOR NON-IDEAL SWITCH
An important addition is that this described optimal energy transfer can also be achieved when the turn-off period is not ideal and when the capacitors do not match, but as stated above, the introduction of two more degrees of freedom also introduces very high complexity to the model.Thus, this point of operation also cannot be mathematically derived due to the interdependencies of the variables, but a numerical method of calculation is able to find the combination of parameters that can display this optimised point.
In this numerical method, a solution only exists if all the values are chosen except for the capacitance values.This indicates that the relationship between the capacitance values is also a very important ratio.
Fig. 17 shows the plot comparing the voltage overshoot and the turn-off period of the optimised points for the non-ideal switching transition.These points of operation are found when optimising for three different turn-off periods while keeping the inductance the same as in the plot above and finding the correct capacitance values.In this plot, it can be seen that the longer the turn-off period is optimised for, the greater the overshoot sacrifice is when not switching at exactly this point.
Additionally, the longer the turn-off period point of optimisation, the greater the ratio between the diode switch capacitor has to be.

B. EFFECTIVE ENERGY MANIPULATION FOR SLOW MODE
When a similar approach is followed for Slow-Mode, it is seen that the voltage overshoot happens at the start of P2 and when the diode clamps, but not in P3, like in Fast-Mode.This means that the equivalent circuit in Fig. 18 will be applicable when the voltage oscillation starts.
In this circuit, the switch is not yet fully turned off when the oscillation starts, so the energy stored in L Par cannot be the same as in P4.To be able to determine the initial conditions of P2 that the I LPar (t) is supposed to be for no oscillation,  the circuit is simplified.The input current and switch current are combined for a similar circuit, as seen P3.
This means that for no overshoot to occur, the voltage over the capacitor must be equal to V Out , and the current through the inductor must be I in − I Switch (t) at the exact moment the diode clamps, and the oscillation is supposed to start.
An example can be seen in the waveform comparison below in Fig. 20, where the inductance is lowered.It is seen that the smaller the mismatch in current or the smaller the energy mismatch, the smaller the voltage overshoot will be.
From the energy mismatch approach, the inductor current must then be as close as possible to the calculated point when the diode clamps, and this can be done relatively easily in two ways.
The first is to increase the slope of the inductor current in P1, which can be done by decreasing the inductance as much as possible, and the second is to make P1 longer, which can be done by switching slower.
Decreasing the inductance or decreasing the switching speed are the two most known methods of decreasing the voltage overshoot, which shows that mainstream attempts to minimise overshoot are just a secondary consequence of lowering the energy mismatch at the start of P2.
Unfortunately, the equation can only be satisfied if there is no inductance in the circuit, which in turn means that perfect optimal energy transfer in Slow-Mode switching is not possible as the inductance cannot be reduced to zero.

V. APPLICATION OF SLOW-MODE OSCILLATION SUPPRESSION METHODS IN FAST-MODE SWITCHING
As discussed in Section I, several existing methods have successfully managed and minimised the overshoot when switching to conventional Slow-Mode.But as discussed in Section II, all fast-switching devices will eventually transition into Fast-Mode, and the equivalent circuit progression and the mechanism underlying the overshoot are different.This means that the mainstream oscillation suppression methods might not be applicable in Fast-Mode switching.This section will re-evaluate the oscillation suppression methods mentioned in Section I to determine if they are still applicable to Fast-Mode switching.

A. MINIMISATION OF PARASITIC INDUCTANCE
From the experimental results presented in [10], it is already known that the assumption that lowering the parasitic inductance will lower the overshoot is not true in Fast-Mode.To further demonstrate this, a similar graph to that of Fig. 5 is presented, where the circuit model is used to determine the overshoot versus the fall time.In this figure, four inductance values are chosen: 1.) Very low 2.) low 3.) High and 4.) very high.
In the plot, the dot refers to the point where each plot transitions between Slow-Mode and Fast-Mode.The graph shows that the overshoot increases as the inductance increases, as expected in conventional Slow-Mode but not in Fast-Mode.When switching to Fast-Mode, the goal of minimisation of parasitic inductance must be shifted to that of an optimal energy transition and not minimisation.
When the limitation of minimisation of inductance does not constrain the layout and packaging of a device, more emphasis can be given to other parameters, such as cooling or even just switching speed.

B. SWITCHING SLOWER
As stated in Section II, switching slower while operating in Fast-Mode will lead to a large voltage overshoot long before the transition is made to Slow-Mode, and the overshoot starts to decrease.This means that Slower switching is not an effective oscillation suppression method in Fast-Mode.

C. FERRITE BEADS
As ferrite beads do not influence the circuit environment of the switch and only provide a high-frequency dependent resistor, this method will still be applicable in Fast-Mode switching.

D. ACTIVE GATE DRIVER
As an AGD can actively adapt the gate driver and, in so doing, actively shape the turn-off waveform of the switching current, it is expected that Active Gate Drivers will remain a research sweet spot with Fast-Mode and Slow-Mode.
When the goal of the AGD is changed to optimal energy transfer, the driver will be able to adapt the turn-off waveform in such a way as to have the correct energy at the required point in time.The successful application of an AGD will then be able to achieve energy balance over a range of inductor currents, shaping the waveform as required.

E. RC SNUBBERS
The applicability of RC snubber in Fast-Mode switching is considered to be a whole investigation on its own.The inclusion of an RC snubber would affect the circuit environment of the entire switching circuit, and the effects on the main idea of achieving optimal energy transition would be a very complicated question to answer.

VI. POTENTIAL OSCILLATION SUPPRESSION METHODS OF FAST MODE
One of the main hurdles to the implementation of ZOS is that the point of operation where the benefits outweigh the effort is very narrow, and a small difference from the optimisation equation in voltage, current, inductance, or capacitance creates a very large overshoot.This means that, practically, it is not an attractive solution if the load cannot vary in the slightest.This point of operation is even narrower when optimised for a non-ideal switching transition.Additionally, it would be very difficult to achieve the designed point of operation practically.
This hurdle can be overcome by widening the area of operation or creating multiple areas of operation, and methods to achieve this are discussed in this section.The widening of the area of operation is also going to be the main research direction in Fast-Mode switching research and is also the main goal of [11] and [12].

A. COMPENSATION FOR NON-IDEAL SWITCHING EVENT
As an ideal switching event is not possible, methods to achieve effective energy transition with a non-ideal switching event must be investigated.
In Section IV, Fig. 17, an example of achieving no overshoot with a non-ideal switching event is presented, and in Fig. 15, an optimisation for ideal switch is presented.
When a switching event is considered, and the allowable overshoot is relaxed from 0% to 5%, a window period where the overshoot is below 5% can be measured and compared.In Fig. 22, a comparison can be seen when a circuit is optimised for a non-ideal switching event and for an ideal switching event.
It can be seen that the window period of the ideal switching event is 1.6 ns when the overshoot is below 5%, and the window period is 1.2 ns for the non-ideal switching event.So, if a fast switch is available, optimising for an ideal switch would be better than a non-ideal switch.
Additionally, to minimise the penalty of a slower switching event, one can again return to the optimisation equation (3).In this equation, it can be seen that the equation is dependent on the relationships between the voltage and current and the inductance and capacitance and not on the values themselves.
This means that the overshoot graph, as seen in the figure above, is translatable.When both the parasitic inductance and capacitance are increased with the same ratio, the overshoot graphs can be translated as seen in Fig. 23.
In Fig. 23, the overshoot of a switching transition of 3.2ns is reduced from 18% to 5% by doubling parasitic components, where 3.2ns is considered to be a realistic transition period with WBG technology available.
However, the amount by which the parasitic components are increased must be kept as small as possible, specifically the capacitance.The capacitance will directly influence the speed of the switch, and a better gate driver will have to be employed to keep the transition period very small while increasing the parasitic capacitance.Keeping in mind a fasterthan-designed switching transition will have better results.

B. COMPENSATION OF RANGE OF CURRENT
When the optimisation equation ( 3) is considered again, another important consideration can be seen.
This was mentioned in [12], which discusses how the presence of the n value creates more than one optimisation point.If a circuit is optimized according to (3), n is chosen as 1, and the switching speed is infinitely fast, the overshoot will be zero.If the current, I Lpar , becomes larger, the overshoot will increase indefinitely, but if the current becomes smaller, the overshoot will increase up to a maximum and then decrease until another optimization point is reached again.This next optimisation point will occur when n is equal to 2 or when I Lpar is equal to I In /3.This reoccurring optimisation point will occur closer and closer to each other as the current decreases, as can be seen in Fig. 24.
A plot similar to the one presented in Fig. 24 can be reproduced for any parameter change from (3).
When the inductance is considered, a very similar plot will be reproduced, as another optimized point will reoccur when the inductance is lowered but will not reoccur when the inductance is increased.
The inverse is true for the capacitance and the voltage.If the capacitance or voltage is decreased, the optimised point will not reoccur but will reoccur if the capacitance or voltage is increased.

VII. RESEARCH IMPLICATION DISCUSSION
The main aim of this research is to extend the modelling of a switching event to encompass both the existing well-known behaviour and the behaviour under very fast switching conditions.
The mathematical results show that when the turn-off speed is fast enough, the circuit will respond in a different  manner as expected, thus, the existing approaches will have to adapt as well.
This model also shows that the point when the circuit progression will change from Slow-Mode to Fast-Mode is solvable for all possible values of the variables.Therefore, the Fast-Mode equivalent circuit progressions and modelling show great promise for realising the advantages of wide and ultra-wide bandgap devices.

VIII. CONCLUSION
This research presents a fundamental model of the switching node of the turn-off switching transition of a boost converter with parasitic components and an explicitly modelled turn-off transition.From the model, it was found that an alternative equivalent circuit progression is responsible and can explain and predict all the results from ZOS while also explaining the expected results from conventional switching.An optimal energy transition theory is presented to provide a fundamental explanation of why the overshoot exists and how to address the underlying energy mismatch to minimise the eventual voltage overshoot.Lastly, a potential solution to widening the ZOS operation area is suggested by incorporating larger parasitic components.The principles established in this paper can be built upon to eventually become the building blocks to realise the potential of WBG and UWBG technology.

APPENDIX MATHEMATICAL EQUATIONS
See Tables 2 and 3.

FIGURE 1 .
FIGURE 1. Boost converter equivalent circuit with parasitic components.

FIGURE 2 .
FIGURE 2. Comparison of the voltage overshoot of the switching node when switching (a) Slow and (b) Fast.

FIGURE 3 .
FIGURE 3. Equivalent circuits of the resonance between parasitic components that cause voltage overshoot in the (a) turn-off and (b) turn-on transition.

FIGURE 5 .
FIGURE 5. Equivalent circuits of a switching node without (a) and with (b) a snubber circuit.

FIGURE 6 .
FIGURE 6. Modified Equivalent circuit of a boost converter switching node.
variables are: 1) I in − − Input Current 2) V out − Output Voltage 3) T Fall − Time taken for the switch to turn off fully 4) C Diode − Parasitic Capacitance of Diode 5) C Switch − Parasitic Capacitance of Switch 6) L Par − Cumulative Parasitic Inductance of Power Loop

FIGURE 7 .
FIGURE 7. Alternative equivalent circuit progression for Slow-Mode and Fast-Mode.

FIGURE 8 .
FIGURE 8. Slow-Mode circuit progression waveforms of voltage and current.

FIGURE 9 .
FIGURE 9. Fast-Mode circuit progression waveforms of voltage and current.

FIGURE 10 .
FIGURE 10.Voltage Overshoot Percentage vs. Turn-off period of switch.

FIGURE 13 .
FIGURE 13.Equivalent circuit From P0 to P4 Highlighting energy storage of reactive components.

FIGURE 14 .
FIGURE 14. Equivalent circuit of oscillation circuit of P3.

FIGURE 15 .
FIGURE 15.Voltage Overshoot vs Switching Speed when Optimisation equation is applied.

FIGURE
FIGUREFast-mode comparison of switching node waveforms for optimal energy transfer vs. non-optimal energy transfer.

FIGURE 17 .
FIGURE 17. Overshoot vs. switching speed when optimised for non-ideal switching event.

FIGURE 20 .
FIGURE 20.Slow-Mode switching node waveforms for non-optimal energy transfer.

FIGURE 21 .
FIGURE 21.Voltage overshoot vs switching speed of four increasing inductance values.

FIGURE 22 .
FIGURE 22. Voltage overshoot vs switching speed comparison when optimising for non-ideal switch and ideal switch.

FIGURE 23 .
FIGURE 23.Voltage overshoot vs switching speed comparison when components are doubled.

FIGURE 24 .
FIGURE 24.Voltage overshoot vs Input Current comparison when current is decreasing.

TABLE 2 .
Fast mode equations derived from mathematical circuit model.Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE 2 .
(Continued.) Fast mode equations derived from mathematical circuit model.

TABLE 3 .
Slow mode equations derived from mathematical circuit model.Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE 3 .
(Continued.) Slow mode equations derived from mathematical circuit model.