Impact of Device-to-Device Thermal Interference Due to Self-Heating on the Performance of Stacked Nanosheet FETs

The stacked nanosheet field effect transistor (SNSHFET) exhibits superior electrostatic performance with its increased effective channel width. However, as the technology node progressing towards angstrom dimensions, self-heating became one of the major challenges in SNSHFETs due to their confined geometry. The self-heating impacts not only the respective device, but also its contiguous device on the same substrate. In this paper, the thermal impact of heat stacked nanosheet FET (He-FET) on proximal cool stacked nanosheet FET (Co-FET) is studied at 7 nm technology node. Thermal impact on DC and analog/RF performance of Co-FET is deliberated by varying the inter-device spacing (IDS) and shallow trench isolation (STI) depth between the two stacked nanosheet FETs. It has been observed that, self-heating induced thermal energy of He-FET shows more impact on the bottom channels compared to the top channels in the Co-FET. The electron mobility is reduced by 4.25% in the channel near to the substrate compared to the channel near to contacts. The transit frequency (fT) and the maximum oscillation frequency (fmax) of 131.5 GHz and 435 GHz were obtained, respectively with the optimization of IDS of 30 nm and STI depth of 50 nm.


I. INTRODUCTION
The technology node scaling led to several non-conventional field effect transistor (FET) structures like FinFET, nanowire FET and nanosheet FET.The gate-all-around (GAA) stacked nanosheet field effect transistor (SNSHFET) clasped more attention due to its excellent electrostatic characteristics, higher drive current, and reduced short channel effects.Therefore, it is widely used in high-performance computing, low power and RF applications, such as microprocessors and digital logic circuits, radio frequency amplifiers, low noise amplifier, and radars, etc [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11].However, besides its stupendous advantages, it suffers from self-heating which affects the The associate editor coordinating the review of this manuscript and approving it for publication was Sneh Saurabh .
DC and analog/RF performance of the device.The vertical geometry of device and poor thermally conductive gate oxide constrained the heatsink pathways in SNSHFETs [12].However, the channel is operating at high voltage, and the current density, in combination with heat and poor thermal dissipation, results in a significant self-heating effect (SHE) [13], [14], [15], [16].In other words, the charge carriers in the channel gain high energy due to the drain electric field.When electron collides with the atoms in the drain, this energy is converted into heat and descended in the drain junction.
Several works were proposed in the literature explaining the impact and mitigation of self-heating in stacked nanosheet field effect transistors.Kang et al. [17] proposed wrap around contact, with which the thermal resistance reduces and improves self-heating performance of nanosheet FET.Venkateswarlu et al. [18] presented a comparative analysis of electrothermal performance of different contact structures of SNSHFET such as epi-based top contact, wrap around, and trench-based contacts, in which the latter one gives superior performance.Su et al. [19] proposed to increase the gap to reduce the thermal resistance and high thermal conductivity metals for gate contact of nanosheet FET.Yoo et al. [20] investigated the effect of bottom oxide with face-up and face-down packages for nanosheet FET and found that SHE is more profound in the former case.Jegadheesan et al. [21] proposed a super steep retrograde silicon substrate to suppress the self-heating in SNSHFETs.Rathore et al. [15], [22] investigated analog/RF and linearity performance of nanosheet FET and proposed diamond-likecarbon which has higher thermal conductivity, in place of SiO 2 to improve the thermal reliability of silicon-on-insulator structures.Tsen et al. [23] proposed inter-bridges between stacked channels to improve the device heat dissipation and reduce temperature difference among the channels of treeFET.Kumar et al. [24] investigated the influence of doping concentration and ambient temperature on the self-heating of the device in SNSHFET.Jeong et al. [25] proposed a trench inner spacer to reduce the thermal resistance and thereby the lattice temperature of nanosheet FET.Myeong et al. [13] found that the lattice temperature decreases with the increase in device operating frequency and decrease in duty cycle in nanosheet FET.Cai et al. [26] given the layout design optimizations to suppress the thermal effects, including self-heating, nonuniformity of temperature, and thermal crosstalk at device level in which they proposed thermal crosstalk ratio to quantify the thermal exchange between adjacent SNSHFETs.In all these works, the cause, impact of the selfheating effect, and its mitigation mechanisms were discussed extensively.This work is, the first of its kind, to investigate the impact of self-heating from heat stacked nanosheet FET (He-FET) induced thermal energy effect on DC and analog/RF performance of adjacent cool stacked nanosheet FET (Co-FET) on the same substrate.In this, the DC parameters such as on-current, off-current, threshold voltage and analog/RF parameters such as transconductance, transit frequency and maximum oscillation frequency were profoundly investigated through extensive Technology Computer Aided Design (TCAD) simulations by varying the shallow trench isolation depth (d STI ) and inter-device spacing (IDS).The proposed device mitigates the thermal intruding from heat SNSHFET to neighboring cool SNSHFET, improve the device performance and helpful in designing the highperformance computing, low power and RF applications, such as microprocessors and digital logic circuits, radio frequency amplifiers, low noise amplifier, and radars, etc.The article is organized as follows.Section II describes the device virtual fabrication methodology and simulation framework using Synopsys Sentaurus TCAD and device calibration by comparing simulated I D -V GS characteristics with experimental data.Section III explains the impact of shallow trench isolation depth and inter-device spacing on oncurrent, off-current, transconductance, transit frequency, and maximum oscillation frequency of Co-FET from He-FET.The optimized STI depth and IDS are presented in section IV.Finally, the article is summarized and concluded in section V.

II. VIRTUAL FABRICATION PROCESS FLOW AND DEVICE SIMULATION FRAMEWORK
The stacked nanosheet field effect transistor structure is created using Synopsys Sentaurus process (SProcess) TCAD [27].In this work, 7 nm ground rules as presented in [2] are used.The device parameters considered during the  virtual fabrication process flow of structure are mentioned in Table 1.Punch-through stopper (PTS) substrate with an acceptor doping concentration of 1×10 19 cm -3 is used to minimize the leakage current and to avoid the parasitic channel formation in the substrate (Fig. 1 (a)) [21].A stack of SiGe/Si/SiGe/Si/SiGe/Si is deposited onto the PTS substrate (Fig. 1 (b)).The isotropic etching forms the stack of channels and also provides room for shallow trench isolation in which oxide is deposited (Fig. 1 (c) and (d)).The polysilicon dummy gate is deposited followed by the source/drain formed by the selective epitaxial growth of silicon (Fig. 1 (e) and (f)).The SiGe sacrificial layer is fully removed to determine the space for the gate stack.After the deposition of spacer, to improve the interface quality and to reduce the trap density at channel-oxide interface, silicon oxide (SiO 2 ) is deposited on the channel, followed by high-κ dielectric oxide (HfO 2 ) is deposited on SiO 2 and further rapid thermal annealing is performed (Fig. 1 (g)-(i)) [28], [29].Finally, the gate metal and the contact electrode metal are deposited [2], [30].Till this, one stacked nanosheet FET is created.Another symmetrical SNSHFET is deployed by using reflecting feature of SProcess.Thus, the final structure consists of adjacent SNSHFETs on the same substrate as shown in Fig. 1 (j).A pair of 3D schematic of three level vertically stacked nanosheet field effect transistors sharing the common substrate and its cross sections along and across the channel are depicted in Fig. 2 (a), (b) and (c), respectively.The overall methodology followed in this work is shown in Fig. 3.In the figure, steps 1-3 are the device creation and calibration with the experimental data explained in this section, and the steps 4, 5 and 6 are the objective of this work, explained in section III and IV, respectively.
The stacked nanosheet field effect transistor is calibrated at first by considering one device.The remaining analysis is carried out with two devices on same substrate later, which is illustrated in section III.The SNSHFET calibration is as follows.The Sentaurus device (Sdevice) simulator [31]    1.28 nm) is considered.Simulated transfer characteristics of SNSHFET are matched with the experimental data [2] as shown in Fig. 4 for V DD of 0.65 V.

III. RESULTS AND DISCUSSION
The maximum heat energy flowing into the neighbor device is expressed as lattice temperature.The lattice temperature can be obtained using thermodynamic model.It accounts for self-heating in the devices, particularly for the devices like stacked nanosheet FET, which have confined geometry, low thermal exchange and high power density.Therefore, thermodynamic model available in SDevice simulator is used to obtain the lattice temperature in both SNSHFETs and the initial temperature assumed at thermal contacts is 300 K.The lattice temperature distribution of stacked nanosheet He-FET and Co-FET and its cross-section profile along the mid-line of the channel is shown in Fig. 5 (a) and (b), respectively.Here, the He-FET (left-side) is operated at saturation (V GS = V DS = 0.65 V) and the Co-FET (rightside) is operated in linear (V GS = 0.65 V and V DS = 0.05 V).The thermal energy generated due to the self-heating of He-FET has to be dissipated through the contacts and the substrate.However, since the devices are sharing a common substrate, the heat dissipating through the substrate trespass 26404 VOLUME 12, 2024 Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.into Co-FET as shown in Fig. 5 (b).The trespassing heat reaches the Co-FET from He-FET by conduction process through the substrate.Therefore, it raises the temperature in the channels of Co-FET, leads to electron scattering in turn tends to mobility degradation and velocity saturation in Co-FET.This impact is more on the bottom channel of Co-FET compared to top channels due to the heat conduction into it through the substrate.Hence, the electron mobility profile of the SNSHFETs cross section along the channel is shown in Fig. 6 and, Fig. 7 is the electron mobility along the mid cut-line of different channels.Therefore, from Fig. 7, it is evident that, the electron mobility in the bottom channel is less compared to the top channel.Thus, the intruding thermal energy affects the Co-FET DC performance.However, the amount of trespassing heat and its impact is mainly controlled by the shallow trench isolation depth (d STI ) and inter-device spacing, and it is presented in the following subsections.

A. IMPACT ON DC PERFORMANCE OF Co-FET 1) THERMAL IMPACT ON DC PERFORMANCE OF Co-FET FOR DIFFERENT STI DEPTH
The impact of shallow trench isolation depth (d STI ) on thermal transfer between He-FET and Co-FET is investigated by varying it from 5 to 100 nm.The DC analysis is carried out on Co-FET by maintaining V DS = 0.05 V and varying V GS from 0 to 0.65 V, while He-FET is operated at V GS = 0.65 V and V DS = 0.65 V [1], [2].The drain current I D versus gate to source voltage V GS of Co-FET for different STI depths is shown in Fig. 8.As the depth of STI increase, the drain current increase due to increased gate control on the channel and reduced thermal interference.The on-current (I ON ) and off-current (I OFF ) in Co-FET are shown in Fig. 9 (a) and (b), respectively.It has been observed from the figure that, when the isolation depth is less, on-current is low due to more thermal flow into Co-FET.Due to the low thermal conductivity of silicon oxide, it restricts the thermal flow through it.Therefore, the higher the isolation depth, it becomes a long path via substrate for thermal energy to intrude into adjacent device.Therefore, the lattice temperature in Co-FET is reduced.The effective mobility of charge carriers, is inversely proportional to the lattice temperature, will increase with the reduced lattice temperature.During the off-state of Co-FET, when the shallow trench isolation depth is less, the potential of substrate parasitic channel is high due to the device-to-device interference and substantial heat flow into Co-FET, since the He-FET is in the on-state.This declines the potential barrier of the substrate parasitic channel, the planar gate on this substrate parasitic channel cannot have significant control and leads to increased off-current.When the STI depth is large, the lower potential of the substrate parasitic channel of Co-FET and reduced heat flow lowers the off-current.Hence, the on-current is improved and the off-current is reduced due to enhanced gate control.Whereas, the change in threshold voltage (V th ) of Co-FET is minuscule.Therefore, the threshold voltage is almost constant as shown in Fig. 9 (c).

2) THERMAL IMPACT ON DC PERFORMANCE OF Co-FET FOR DIFFERENT INTER-DEVICE SPACING (IDS)
Inter-device spacing is another important aspect that exhibits a substantial impact on thermal energy flow between the devices.It is the distance between two adjacent devices.When the two devices are close apart, the amount of thermal energy flowing from He-FET into Co-FET is significant.It degrades the DC performance of the Co-FET.The impact caused by He-FET on Co-FET is contemplated by varying IDS from 10 nm to 70 nm.The drain current (I D ) versus gate to source voltage (V GS ) of Co-FET for different inter-device spacing is shown in Fig. 10.As the width of inter-device spacing increase, the drain current of Co-FET increase.This is due to the increased restriction of thermal energy from intruding into Co-FET when IDS is more.The variation in on-current with respect to IDS is shown in Fig. 11 (a).It is observed from the figure that, when the IDS between two devices is less, the on-current (I ON ) of Co-FET is low due to the increased thermal effect.As the IDS between devices increases, I ON also increases.At the same time, the off-current of Co-FET I OFF is also increases with increase in the IDS as shown in Fig 11 (b).This is due to improved effective charge carrier mobility in the Co-FET.However, after an inter-device spacing of more than 50 nm between the devices, the on-current (I ON ) as shown in Fig. 11 (a) and the threshold voltage (V th ) as shown in Fig. 11 (c).The increase in inter-device spacing beyond 50 nm certainly reduces the thermal intruding from heat stacked nanosheet FET to cool stacked nanosheet FET.However, with the increase in interdevice spacing, the area of the substrate is going to increase, which gives a series resistance in the lateral direction, causing source degeneration, which in turn to more leakage through it and thus a slight reduction in on-current is observed beyond 50 nm inter-device spacing.

B. IMPACT ON ANALOG/RF PERFORMANCE OF Co-FET 1) THERMAL IMPACT ON ANALOG/RF PERFORMANCE OF Co-FET FOR DIFFERENT STI DEPTHS
The analog/RF performance analysis are carried out on Co-FET by maintaining V DS = 0.05 V while He-FET is operated at V GS = 0.65 V and V DS = 0.65 V using mixed-mode simulation in SDevice.The transconductance (g m ) is the ratio of the change in drain current to the change in gate voltage over an arbitrarily small interval on the I D -V GS curve.It is the device figure of merit, whose value if larger means, higher the device gain.It is given by Equation 1 [5].
The transit frequency is the frequency at which the transistor current gain becomes unity.It is expressed as given in Equation 2 [5].
where, C gg is the gate capacitance.
The maximum oscillation frequency is the frequency at which the unilateral power gain of the transistor becomes unity.It is given by Equation 3 [5].
where, R se is the series resistance, g ds is the output conductance and C gd is the gate to drain capacitance [5].Fig. 12 (a) and (b) depict the transconductance (g m ) and transit frequency (f T ) versus shallow trench isolation depth (d STI ), respectively.Improvement in the transconductance and transit frequency is observed with the increase in isolation depth from the figure, due to increase in on-current.The maximum oscillation frequency (f max ) for different STI depths is shown in Fig. 12 (c).It is observed that, f max is increased with the increase in STI depth.It is attributed to the reduction in gate capacitance due to reduced ascendancy of thermally generated carriers in the channel by the lattice temperature with increase in STI depth.The maximum oscillation frequency f max versus gate to source voltage V GS of Co-FET for different STI depths is shown in Fig. 13.Further, the thermal crosstalk ratio (TCR) is the total thermal energy interloped into Co-FET (Q in Co-FET ) to the total thermal energy emitted by the He-FET (Q emit He-FET ).Thus, the percentage of thermal crosstalk ratio is given by Equation 4 [26].
The thermal crosstalk between the two devices with respect to the shallow trench isolation depth is shown in Fig. 12 (d).It is obvious that, from the figure, thermal crosstalk reduces with the increase in the shallow trench isolation depth.

2) THERMAL IMPACT ON ANALOG/RF PERFORMANCE OF Co-FET FOR DIFFERENT INTER-DEVICE SPACING (IDS)
The transconductance (g m ) versus inter-device spacing is shown in Fig. 14 (a).The transit frequency (f T ) and maximum  oscillation frequency (f max ) versus inter-device spacing is shown in Fig. 14 (b) and (c), respectively.The thermal energy intruding from He-FET into Co-FET reduces with increase in inter-device spacing.Hence, the lattice temperature reduction in Co-FET enhances the electron mobility and hence improved transconductance, transit frequency and maximum oscillation frequencies were achieved.However, after a 50 nm IDS, further increase in it leads to the diminishing of g m and f T .Whereas the maximum oscillation frequency is increased till an IDS of 30 nm, and then after it deteriorates.This is because when the inter-device spacing is increased, the source-substrate parasitic resistance increases.When higher inter-device spacing exists, it forms series resistance along the substrate in a longitudinal direction.Compared to f T , f max is less sensitive to source-substrate parasitic resistance as the f T appears both in numerator and denominator of maximum oscillation frequency equation.The maximum oscillation frequency f max versus gate to source voltage V GS of Co-FET for different inter-device spacings is shown in Fig. 15.
The thermal crosstalk between the two devices with respect to the inter-device spacing is shown in Fig. 14 (d).As the IDS between the He-FET and Co-FET increases, the thermal effect from He-FET is reduced on Co-FET.Nevertheless, after an inter-device spacing of 50 nm, the thermal crosstalk saturates.

IV. OPTIMIZED INTER-DEVICE SPACING AND SHALLOW TRENCH ISOLATION DEPTH
There is a trade-off between the thermal crosstalk and interdevice spacing and shallow trench isolation depth between heat FET and cool FET.However, the optimization of IDS and STI depth is considered, such that, at which maximum performance improvement in Co-FET with minimal total area as criteria.An IDS of 30 nm is selected as the optimum value because it exhibits high transconductance, maximum oscillation frequency, and low off-current.The shallow trench isolation depth is considered as 50 nm for its higher maximum oscillation frequency, high on-current, and low off-current.With the optimized IDS and STI depth, an on-current I ON of 21.45 µA, a transit frequency f T of 131.5 GHz, and a maximum oscillation frequency f max of 435 GHz are obtained for Co-FET.

V. CONCLUSION
The self-heating induced thermal effect between stacked nanosheet field effect transistors sharing a common substrate is investigated in this work.A heat FET shows a severe impact on neighboring cool FET.Thermal impact on DC and analog/RF performance of cool FET is deliberated by varying the inter-device spacing and shallow trench isolation depth between the two stacked nanosheet field effect transistors.It is observed that, when deeper shallow trench isolation and wide inter-device spacing are considered, the thermal energy intruding into Co-FET from He-FET is less.This is due to the long path for thermal flow.Further, the optimization of STI depth and IDS was done for improved performance of the device.A higher on-current of 21.45 µA, cut-off, and maximum oscillation frequencies of 131.5 GHz and 435 GHz respectively, are achieved by the optimization of shallow trench isolation depth and inter-device spacing.It gives an improvement of ≈ 5.4% in on-current and ≈ 64% of f max compared to minimum values concerning STI depth and ≈ 2.4% in on-current and ≈ 60% of f max compared to minimum values concerning IDS are achieved.This work gives guidelines to mitigate the device-to-device thermal interference due to self-heating on stacked nanosheet FET performance in applications where multiple devices are on the same substrate and operate at different voltages.The applications include microprocessors and digital logic circuits, radio frequency amplifiers, low noise amplifiers, etc.

FIGURE 1 .
FIGURE 1. SNSHFET schematic at different phases of the virtual fabrication flow.

FIGURE 3 .
FIGURE 3. Methodology followed in this work.
FIGURE 5. (a) The lattice temperature profile and (b) its cross-section showing the thermal energy transfer from He-FET to Co-FET.

FIGURE 6 .
FIGURE 6. Electron mobility profile on the cross section along channel (left: He-FET; right: Co-FET).

FIGURE 7 .
FIGURE 7. Electron mobility along the centered cut-line of different channels in Co-FET.

FIGURE 8 .
FIGURE 8.I D versus V GS of Co-FET for different STI depths.

FIGURE 9 .
FIGURE 9. (a) On-current I ON (b) off-current I OFF (c) threshold voltage V th of Co-FET versus shallow trench isolation depth.

FIGURE 10 .
FIGURE 10.I D versus V GS of Co-FET for different inter-device spacing.

FIGURE 11 .
FIGURE 11.(a) On-current I ON (b) off-current I OFF (c) threshold voltage V th of Co-FET versus inter-device spacing.

FIGURE 12 .
FIGURE 12. (a) Transconductance g m (b) transit frequency f T (c) maximum oscillation frequency f max of Co-FET (d) thermal crosstalk ratio versus shallow trench isolation depth.

FIGURE 13 .
FIGURE 13.Maximum oscillation frequency f max versus gate to source voltage V GS of Co-FET for different STI depths.

FIGURE 14 .
FIGURE 14.(a) Transconductance g m (b) transit frequency f T (c) maximum oscillation frequency f max of Co-FET (d) thermal crosstalk ratio versus inter-device spacing.

FIGURE 15 .
FIGURE 15.Maximum oscillation frequency f max versus gate to source voltage V GS of Co-FET for different inter-device spacing.

TABLE 1 .
Device parameters considered in this work.