Investigating Mesa Structure Impact on C-V Measurements

Capacitance-voltage (C-V) measurements play a crucial role in evaluating semiconductor device performance by revealing vital parameters such as doping levels and charge carrier behavior. This study specifically investigates the impact of mesa structures on C-V measurements in 4H-SiC PiN vertical diodes. Our analysis uncovers distinct capacitance values per unit area among diodes with varying diameters within the same diode family. These findings underscore the limitations of conventional capacitance equations formulated for planar devices when extended to mesa-structured devices. To separate the capacitance portion dependent solely on the PN junction’s area from the overall depletion capacitance, which is influenced by the device’s geometry, we applied a methodology involving multiple C-V measurements across diodes with differing diameters and validated the experimental outcomes through rigorous calculations. This enables the utilization of standard capacitance equations. Neglecting the impact of device geometry has the potential to introduce significant inaccuracies in critical device parameters. The proposed methodology addresses these limitations, offering valuable insights to enhance the accuracy of extracted quantities from C-V measurements. Furthermore, it provides guidance for interpreting experimental data obtained from devices incorporating mesa structures.


I. INTRODUCTION
Capacitance-Voltage (C-V) measurements play a crucial role in semiconductor device characterization, offering insights into key performance parameters such as interface quality, depletion region properties, charge carrier behavior, doping levels, and built-in potential [1].The diverse techniques within C-V measurements, ranging from evaluating doping profiles [2] and band-offsets [3] to analyzing steady and transient capacitance for deep-level impurity characterization [4], [5], share a common underlying necessity: they require the assessment of capacitance arising from charge within the space charge region at specific voltage levels.
Furthermore, it is crucial to acknowledge that the capacitance can be affected by the existence of a mesa structure within the device, which is the central focus of this study.
The associate editor coordinating the review of this manuscript and approving it for publication was Marcelo Antonio Pavanello .
More specifically, we delve into the effects of the mesa structure on the distribution of charges within the device and how this, in turn, influences the resulting capacitance values.Consequently, this influence directly affects the precision of estimates derived from this capacitance for various quantities.For instance, the built-in voltage and the doping level, as well as quantities indirectly dependent on them, such as estimating defect concentration through DLTS measurements [6] or transient CV measurements, which necessitate knowledge of the substrate doping, or in assessing the distribution of the reduced lifetime region in irradiated diodes [7].
To enhance the precision of these evaluations, we have introduced a method involving multiple C-V measurements across diodes with varying diameters and validated the experimental procedure results with calculations.

II. DEVICE UNDER STUDY
The studied devices are vertical mesa PiN diodes of cylindrical shape with anode diameters varying from 200 to 700 µm fabricated on homo-epitaxial 4H-SiC wafer housed in 2.5 mm × 2.5 mm square chip [8].Half the cross-section of the diode, as determined through analysis using Secondary Electron Microscopy (SEM) of a cross-sectioned specimen, is sketched in Fig. 1.The doping values and types of the homo-epitaxial and bulk layers were obtained from the SiC wafer data sheet.
We performed C-V measurements on diodes of different diameters, in the bias range from −20 V to +2.4 V, using an HP4284A LCR meter operating at a frequency of 1 MHz, with an oscillator level of 200 mV, and with a residual stray capacitance estimated to be < 0.1 pF.All measurements were conducted at 20±2 • C.
C-V measurements were conducted to assess the doping profile of the n-type epilayer and the built-in potential values.

A. C-V CURVES
As known, the depletion-layer capacitance of a PN junction with uniform doping profiles, can be calculated using the following formula [9]: here ε SiC is the electrical permittivity of the semiconductor, q the electron charge, ϕ bi the built-in potential, X D the depletion region width, A the junction area, C A the depletion-layer capacitance per unit area, V the reverse bias voltage.
If the doping is uniform, the slope of 1/C 2 versus the reverse bias voltage should be a straight line whose slope is relate to the doping, whereas the intercept of the straight line with the voltage axis should give the ϕ bi .
For one-sided abrupt junction, that is a strongly asymmetric junction, i.e., N A ≫ N D as for diodes in this study, the doping of the n-side of the junction can be calculated from (1) as: Equation ( 1) employs the parallel plate capacitor approximation, treating the depletion region as a capacitor formed between P-type and N-type semiconductor regions.This model assumes a uniform depletion region with a constant electric field across the entire width [6].However, the diodes under examination have a mesa structure (refer to Fig. 1).
Our main objective was to assess the suitability of equation ( 1) in interpreting C-V measurements for mesastructured diodes under study.
We initiated the analysis by examining the capacitance values obtained at V = 0 V in diodes of different diameters, C(V = 0V).
If (1) were valid, the ratio of C(V = 0 V) to A (with A representing the junction area calculated as π r 2 , and r the radius shown in Fig. 1), would have remained constant, since C(V = 0 V)/A coincided with C A in (1).
However, the data presented in Table 1 clearly demonstrate that this is not the case.To investigate the potential impact of the device geometry on the C-V characteristics, we graphed C(V)/A ratio against 1/r, as depicted in Fig. 2 for the two cases of 0 V and −3 V. Remarkably, the experimental data points align very well with a parabolic function described by the equation: The identical correlation holds for negative applied voltages.The parameters α, β and γ exhibit voltage dependency, as demonstrated in table 2; derived through interpolation of experimental results using (3) at various voltage levels.
In (3), the term α corresponds to the depletion-layer capacitance component that is solely dependent the PN-junction area, i.e.C A (V) in (1), while the terms β and γ are dependent on the device's geometry.At V = 0 V, the obtained C A = 1.95 nF/cm 2 .
To establish a link between the experimental law and the diode's geometry, we calculated the diode capacitance by accounting for a generic mesa structure depicted in Fig. 3,  which also includes the parameters used in the computation.The calculation steps are detailed in the appendix.
Below, the resulting equation is provided for the case of X n > h as for diodes of this study: where X ′ D is the derivative of the depletion region width, X D , with respect to voltage (the expressions of X D and X ′ D are reported in the appendix), while l and h are parameters associated with the mesa's geometry, as depicted in Fig. 3.
C A (V), which coincides with α(V) in can therefore be calculated as:

B. DOPING EXTRACTION
The doping concentration N D (V) can be determined by (2) based on the values of C A (V).However, to obtain C A (V) from ( 5) would require extract β and γ at all voltages, that would make the process challenging to implement.One viable approach could be to use for both β and γ the values calculated at 0 V, neglecting their dependency on voltage.
Using measured data in table 2, we calculated the relative error incurred when calculating C A (V) with ( 5) accounting for the dependency of β and γ on voltage compared to assuming β and γ remain constant at V = 0 V, finding a maximum relative error < 1%.
Hence, we compute the value of C A (V) based on (5), while assuming the values of β and γ at 0 V; that C A (V) is finally used to calculate the doping N D (V) with (2).Fig. 4 illustrates the doping concentration N D (V) for diodes of largest and smallest diameter calculated with the described procedure (solid lines) and the standard approach (dashed lines).
As the forward bias approaches the ϕ bi , the significance of the diffusion capacitance renders the employed capacitance model and the corresponding N D invalid.
With the proposed approach, the calculated doping concentration in the epilayer for both diode diameters closely approximates N D ∼1.5•10 14 cm −3 and remains uniform for negative applied biased, that is, increasingly deeper into the epitaxial layer (solid lines).However, disregarding the contribution to depletion-layer capacitance associated with the diode's geometry, such as in the case of measuring a single-diameter diode, would result in the doping profiles shown by the dashed lines in Fig. 4. Notably, doping appears to be non-uniform within the epitaxial layer, also exhibiting different values for the two diodes.
The largest error in doping estimation is observed in the case of the smaller diameter diode, where factors like β r and γ r 2 in (5) exert a more significant influence, leading to an ∼700% error in doping estimation at 0 V.This error diminishes in the larger diameter diode scenario but remains at approximately 33% at 0 V.

C. BUILT-IN VOLTAGE EXTRACTION
Similarly, we computed the built-in potential by plotting 1/C 2 versus the reverse bias voltage utilizing both the measured capacitance and the C A (V) calculated as in ( 5): the extrapolation of 1/C 2 to 0 should provide the built-in potential.Fig. 5 illustrates the plotted curves for a diode measuring 700 µm in diameter.Disregarding the influences tied to the diode's geometry results in a relative error of ∼22% in estimating the built-in potential.

IV. CONCLUSION
During our investigation into reverse-bias capacitance measurements in SiC vertical PiN diodes of varying diameters and featuring mesa structures, we observed the limitations of employing the traditional voltage-dependent capacitance equation designed for planar device in doping extraction.Notably, distinct values of capacitance per unit area (C/A) were obtained in diodes of different diameters within the same sample.
To explore the potential influence of device geometry on the measured capacitance (C), we plotted the C/A ratio against the reciprocal of the PN junction radius (1/r).This analysis revealed a quadratic relationship between these parameters, enabling the determination of the depletion capacitance component solely associated with the PN junction area.This approach allows for the extraction of doping and built-in potential parameters using standard expressions calculated for a planar device.
To interpret the observed experimental trend, we derived expressions for capacitance as functions of geometric parameters.These calculations provide a valuable tool for interpreting experimental data obtained from devices featuring mesa structures.
Furthermore, we demonstrated that neglecting the impact of device geometry can introduce significant errors in doping estimation and the evaluation of the built-in potential.This oversight potentially compromises the accuracy of parameters dependent on these quantities.To address these limitations, we propose a methodology to mitigate such errors.

APPENDIX DEPLETION-LAYER CAPACITANCE VS VOLTAGE CALCULATION
The methodology employed to derive the mathematical expression for interpreting experimental capacitance values is detailed in the following.Fig. 3 illustrates half of the cross-section of the cylindrical diodes along the longitudinal axis of symmetry, displaying the PN junction and the mesa structure.N A and N D are the p-and n-type doping, r the PN junction radius, X D the depletion region width, d denotes the portion of the depletion region extending both laterally and vertically beneath the mesa etching surface.
The depletion region width of a planar PN junction is a function of the applied reverse-bias voltage, V, and can be calculated as [9] and [10]: where ϕ bi is the built-in voltage, q the elementary electron charge, and ε SiC the dielectric constant of semiconductor, the Silicon Carbide for the studied devices.
In the case of an asymmetrical junction, as in the studied diodes, the depletion region primarily extends into the low-doped side of the junction, namely the n-side, X n (V ), of expression: Under the approximation of fully depleted region [9], [10], the total charge of depletion region in the n-side of the diode can be calculated as Q TOT = q•N D •V TOT , where V TOT is the total volume depleted of charge.
V TOT can be calculated as the sum of different contributions, as sketched in Fig. 6.We considered two main cases:

FIGURE 1 .
FIGURE 1. Cylindrical diodes' half cross-section, with a dash-dot line denoting the central axis of symmetry.Mesa etchings along the diode periphery and the anode are identified through SEM observations.

TABLE 2 .
Fitting parameters obtained from the interpolation of the measured capacitances at different voltages with (3).

FIGURE 3 .
FIGURE 3. Cross-sectional view of the diode region with the PN junction, illustrating the extension of the n-side depletion region (d = X n -h) both vertically and laterally beyond the mesa etch surface for depletion capacitance computation.

FIGURE 4 .
FIGURE 4. Doping concentration within the epilayer, N D (V), versus voltage, computed directly from measured capacitance C(V) (standard approach), or derived from C A (V) using (2) (this work).

FIGURE 5 .
FIGURE 5. Built-in potential, ϕ bi , computed directly from measured capacitance, 1/C 2 (red circles, standard approach), or derived from 1/(A•C A ) 2 using (2) (black squares, this work).C represents the measured capacitance, whereas C A represents the depletion-layer capacitance component solely dependent on the PN-junction area, calculated using(5).

TABLE 1 .
Measured capacitance-to-area-ratio for diodes of various diameters calculated at 0 V.