Effective DC Link Utilization of Multilevel Dual Inverter With Single Source in the Maximal Distention Mode

This paper presents an effective voltage control scheme for an open-end winding (OEW) inverter topology with a single DC supply. The proposed configuration consists of a 3-level flying capacitor inverter at one end, and a floating capacitor fed 2-level inverter at the other end. This dual inverter configuration is operated in the maximal distention mode. i.e., the voltage ratio of the inverters is maintained at 4:1 to get the largest number of effective pole voltage levels. Maximal distention mode has the advantage of good power quality and low voltage stress. A major drawback of open-end winding inverter topology with a single source in maximal distention mode is the inability to charge balance the floating capacitor in the full space vector region, which limits the battery utilization as well as the magnitude of output voltage. In this work, a modified modulation technique is proposed to maintain the floating capacitor at the desired level, attaining a 13.1% increase in the output voltage magnitude, resulting in an improvement in the battery utilization in the same proportion, yielding a smaller and less expensive system. Simulation and experimental results corroborate the proposed modulation technique and voltage control scheme on a 3HP, 3-phase, 415V, 1440 rpm open-end winding induction motor.


I. INTRODUCTION
Multilevel inverters (MLIs) are quite popular as it has many advantages like low Total Harmonic Distortion (THD) in current and voltage and reduced switch voltage stress compared to conventional 2-level inverters.Neutral Point Clamped (NPC), Flying Capacitor, Cascade H-bridge, etc. are some of the widely used MLI topologies.As the number of voltage levels in an MLI increases, the NPC MLI and Flying Capacitor MLI (FCMLI) topologies require additional components like clamping diodes and flying capacitors respectively, whereas the cascade H-bridge MLIs require a greater number of isolated sources [1], [2], [3].Besides these topologies, there are multilevel inverter schemes such as dual inverter open-end winding (OEW) schemes, and modular The associate editor coordinating the review of this manuscript and approving it for publication was Inam Nutkani .MLI as derived from the conventional topologies [4].The main advantage of the dual inverter fed open-end winding configuration is that it has reduced DC link requirement and low voltage rating for the switching devices.Based on the number of sources used, open-end winding MLIs can be classified into two: single source topology and multi-source topology.Single source topology is of two types: (i) single source feeding both the inverters after eliminating common mode voltage [5], [6] (ii) single source feeding one inverter and the other inverter powered by floating capacitor [7], [8], [9], [10].The main disadvantage of the second scheme is its ineffective utilization of the linear modulation range due to floating capacitor charge balance issues.In [11], OEWIM supplied by two flying capacitor multilevel inverters are discussed.However, the configuration requires two voltage sources.Several OEW topologies are realized with a reduced number of switches in [12].However, all these configurations use two voltage sources.In [13], an open-end dual source multilevel inverter topology eliminates all the 6n ± 1 (n is an odd positive integer) harmonics from the phase voltages in the entire modulation range.Again, this configuration requires two voltage sources.In [14], a 3-level and 2-level inverter are used to feed an OEWIM.With this scheme, a higher waveform quality and an enhancement in linear modulation range are achieved.However, this scheme requires three isolated voltage sources.
A 5-level inverter scheme using a single DC link with a reduced number of floating capacitors and switches for OEWIM drives is proposed in [9].At a source voltage ratio of 4:1 (see Fig. 1), this topology can generate the maximum number of effective pole voltage levels giving a 6-level space vector diagram (maximal distention mode) [15], [16].However, due to floating capacitor charge balance issues, the outermost layer of space vectors (Fig. 2) could not be utilized (i.e., space vector locations up to a space vector level of N = 5 could only be used).This restricted the linear modulation range to 0.866V dc , whereas it could go theoretically up to 1.0825V dc as shown in Fig. 3.This reduces the utilization of DC link voltage.In [17], an MLI scheme with cascade H-Bridges is presented.This scheme achieves an extension of the linear modulation range of 0.955V dc but uses 30 switches and 6 capacitors.In [18], a 5-level cascade H-Bridge topology with a single source has been proposed.This uses only 21 switches as compared to that in [17], but extension achieved is only upto 0.945V dc .In [19], an OEWIM scheme capable of extending the linear modulation range to 0.955V dc is presented.However, this configuration requires a large number of switches (24 nos.) to get the extended linear modulation range.In [20], two numbers of 3-level NPC inverters are used.The linear modulation range is extended to 0.955V dc .But the configuration is not operated in maximal distention mode and the configuration requires 24 switches and 4 capacitors.
From the above discussion, it is clear that the existing OEW topologies with a single source in the maximal distention mode do not properly utilize the entire linear modulation range due to less number of redundant states for charge balancing of capacitor.In this paper, a voltage control scheme for a 6-level dual inverter topology for OEW configuration with a single source and reduced number of switches (18nos.) is proposed.This voltage control scheme helps to increase the magnitude of output voltage in the linear modulation range, resulting in increased DC link utilization.By incorporating suitable changes in the modulation technique, the space vectors in the outermost layer are effectively utilized yielding a linear modulation range up to 0.98V dc .
This paper is organized as follows: Section II discusses the cascade 3-Level-2-Level dual inverter (DI) topology.The operating principle, capacitor voltage control, and modulation technique are explained in section III.Sections IV and V discuss the simulation and hardware results respectively.
Finally, section VI summarizes the key findings and benefits of this work.

II. CASCADE 3-LEVEL-2-LEVEL DI TOPOLOGY
The circuit diagram of the 3-level-2-level cascade DI topology is shown in Fig. 1.The induction motor is fed by a 3-level FCMLI on one end and the other end of the motor is connected to a conventional 2-level inverter with a floating capacitor.A single DC source, V dc is utilized which is connected to the 3-level FCMLI, and this in turn charge balances the floating capacitor of the 2-level inverter at V dc /4.
Here • Pole voltage of the 3-level inverter is given by where, V A 1X , V B 1X and V C 1X are the pole voltages of inverter 1 (INV1) and H a , H b , and H c are switching functions that can take values 0, 1 or 2.
• Pole voltage of the 2-level inverter is given by where, V A 2X ′ , V B 2X ′ , and V C 2X ′ are the pole voltages of inverter 2 (INV2) and S a , S b , and S c are switching functions that can take values 0 or 1.The resultant voltage space vector or equivalently, the reference voltage V ref for the resultant space vector [13] is given by The topology is capable of generating a 6-level space vector diagram, based on this equation, as shown in Fig. 2 for a voltage ratio of 4:1.More details are given in the next section.The outer layer is also considered in this work unlike that in [9] where charge balance issues in the floating capacitor limit the magnitude of V ref to 0.866V dc only as already mentioned in the introduction.

III. PRINCIPLE OF OPERATION A. SPACE VECTOR STRUCTURE
The 6-level space vector structure (SVS) in Fig. 2 represents all the possible pole voltage combinations obtained by superimposing 3-level inverter space vectors and 2-level inverter space vectors [9].In the 6-level space vector structure, there are a total of 216 states occupying 91 space vector locations.Space vector locations indicated by star notations are states without redundancies.There are adequate numbers of redundant states in the inner layers as denoted by circle or triangle notations.Space vector locations indicated

B. CAPACITOR VOLTAGE BALANCING
The voltage of the flying capacitors C a , C b , and C c are maintained at V dc /2 and their charging and discharging depend on the respective phase current directions.Voltage balancing of the flying capacitors can be done only during level 1 of the INV1 i.e., when the alternate switches H a1 and H a3 or H a2 and H a4 of the INV1 are ON.Charge balancing of the floating capacitor C F depends on the direction of all the three-phase currents i a , i b , and i c .Table 2 gives the charging and discharging states according to the direction of current for the floating capacitor C F .Here 'C' stands for charging, 'D' for discharging, and 'N' for neutral status.The currents i a , i b , and i c are taken as positive when they flow from INV1 to INV2 through the respective phase windings.
Consider a point 'P' (indicated by a pentagon notation) in Fig. 2. The nearest 3 vectors concerning point 'P' are 227, 224, and 225.However, it may be noted that by switching these vectors, the balancing of the floating capacitor C F is not possible due to the absence of a sufficient number of redundant switching states.To balance To understand the charging and discharging of flying capacitor 'C a ', consider INV1 in Fig. 4, here the alternate switches of phase-A are ON, say H a 1 = 1 and H a 2 = 0.For i a ≥ 0, H a1 = 1; H a 2 = 0, charges C a and H a1 = 0; Similar is the case with other phases.

C. MODULATION TECHNIQUE
In this paper, the modulation index is defined as where V ref is the length of the reference vector.
For the modulation, space vector pulse width modulation (SVPWM) is implemented using the hexagonal decomposition method, i.e., each hexagon is mapped to a 2-level  hexagon [22].For higher level multi-level inverters where the density of space vectors in the space vector diagram is very large, nearest vector switching methods [23], [24] may also be attempted which obviates duty cycle computation burden at the expense of slightly higher harmonic distortion.However, since the number of levels is not large (6-levels in this paper), the hexagonal-decomposition based duty cycle computation is adopted and it is a very simple and straightforward scheme.
In the outer layer i.e., V ref > 0.866V dc , the 6-level hexagon (outermost hexagon) is divided into six 4-level hexagons, then each 4-level hexagon is further divided into six 3-level hexagons.These 3-level hexagons are mapped to the vectors of the basic 2-level hexagon as shown in Fig. 6.The centre of the 6-level hexagon is indicated as 'O'.Points A, B, C, D, E, and F are the centres of the 4-level hexagons.Points G, H, I, J, K, and L are the centres of the 3-level hexagons.
Consider any arbitrary point 'P 1 ' in the outer layer (see Fig. 6).Point 'P 1 ' lies in the 3-level hexagon with centre 'G', Here V α0 and V β0 are the components of vector GP 1 in α − β frame.The switching time of the active vectors is denoted by T 1 and T 2 and that of the null vector is T 0 .T s is the switching period and n is the sector number which can vary from 1 to 6.
Selection of switching vectors for the inner layer i.e., V ref ≤ 0.866V dc is depicted in Fig. 7.Here the 5-level hexagon with centre 'O' is considered and divided into six 3-level hexagons with centres at A, B, C, D, E, and F. Next each 3-level hexagon is further divided into six 2-level hexagons with centres G, H, I, J, K, and L. For an arbitrary point P 2 in the inner layer, the nearest vectors G, R, and Z are switched and the corresponding switching times are calculated using ( 5)-( 8) by replacing V dc 2 with V dc 4 .

IV. SIMULATION RESULTS
The simulation was done using MATLAB and PLECS software.All the results are shown at no load operation as it gives the worst case THD performance.Fig. 8 shows the simulation results for 15Hz, 30Hz, 45Hz, and 48.45Hz operation.It can be noted that as frequency decreases, the number of levels gets reduced.At 48.45Hz, 45Hz, and 30Hz, the pole voltage of INV1 has 3 levels, while at 15 Hz, it has only 2 levels.As shown in Fig. 8 pole voltage of INV2 has a 2-level operation at all frequencies.The performance of capacitors during charging is shown in Fig. 9.No pre-charging is used and therefore initially the capacitor voltages are zero and rise to the desired values from the initial uncharged voltage.The flying capacitor C a and floating capacitor C F are maintained at V dc /2 and V dc /4 respectively, irrespective of the magnitude of output voltage.However, for the outer space vector region, charge balancing of floating capacitor C F is quite difficult as the redundant state switching time is less.Therefore, it takes a longer time (about 3s) to reach the steady state value (refer to Fig. 9d).It may also be noted that the time to attain a steady state value for flying capacitor voltage V C a is quite small and is not affected by the change in magnitude of V ref .
Fig. 10 shows the simulated plot of the harmonic spectrum of the phase current (magnitude in % of fundamental) and the THD i Vs frequency graph is shown in Fig. 10b.It can be seen that the modulation strategy gives low THD.Theoretically, the magnitude of V ref could be varied up to 1.0825V dc (refer Table 3) i.e., an increase of 25% in the linear range.Due to charge balance issues, the magnitude of V ref could be varied only up to 1.05V dc (21.25% increase in the linear region) in the simulation study with the switching frequency of 5kHz.A lower value is obtained for V ref in the hardware experiment compared to the simulation due to various non-idealities and power losses.Table 3 gives a comparison of attainable modulation index, maximum V ref , and DC link utilization attained with the proposed scheme with that in [9] of the 3-level-2-level DI in the maximal distention mode.It can be noted that the proposed method gives much better performance.

V. EXPERIMENTAL RESULTS
Open loop v/f control is performed on a 3-phase 2.2kW, 415V, 50Hz 1440 rpm OEW induction motor to verify the operation of the proposed modulation technique.The experimental setup is shown in Fig. 11.The proposed scheme is implemented using DSP TMS320F28335 and FPGA spartan 6.The block diagram of the implementation scheme is shown in Fig. 12.The FPGA was used to provide deadtime for all the switches and also for realizing the space vector PWM and capacitor charge balance through suitable operation of power switches from the PWM data as available on the PWM ports of the DSP and the capacitor charge status (Please see Fig. 12).The DSP processor alone cannot do the operations as the DSP operates sequentially whereas the PWM operation and charge balance of the FC multilevel inverter demands    frequency is 5kHz and a dead time of 2 µs is also provided.The design of capacitors is done according to the equation C = (I p T s / V ).Here, I p is the peak phase current, T s is the sampling period and V is the peak ripple voltage of the capacitor.The capacitance value is proportional to the magnitude of the current.So as power rating increases current increases and hence required capacitance value also increases.The pole voltages are measured using high voltage differential voltage probes (Tektronics P5200A).The phase  the voltage of floating capacitor V C F is more, due to the lack of sufficient redundant states in the outer layer.Fig. 16a shows the measured harmonic spectrum of phase current   at 45 Hz.In hardware the measured THD is 7.3 %.Fig. 16b depicts the THD Vs frequency plot.It can be noted that at higher frequencies THD is lower compared to that at lower frequencies.The THD figures are higher in the hardware results due to various non-idealities such as deadtime, switching delays, core saturation etc.
The waveforms during the starting of the motor are shown in Fig. 18.It can be seen that the floating capacitor and flying capacitor voltages rise to the desired value without any precharging requirement.The acceleration characteristics are illustrated in Fig. 19.It can be noted that smooth acceleration is obtained with the proposed scheme.In both steady and transient states, the capacitor voltages are well balanced.As given in Table 3, the modified modulation technique achieves 90.5% DC link utilization.The modulation index   could be varied up to 0.905, whereas in [9], it was limited to 0.8.Also, the maximum possible V ref is extended to 0.98V dc , which was earlier limited to 0.866V dc .Thus, the magnitude of output voltage could be increased by 13.1% in the linear region.This improvement could be achieved without any topological change demanding more switches as that in [19], demonstrating the usefulness of the proposed scheme.Table 5 essentially gives a comparison with other 5-level inverters which attempts linear modulation range extension.The proposed scheme achieves the largest extension of linear modulation with lowest number of devices.

VI. CONCLUSION
The space vector modulation and charge balancing of capacitors of a dual inverter with a minimum number of switches, fed from a single DC source have been analyzed and the results are presented.With the proposed modulation technique, the partitioning of the space vector diagram has been modified to achieve charge balance for the floating capacitors thus utilizing the entire space vector region for the modulation unlike that has been reported hitherto in literature.
The proposed modulation strategy accounts for a 25% increase in the magnitude of output voltage in the linear modulation range theoretically.However, this demands very large capacitance values and a high switching frequency.With a realistic switching frequency of 5kHz for medium voltage drives and capacitance values of 2200µF and 4400µF respectively for flying and floating capacitors, the output voltage magnitude and battery utilization could be increased by 13.1%, which is a significant achievement as it helps to achieve a more compact and cost-effective system.The proposed scheme can be effectively used in applications where the load can be open-ended such as high-power motor drives in ship propulsion & e-mobility, grid interactive inverters, and STATCOMS with open end winding transformers.

FIGURE 1 .
FIGURE 1. Multilevel inverter configuration for the proposed control scheme.

FIGURE 4 .
FIGURE 4. Charging of capacitor C a and discharging of C F (State 15).

FIGURE 5 .
FIGURE 5. Charging of both Capacitor C b and C F (state 222).

FIGURE 12 .
FIGURE 12. Functional block diagram of the control scheme.

FIGURE 15 .
FIGURE 15.DC link and Flying capacitor voltages, Traces : (1) DC link voltage V dc (2) Phase-A flying capacitor voltage V C a (3) Phase-B flying capacitor voltage V C b (4) Phase-C flying capacitor voltage V C c , at 45 Hz operation.

FIGURE 17 .
FIGURE 17. Disabling the charge control scheme of flying capacitor V C a of inverter 1 at time 'A' and re-establishing the charge control at 'B'; and that of floating capacitor V C F at time 'C' and reestablishing the charge control at 'D', at 45 Hz operation and x-axis:1s/div.
H a 1 , H a 2 , H a 3 , H a 4 are the switches of the phase-A of the flying capacitor inverter (INV1), and S a 1 , S a 2 are the switches of the phase-A of the 2-level inverter (INV2).H a 3 and H a 4 are complements of H a 2 and H a 1 respectively.Also, S a 1 is the complement of S a 2 .For the FCMLI, level 2 indicates that the top two switches (H a 1 , H a 2 ) are ON, level 1 means alternate switches (H a 1 and H a 3 or H a 2 and H a 4 ) are ON and level 0 means bottom two switches (H a 3 , H a 4 ) are ON.

TABLE 1 .
[21]ing of switching function with switching states.bycircleshaveboth charging as well as discharging states.Space vector locations denoted by triangles indicate neutral state locations i.e., the voltage level of the floating capacitor is unaffected[21].

TABLE 2 .
Status of capacitor C F , based on switching function of inverter 2 and phase current direction.

TABLE 5 .
Comparison of other 5-Level inverters with extension of linear modulation range.