Hybrid DC–DC Converter With Novel Clamp Circuit in Wide Range of High Output Voltage

In this paper, a hybrid converter with a novel clamp circuit is introduced. This hybrid converter integrates a phase-shifted full-bridge (PSFB) converter with a half-bridge (HB) LLC converter. On the primary side, the lagging leg of the PSFB converter is shared with the HB LLC converter. On the secondary side, the full-bridge rectifiers (FBR) of both converters are connected in series. Due to its series connection structure on the secondary side, this hybrid converter is suitable for high output voltage applications. The converter also includes the novel clamp circuit, which consists of two diodes and one capacitor connected to the center of the transformer. The proposed converter can overcome many drawbacks of conventional PSFB converter. Lastly, it offers improvements in efficiency, power density, and cost. To validate the viability of the proposed converter, a 3.3kW prototype was tested.


I. INTRODUCTION
Recently, in the electric vehicle (EV) field, the rated voltage of batteries has been increased to 800V to increase the charging speed of batteries in vehicles.Fast charging is important for EVs as it reduces the time required for charging an EV, making it much more convenient for users.Also, it can allow EVs to cover longer distance on a single charge.To increase charging speed, the charging power must be increased.In order to increase charging power under the same voltage condition, the charge current should be increase.However, a high charging current has challenges such as increased conduction loss and the need for thicker charging wires.On the other hand, a high charging voltage can increase charging speed without limiting the current [1].With this trend, interest in DC/DC converters with high rated output voltage is also increasing.
The associate editor coordinating the review of this manuscript and approving it for publication was Vitor Monteiro .
Meanwhile, at several kilowatts (1-7 kW), An LLC converter is a good candidate.However, the LLC converters face challenges in achieving optimal design due to a pulse-frequency modulation (PFM) control method.Above all, the LLC converter has significant challenges in operating across a wide range of output voltages with high output power [20], [21], [22].On the other hand, a phase-shifted fullbridge (PSFB) converter has many advantages such as simple control and wide range of voltage gain [2], [3].
In order to improve the disadvantages in the conventional PSFB converter, several studies of hybrid model integrating PSFB converter with half-bridge (HB) LLC converter have been studied [16], [17], [18].On the secondary side, the FBRs of both converters are connected in series.Due to its series connection structure on the secondary side, this hybrid converter is suitable for high output voltage applications.Moreover, ZVS can be easily achieved by sharing the lagging-leg of the PSFB converter with the HB LLC converter, resulting in a reduced circulating current.However, there are still drawbacks that need to be resolved.In [16], the converter has high voltage stress on their full-bridge rectifiers due to the absence of a clamping circuit.In [17] and [18], the CDD clamping circuit was proposed, as shown in Fig. 1(b).It effectively reduced voltage stress on these rectifiers.Nonetheless, the CDD clamp mechanism has its own challenge: significant ripple current flowing through the output capacitor.This occurs because there is a current path directly connected to the output capacitor without going through the output inductor.To cover this large ripple current, larger output capacitors are necessary, which consequently reduces power density.This result is very undesirable, because PSFB converters typically benefit from a low-pass filter.
The proposed converter integrates PSFB converter with HB LLC converter, featuring a novel clamp circuit applied to the PSFB converter.The novel clamp circuit consists of two diodes and one capacitor, and it is connected to the center-tap of the transformer on the secondary side.The proposed converter solves the problems of previous studies.The proposed converter has the following advantages: 1) No circulating current loss.
2) Low voltage stress of FBR diodes.
The comparisons of the proposed converter with previous researches are summarized in Table 1.
This paper is based on previous research [19].It includes a considerable amount of additional analysis.This analysis includes the following aspects.The study focused on a prototype with a broader range and higher output voltage (560 V ∼ 800 V), which was not addressed in [19].Through a more detailed analysis, the paper enhances technical understanding, and the paper includes design considerations important for improving the reliability and efficiency of the converter.Moreover, by providing a detailed loss analysis, the study explores ways to enhance the efficiency of the converter.
The structure of this paper is organized as follows: Section II introduces the operation principle of the proposed converter.Section III provides a steady-state analysis.Design considerations are explored in Section IV.Section V confirms the performance of the proposed converter.The paper concludes in Section VI.

II. OPERATION PRINCIPLE
Fig. 2 shows the circuit diagram of the proposed converter.On the primary side, the lagging-leg of the PSFB converter is integrated with the HB LLC converter, enabling ZVS for the lagging-leg through the HB LLC converter.The secondary side features two full-bridge rectifiers connected in series, making the converter suitable for fast chargers in DC/DC converters requiring high output voltage.The clamping circuit, composed of two diodes and a capacitor, is connected to the midpoint of the transformer on the secondary side.Fig. 3 shows the key waveforms.Each cycle, denoted as the switching period T S , is divided into two parts.In this paper, we solely focus on one of these parts due to its symmetrical operations.This part is divided into six stages, each corresponding to circuits illustrated in Fig. 4. To enhance clarity, several assumptions have been made: 1) The output capacitance C O_LLC of the LLC converter and the clamping capacitance C C are sufficiently large to sustain a constant-voltage (CV) source throughout T S .The magnetizing inductance L m1 of the PSFB converter is so large that its current remains zero.The primary current i pri1 in the PSFB converter is described as follows: where n T 1 is the turns ratio of the secondary side to the primary side for T 1 , V Lkg1 is the voltage across L lkg1 , and V S is the input voltage.
Mode 2 [t 1 -t 2 ]: Mode 2 begins when the leading-leg switch Q 1 is turned off.The junction capacitors of switches Q 1 and Q 2 are charged or discharged by i pri1 , which equals the primary-reflected output current.During this mode, L O supplies the ZVS energy in the same manner of the traditional PSFB converter, ensuring that i pri1 remains constant.
Mode 3 [t 2 -t 3 ]: In this mode, commutation shifts from the FBR diodes D 1 and D 3 to the clamping diode D C2 .Since switches Q 2 and Q 3 , as well as diodes D 1 , D 3 , and D C2 , are turned on, V C is reflected to the primary side, making V Lkg1 equal to -V C /n T 1 .Due to the negative V Lkg1 , i pri1 decreases.Importantly, there is no circulating current in this stage as power continues to be delivered to the secondary side with positive voltage across L m1 .This demonstrates that the novel clamp circuit eliminates circulating current on the primary side, subsequently reducing conduction losses.Additionally, when V Lkg1 remains below 0.5V S , which is less than half of the value seen in traditional PSFB converters, the slope of the decreasing i pri1 is moderate.This ensures that the rate of change di D /dt of the current in the FBR is also moderate, leading to a reduction in the reverse-recovery current of the FBR [13], [14], [15].During this mode, commutation takes place from D 1 and D 3 to D C2 .The duration of this mode can be articulated as follows: Mode 4 [t 3 -t 4 ]: Mode 4 initiates when D 1 and D 3 are turned off.During this mode, the reverse voltages of D 1 and D 3 rise to V C , which is notably smaller than what is observed in traditional PSFB converters.As a result, the switching losses of D 1 and D 3 are significantly reduced due to the minimized reverse voltage and the decreased reverserecovery current.Furthermore, during this freewheeling period, V rect1 is clamped to V C .This results in a much lower voltage being applied to the L O , thereby reducing the size of the L O .
Mode 5 [t 4 -t 5 ]: This mode initiates when the lagging-leg switch Q 3 is turned off.Considering the large inductance of L m1 , the magnetizing current i Lm1 of T 1 is assumed to be zero, resulting in i pri1 also being zero.As a result, the PSFB converter does not contribute to the ZVS operation for the lagging-leg switch.Instead, the ZVS operation is achieved by the HB LLC converter.Moreover, the turn-off losses in Q 3 are significantly reduced due to the decreased turn-off current, which is a result of the elimination of the circulating current.

III. STEADY STATE ANALYSIS
For a simple illustration, it is assumed that the duration of the dead-time is narrow enough to be ignored.

A. VOLTAGE GAIN
The output voltage V O can be represented as the sum of the output voltage V O_PSFB from the PSFB converter and the output voltage V O_LLC from the HB LLC converter, as follows: V O_PSFB is controlled using phase-shifted pulse-width modulation (PWM) at a constant switching frequency f S .From Fig. 3 and Fig. 4, V O_PSFB can be obtained as the averaged voltage of V rect1 as follows: where D eff is the effective duty cycle.
As explained in detail in the previous study [11], the voltage gain M PSFB can be expressed from equation (5) as follows: where Thus, the output voltage V O_PSFB can be expressed as follows: where M PSFB_norm is normalized voltage gain supposing n T 1 = 1.
As for LLC converter, V O_LLC can be obtained as follows: where n T 2 represents the turn ratio from the secondary to the primary side of the LLC transformer T 2 , and M LLC_norm represents the normalized voltage gain of the HB LLC converter supposing n T 2 = 1.
In this paper, the LLC converter operates at the resonant frequency f R to reduce the primary-side RMS current and to prevent switching turn-off losses and reverse-recovery issues in the secondary side diodes.Therefore, by using a fixed f S that holds the value of f R , M LLC_norm is equal to 0.5.
Finally, from ( 7) and ( 8), the voltage gain M is expressed as follows: Normalized voltage gain of the proposed converter M prop_norm (supposing n T 1 = 1) is shown in Fig. 5. From the figure, for the same D eff , the proposed converter achieves a higher voltage conversion ratio than the conventional PSFB converter, because the proposed voltage gain M PSFB is higher according to (6).Also, V O_LLC of the HB LLC converter is added.Thus, the proposed converter can reduce turns ratio n T 1 and n T 2 , thereby decreasing the primary RMS current and reducing conduction loss.

B. CIRCULATING CURRENT AND DUTY-CYCLE LOSS
As shown in Fig. 4(c), which represents mode 3, i pri1 decreases until it reaches i Lm1 , because V lkg1 has a negative value.Thus, as shown in Fig. 4(d), which illustrates mode 4, there is no circulating current, and power continues to be transferred to the secondary side.Additionally, duty-cycle loss does not occur, because V Lm is positive during the change in the direction of the primary current.Thus, the proposed converter removes the conduction loss caused by circulating current and duty-cycle loss.

C. SECONDARY-VOLTAGE STRESS
Fig. 3(a) illustrates mode 1, where the voltage stress is maximum.With the clamping diode D C1 turned on, which providing a clamping path, the voltage at the center-tap of the secondary transformer is set to the clamping voltage, V C .As a result, the maximum voltage stress on the FBR is clamped at 2V C , which is equivalent to n T 1 V S .

D. SWITCHING LOSS IN THE FULL-BRIDGE RECTIFIERS
The reduction in the slope of i pri1 results in a decrease in the reverse-recovery current.In Fig. 4(c), the value of V Lkg1 at −V C /n T 1 is markedly lower than that observed in traditional PSFB converters.Moreover, the reverse voltages of the FBRs have a significantly reduced value of V C , equivalent to 0.5n T 1 V S .As a result, switching losses are greatly diminished due to both the minimized reverse-recovery current and the reduced reverse voltage.

IV. DESIGN CONSIDERATION
To demonstrate the practicality of the proposed converter, a design example is provided.The specifications are as follows: V S = 715 V, V O = 560-800 V, the charging current during constant-current (CC) mode or the maximum output current I O_max = 4.2 A, and f S = 50 kHz.For simple illustration, it is assumed that the magnetizing inductance of the PSFB converter L m1 is sufficiently large, making i Lm1 negligible, and the output capacitances of the secondary diodes are minor enough to be ignored.

A. TRANSFORMER TURNS RATIONS n T 1 AND n T 2
n T 1 and n T 2 can be designed through a relational expression with input and output voltage.As discussed in the previous section, V O_LLC is constant regardless of the D eff , while V O_PSFB is determined by D eff .From (6), by setting the minimum D eff to be 0.2, M norm_PSFB has a value from 0.53 to 0.97.Thus, from (4), the maximum output voltage V O_max and the minimum output voltage V O_min can be expressed as follows, respectively: V O_MIN = 0.53n T 1 V S + V O_LLC (11) Subtracting two equations ( 10) and ( 11), the left-hand side is left with the range of output voltage, and the right-hand side is represented by n T 1 V S .Therefore, when the range of output voltage and input voltage are determined, n T 1 can be designed.In this paper, n T 1 is designed to be 0.77.By substituting (8) for V O_LLC , (10) can be reduced as follows: From ( 12), n T 2 can be easily designed.In this paper, n T 2 is designed to be 0.77.

B. TRANSFORMER LEAKAGE INDUCTOR L lkg1 TO ACHIEVE ZVS FOR LEADING-LEG SWITCHES
As shown in Fig. 3 and Fig. 4, the ZVS for the leading-leg switch is achieved through mode 2 and mode 3.

VOLUME 12, 2024
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.In mode 2, the ZVS energy comes from L O , so that i pri1 equals the primary-reflected output inductor current n T 1 i LO .Mode 3 starts when the clamping diode D C2 is turned on.Since the voltage across does not participate in the resonance for ZVS operation.Thus, the procedure for ZVS is completed by the energy stored in L lkg1 .The ZVS condition can be obtained as follows: where where i LO is the ripple current of L O .By substituting ( 14) and ( 15) for i pri1 (t 2 ) and V C , respectively, ( 13) can be reduced as follows: From ( 16), it can be observed that the condition for L lkg1 to ensure ZVS operation of the leading-leg switch varies depending on the load condition.In order to ensure ZVS operation above 25% load conditions, L lkg1 should be designed to be larger than 27 µH.

C. TRANSFORMER MAGNETIZING INDUCTOR L m2 TO ACHIEVE ZVS FOR LAGGING-LEG SWITCHES
In Mode 5, shown in Fig. 3 and Fig. 4, the ZVS process for the lagging-leg switch is demonstrated.Considering the significant value of L m1 , i Lm1 is assumed to be zero, which means i pri1 is zero.As a result, the PSFB converter does not contribute the ZVS function of the lagging-leg switch.Instead, the ZVS function is achieved by the HB LLC converter.Therefore, the ZVS condition can be derived as follows: where T dead is the deadtime.Since the resonant frequency f R for the LLC converter is equal to the f S , i Lm2 (t 5 ) can be expressed as follows: By substituting (18) for i Lm2 (t 5 ), ( 17) can be presented as follows: From (19), it is evident that the value of L m2 ensures the ZVS operation of the lagging-leg switch, independent of the load conditions and D eff .This makes the selection of L m2 simple.Furthermore, since only the required magnetizing current flows regardless of the D eff value, conduction losses due to magnetizing current can be significantly reduced.

D. RESONANT CAPACITOR C R
C R can be designed by considering the resonant period.Since the f R for the LLC converter is equal to the f S , C R can be designed as follows: where L lkg2 can be simply implemented as the leakage inductor of T 2 .

E. CLAMPING CAPACITOR C C
C C can be designed by considering the peak-to-peak value of the clamping voltage V C,pk−pk during 0.5T S .C C can be expressed as follows: As explained in detail in the previous study [11], The amount of charge to be charged Q Cin and the V C can be expressed as follows, respectively: From ( 22), Q Cin can be obtained, and the largest value is obtained as 24uF, where D eff is at the minimum value.To ensure that the maximum V C,pk−pk is less than 5% of the maximum clamping voltage V C,max , C C is designed to be 2 µF.In (23), V C,max is about 0.5nV S , where D eff is maximum.V C,pk−pk occurs at the minimum D eff , where the offset value of V C is minimum.Therefore, this voltage ripple of V C does not affect the maximum voltage stress in the secondary diodes.

V. EXPERIMENT RESULTS
To validate the viability of the proposed converter, a 3.3 kW prototype was constructed and tested.The test included a constant-current (CC) charging process for rapidly charging the EV battery at low voltage and a constantvoltage (CV) charging process, which reduces the charging current to prevent overcharging as the EV battery voltage increases.The prototype of the proposed converter is shown in Fig 6 .As shown in the figure, the prototype consists of five distinct circuit components.These components include a micro-controller unit circuit, a primary leading leg switches circuit, a primary lagging leg switches circuit, a PSFB converter with novel clamp circuit, and a HB LLC converter circuit.The design parameters are provided in Table 2.

A. SIMULATION RESULTS
Fig. 7 shows the simulation waveforms of the proposed converter during the battery charging from 560 V to 800 V at a CC of 4.2 A. In Fig. 7(a), it is noted that the proposed  converter demonstrates no circulating current on the primary side of the main converter.Moreover, in Fig. 7(b), it is evident that the novel clamp circuit successfully clamps the peak voltage of the FBR at 560 V, which is equivalent to 2V C .

B. EXPERIMENT RESULTS
Fig. 9 and Fig. 10 show the key waveforms of both the conventional PSFB converter and the proposed converter during the battery charging from 560 V to 800 V at a CC of 4.2 A, respectively.As shown in these figures, unlike the conventional PSFB, the novel clamp circuit demonstrates no circulating current on the primary side of the main converter.
Moreover, in Fig. 10(b), it is evident that the novel clamp circuit successfully clamps the peak voltage of the FBR    components such as parasitic inductance inherent in all clamping circuits.Fig. 11 shows the measured efficiencies of the conventional PSFB converter and the proposed converter throughout the CC-CV charging process.It is clear from the figure that the efficiency of the proposed converter is considerably higher across all conditions compared to the conventional PSFB converter.The enhanced efficiency is due to the reduced conduction loss and turn-off switching loss in primary switches Q 1 -Q 4 , as well as the reduced conduction loss in the FBRs D 1 -D 4 .
Fig. 12 shows the loss distribution during the CC mode at the nominal voltage of 700 V.In the figure, Pri.Cond.represents the sum of the conduction losses in switches and windings of transformer T 1 on the primary side, Pri.SW switching.represents primary switching loss, and Sec.cond.represents the sum of the conduction losses in FBRs and windings in transformer T 1 on the secondary side.The Integrated HB LLC. is the sum of the conduction losses in the FBRs and transformer T 2 for the LLC converter.As shown in the figure, the primary switching loss is significantly reduced.Primary switching loss consists of switch-on loss and switch-off loss.However, switch-on loss is negligible in both the proposed converter and the conventional PSFB converter due to the ZVS condition.Instead, the switch-off loss is occurred by switch turn-off current, the i pri flowing through the primary switch at the turn-off point.Because the circulating current is removed, the lagging-leg switches of the proposed converter have no turn-off current.Thus, the primary switching loss of the proposed converter is low.Additionally, the secondary conduction loss is significantly reduced due to the low conduction loss of FBRs.The conduction loss in FBRs is calculated by multiplying the average current in FBRs with V F .Although the average current is almost the same in both the proposed converter and conventional converter, different V F makes a difference in the conduction loss.The conventional PSFB converter using SiC diodes, does not have turn-off crossover switching loss and the RCD snubber loss.However, the conduction loss in the FBRs is increased due to the high V F .Although the addition of the HB LLC converter, the reduction of primary switching loss and secondary conduction loss is more dominant.
Both the volume and the cost of the proposed converter have been reduced, due to the introduced novel clamp circuit.This is because circuit not only diminishes the size of the output inductor but also enables the use of diodes with a lower voltage rating by decreasing the peak voltage of the FBR diode.Furthermore, while conventional PSFB converters typically use SiC diodes, the novel clamp circuit enables the use of Si diodes, leading to significant cost savings.

VI. CONCLUSION
In this paper, a hybrid converter with a novel clamp circuit is proposed.Due to the integrated PSFB converter with HB LLC converter, the proposed converter is suitable for the high output voltage, and ZVS of legging-leg switches can be easily achieved.Also, the novel clamp circuit applied to the PSFB converter consists of two diodes and one capacitor connected to the center of the transformer on the secondary side.As a result, the proposed converter has the advantages, such as no circulating current loss, low voltage stress of FBR diodes, low reverse recovery current, small output inductor, and small output capacitor.Finally, a 3.3 kW prototype was fabricated and tested in the lab.The proposed converter achieved higher efficiency over the conventional PSFB converter.

FIGURE 3 .
FIGURE 3. Key waveforms of the proposed converter.

2 ) 3 )
Excluding the junction capacitors and internal body diodes, the switching devices function as ideal MOSFET.The junction capacitors of all MOSFETs have the same capacitance of C OSS .4) The junction capacitances of the clamping diodes D C1 and D C2 , as well as the secondary diodes D 5 , D 6 , D 7 , and D 8 of the LLC converter, are negligible.This is because their voltage ratings are much lower than those of the FBRs of PSFB converter.5) The leakage inductor L lkg1 of the PSFB converter incorporates the external inductor L ext .Mode 1 [t 0 -t 1 ]: This mode initiates when the commutation from the clamping diode D C2 to the FBR diodes D 1 and D 3 is complete.In this mode, power is delivered to the output through T 1 and L O in the same manner of the conventional PSFB converter.Simultaneously, C O_LLC charges by the resonant current arising from the interaction of the leakage inductor L lkg2 and the resonant capacitor C R .When the clamping diode D C1 is turned on, it provides a clamping pathway, setting the voltage at the center-tap of the secondary of T 1 to the clamping voltage V C .This operation results in the secondary rectifier output voltage V rect1 of the PSFB converter being clamped to 2V C .Hence, the maximum voltage stress on the FBR is restricted to 2V C , effectively reducing voltage ringing, as shown in Fig. 3.This novel clamp circuit allows for the use of diodes with reduced voltage ratings, resulting in decreased conduction losses in the FBRs.

Mode 6
[t 5 -t 6 ]: This mode initiates when the drain-source voltage V DS4 of Q 4 reaches zero.In this mode, commutation occurs from D C2 to the FBR diodes D 2 and D 4 .With Q 2 , Q 4 , D 2 , D 4 , and D C2 turned on, V C is reflected to the primary side, making V Lkg1 equal to -(V S -V C /n T 1 ).The negative V Lkg1 results in a decrease in i pri1 .At the same time, a resonance between L lkg2 and C R begins, charging C O_LLC .The commutation from D C2 to D 2 and D 4 takes place during this mode.The duration of this mode can be described as follows:

FIGURE 5 .
FIGURE 5. Normalized voltage gain M norm according to D eff .

FIGURE 7 .
FIGURE 7. Simulation waveforms of the proposed converter during CC mode with the I O of 4.2 A. (a) V O = 560 V, (b) V O = 800 V.

FIGURE 8 .
FIGURE 8. ZVS simulation waveforms of lagging leg swiches.(a) During CC mode with the I O of 4.2 A and the V O of 560 V. (b) During CV mode with 10% load condition and the V O of 800 V.

Fig. 8
Fig. 8 shows the ZVS simulation waveforms of laggingleg switches.Fig 8(a) shows the waveforms during the CC mode at the output voltage of 560 V, which is the worst case.Meanwhile, Fig. 8(b) shows the waveforms during the CV mode at the 10% load condition.These figures demonstrate the successful ZVS in the primary switches.

FIGURE 9 .
FIGURE 9. Key waveforms of the conventional converter during CC mode with the I O of 4.2 A: (a) V O = 560 V, (b) V O = 800 V.

FIGURE 10 .
FIGURE 10.Key waveforms of the proposed converter during CC mode with the I O of 4.2 A: (a) V O = 560 V, (b) V O = 800 V.

FIGURE 11 .
FIGURE 11.Measured efficiency: (a) CC mode with the I O of 4.2 A and (b) during CV mode with the V O of 800 V.

FIGURE 12 .
FIGURE 12. Loss distribution during CC mode at the nominal voltage of 700 V.

TABLE 1 .
Comparison of the characteristics for the proposed converter with the previous research.

TABLE 2 .
Components list of prototype.