A New Boost Topology Seven-Level Inverter of High Voltage Gain Ability and Continuous Input Current With MPPT for PV Grid Integration

This paper proposes a single-dc-source, seven-level (7L) inverter scheme with a dynamic voltage gain for solar applications. The proposed circuit is created by joining the two DC-DC boost converters in series for discharging and parallel for charging. The finite set model predictive controller is used to deliver the maximum power to the load. Additional details are provided regarding the mathematical expression of volt-ampere balances. The benefits of the proposed topology over current PV inverters are stressed, proving its superiority. Through experimental validation using a lab hardware setup, an improvement in power quality and efficiency of 96.7% is guaranteed. The empirical results are demonstrated by a number of variables, including load fluctuation, modulation index variation, etc.


I. INTRODUCTION
From a few watts to megawatts, grid-connected photovoltaic (PV) systems are an established renewable energy-producing technology.Numerous PV inverters are now available on the market, and several research papers have been presented effectively.On the other hand, the PV has a low output voltage and depends on its unpredictable nature, which needs a DC-DC converter to regulate and boost the voltage to meet the grid requirement.Conventional dc-dc converters are more suitable and reliable.Still, they have limitations in the duty cycle for higher voltage boosting, which can be solved using the high voltage gain DC-DC converters, as reported in [1] and [2].However, their duty cycle, component count, and stress on components are still challenges.Recently, switched capacitor-based inverter (SCI) topologies have emerged in inverter technology due to their offers, such as single-dc source, low voltage stress, and high voltage boosting ability.
The associate editor coordinating the review of this manuscript and approving it for publication was Ahmed Aboushady .
It still offers several technical concerns, such as a high charging current and its required large capacitance value for higher power applications.Additionally, the system's efficiency is affected by the passive component stress and count.
A small magnetic component (inductor) is used to minimize the charging current but not entirely.Therefore, SCI topologies need more research and applicability before being used in a real-time system.The SCIs, however, could be appropriate for low-power applications like microinverters.Combining the DC-DC converter and switched capacitor inverter technique will be the best solution to achieve high voltage boosting with high efficiency and low cost.A simple seven-level inverter with front end conventional DC-DC boost converter is proposed in [3], and the output voltage depends on the DC-DC cycle.This topology suffers due to either high v in or high duty cycle.Furthermore, this topology needs three independent DC sources with three DC-DC boost converters to achieve the seven-level output voltage.Nevertheless, balancing the DC-link capacitor is another challenge and requires an additional control system design.A new control algorithm was introduced in [4] to overcome the PV partial shading issue.
The conventional cascaded h-bridge with integrated PV and dc-dc converter topology is presented in [5] for independent PV arrays.The control method is based on an energy-sampled PV system, and a discrete linear controller is used to ensure the system's stability.The two-dc sourcebased seven-level inverter topology is presented in [6], and it needs two dc sources with independent source control.The above-discussed topologies are designed based on more than one DC source, and these topologies need individual MPPT tracking algorithms and increase the system burden.Single DC-source-based topologies are developed to rectify the above-said issues.A single dc source with one dc-dc boost converter and high-frequency transformer (HFT) is used to achieve the high voltage gain and seven-level stepped voltage waveform [7].However, this topology only supports unity power factor load due to the diodes presented in the current path.The improved structure of [7] is proposed in [8], and it uses a packed-U cell structure as an inverter, whereas a full bridge inverter is used in [8].
The typical mode filter suppresses the leakage current to make this topology suitable for the transformerless grid-tied inverter.The major drawback of these topologies is using a high-frequency transformer for voltage boosting.Due to the presence of HFT, the weight and power loss will be high.Further, to improve the efficiency and reduce the losses, a new switched capacitor structure with the integration of dc-dc boost converter topology with a generalized structure is presented [9], [10].The boost converter inductor acts as soft charging of switched capacitors to suppress the inrush current and voltage boosting.The dedicated seven-level inverter topology with a boost converter is presented in [11].The voltage gain of this inverter is three times higher than the v in, and the maximum duty cycle is fixed at 50%, which affects the dynamic voltage boosting feature.Further, the PV source current is not continuous, i.e., pulsated dc input current, due to the parallel and series connection of the inductor and capacitor, respectively.Further, the high temperatures reduce the power and efficiency produced by PV, while high solar radiation levels enhance these two parameters.Even when the temperature and radiation change, it's crucial to maintain the maximum power point (V mpp ) PV output voltage.
Several articles have investigated how MPPT techniques could be used to accomplish this.The MPPT techniques are divided into two main groups: direct approaches, such as incremental conductance (IC), perturbation and observation (P&O), and intelligent techniques, like methods based on artificial neural networks and fuzzy logic [12], [13], and indirect techniques, such as short-and open-circuit techniques [14].Due to the requirement of prior knowledge of the operating characteristics of PV, it is difficult to precisely track the MPP using indirect methodologies at any cell temperature or solar radiation [15].In contrast, in the direct approaches, the reference signal of a DC-DC boost converter is modified to regulate the voltages of both the photovoltaic and DC-bus.The primary advantages of employing P&O or IC technologies are their reduced cost, compatibility with digital controllers and industrial inverters, and the fact that no prior knowledge of PV is necessary [16].The voltage oscillation during rapid changes in weather conditions is the fundamental drawback of the P&O approach.However, the IC approach improves tracking speed and accuracy problems.The key benefits of adopting intelligent procedures over direct methods are their increased tracking speed and accuracy despite their complexity and high application costs [17].In this case, the IC approach can be utilized in conjunction with a direct control method to enhance the system's characteristics [18].
Therefore, the IC method and MPC are coupled to accomplish the MPPT from the PV system.First, the best current  possible from the PV, I refPV is obtained using the IC concept.The major highlight of the proposed topology is listed as follows: • Single DC source and conventional DC-DC boost converter are used.
• Wide range of input variation.
• Capacitors are balanced and have low capacitance values.
• Applying the combined IC+FCS-MPC to extract the maximum power from the PV system.
• Achieving a unity power factor while connecting to the grid.
• PQ control scheme is used for grid connection.

B. MODES OF OPERATION
The conv A and conv B are cascaded on the source side but the output of these two converters is in series to the load side as shown in Fig. 1.Assume that capacitor C T has been fully charged.Initially, the conv A charges the inductor via S T , and the pre-charged capacitor C T supplies the energy to the load.The inductor energy that has been stored is released to charge the C T and C VS capacitors when the S T is switched off.The C T and C VS stored energy is equivalent to the v PV /(1-D 1 ).By turning the switch S B ON and OFF, the capacitor C B is discharged and charged, respectively, and the ), and the conv B duty cycle (D 2 ) is fixed at 50% to maintain the symmetric output voltage waveform at load.It is important to note that even a small To reach the peak voltage in the third level, the capacitor voltages v CT and v CB will be summed together by turning ON the S 3 and turning OFF S 2 as shown in Fig. 2 (c).Similarly, the same-level generator switches are triggered to produce the negative output voltage.Still, instead of H 1 /H 4 pair, the H 2 /H 3 pair is used as given in the switching sequence in Table 1.Another important state is zero states which can be obtained by turning either H 1 /H 2 or H 3 /H 4 switch pairs.The simple sinusoidal level shifted pulse width modulation scheme is used to generate the required pulses, as shown in Fig. 3.Here worth mentioning that the proposed topology switch count is low, reducing the logic gates' utilization and improving the digital processor speed.Further, the maximum number of the on-state switch is four for level generation.

C. MATHEMATICAL MODELLING OF DC-DC CONVERTER
The mathematical analysis for the proposed DC-DC converter is discussed as follows.When the switch S T is turned ON, the inductor stores the energy to supply both C T and C VS will charge as given in (1).Similarly, the i LB is getting charged to (2) The capacitor's voltage (v CT & v CB ) depends on the duty cycle (D 1 and D 2 ) and source voltage which is expressed in (3) and (4) for both conv A and conv So, the inverter output voltage depends on the sum of the two capacitors, i.e., Equations ( 3) and (4) will obtain (5), and voltage gain is expressed in ( 6) where M is the modulation index.The steady analysis is calculated for resistive load and can be extended to resistiveinductive load.
By applying standard Kirchhoff voltage law (KVL) and Kirchhoff current laws (KCL) to the circuit depicted in Fig. 4, the following differential equations can represent the parallel connected dc-dc boost converter.
During the 3 rd level, the C T and C B are series, and the ( 8) and ( 11) can be summed as follow: Since the proposed topology output voltage depends on the duty cycle of both the converter, it is necessary to find the maximum voltage gain of the proposed inverter.Fig. 5 shows the various combination of duty cycles with a voltage gain, the maximum duty cycle is fixed at 80%, and the maximum gain is 30 times higher than v pv for both D 1 = D 2 =80%.
However, the output voltage steps will not be equal.Here worth mentioning that the higher gain can be achieved with small tolerance of unsymmetrical stepped waveform.

III. PROPOSED CONTROL TECHNIQUES FOR THE DUAL DUTY HIGH GAIN SEVEN LEVEL INVERTER (D2HG-7L)
The precise control procedures for all systems and converters will be covered in this section.
A. MPPT FROM THE PV ARRAY Fig. 6 shows the flowchart of the IC algorithm.The generated PV output current and voltage are measured to establish the basic operating principles of this IC technology.Next, differentiate to time, and the results are compared with zero.Based on the output voltage and current sign, the incremental value E, a trade-off between the oscillation of power and the tracking speed of the MPP, is utilized to update the I refPV value.The MPC will then use this optimal current to regulate the ON/OFF states of the one duty for the proposed D2HG-7L converter.The discrete model for this upper boost  converter state, i LT , must be defined in order to apply the MPC to predict the following action.As previously described, there are two possible switching states, 1 or 0. These switching states and the Euler discretization rule are used to calculate the expected value of the inductor current, i LT (k+1), which is equivalent to the PV output current, for the dynamic model of the upper boost converter.It is distributed by where k and (k+1) refer to the current and next instant, respectively.S T is the switching state 1 or 0. V pv , T s , V Vs are the PV output voltage, the sampling time, and the bottom capacitor voltage.The predicted current i LT (k+1) depends on the switching state.To produce the MPPT, the switching state is chosen based on the cost function that minimizes the difference between the expected input top boost converter current and the reference acquired from the IC method.The selected cost function is as follows where X is the penalty function that is utilized to avoid a short circuit in the PV array and is established by The PV array's MPPT controller is depicted schematically in Fig. 7.By reducing ripple oscillation and raising computation precision, the MPC controller increases tracking accuracy.

B. CONTROL OF THE SINGLE-PHASE GRID-SIDE INVERTER
To eliminate phase or frequency mismatches, grid-connected inverters must have a clean phase lock and reject any oscillation/fluctuation or voltage changes.

1) ENHANCED PHASE LOCKED LOOP (EPLL)
Grid synchronization is crucial for the control system of a PV system connected to the grid [19], [20], [21].As a result, grid angle estimation is required for synchronism while injecting power into utilities.The system can function at a unity power factor in the typical operational mode with satisfactory synchronization.Therefore, the phase-locked loop (PLL) synchronization methods should have quick and precise dynamics [22].Figure 8 shows the general structure of the PLL which consists of three parts (1) Phase Detector (PD) to detect the phase difference; (2) Loop Filter (LF); and (3) Voltage Controlled Oscillator (VCO).The proportionalintegral (PI) controller is used as an LF to improve the filtering capability of the PLL.Meantime, an integrator is used to represent the VCO.Meanwhile, a sinusoidal multiplier can be the fundamental PD.The output of the basic PLL with a sinusoidal multiplier has double-frequency ripples, which are challenging for the LF to remove even in a perfect situation [21].Therefore, an improvement for the PD unit based on adaptive notch filtering (ANF) is used due to its simplicity, robustness, and effectiveness.Consequently, this PLL with this improvement in the PD is adopted in this work and may called is called enhanced PLL (EPLL).Phase-angle tracking, and amplitude estimation are accomplished through the control loop of the EPLL, and the aforementioned significant shortcomings of the conventional PLL are removed.The structure of this EPLL is shown in Fig. 9.The input grid voltage can be assumed to be purely sinusoidal with rated grid frequency and expressed by v in = V g sin θ in , while the estimated output voltage can be given by v out = V g ′ sin θ in ′.Hence, the phase error output of the PD is provided by Meanwhile, the amplitude of the grid voltage can be estimated by At steady state, the amplitude and phase output voltage is approximately equal to the amplitude and phase of the grid voltage, V g ′ = V g and θ in ′ = θ in .The double-frequency term therefore equals zero.There won't be any double-frequency ripples in the calculated signals' phase angle, frequency, or amplitude [23].

2) DC-BUS VOLTAGE CONTROL LOOP
The DC-bus voltage is continuously maintained by controlling the power supplied from the PV to the grid.This is demonstrated using the balance between input-output power and the assumption that the system is lossless [24].
The amount of the DC-bus voltage depends on how much PV output power is there.As a result, it controls the DC-bus voltage via PI control.

3) REFERENCE GRID CURRENT GENERATION
The reference current, i * g injected into the grid is generated from the reference active, P * and reactive power, Q * .According to the single-phase instantaneous power control theory, the reactive power, Q * and active power, P * references are used to determine the inner control loop's current reference, i * where v gα , v gβ , i gα , and i gβ are the orthogonal components of the grid voltage and current.
Using the reference active and reactive power, the reference i * gα can be obtained based on the previous relations and calculated from the following relation.
Using the orthogonal signal generator, the reference β-axis current, i * gβ can be generated.Hence, the reference αβaxis currents can be transformed into dq-axis currents to be used for the closed loop of the current control loop.

4) CURRENT CONTROL LOOP (CCL)
The CCL is designed based on applying two PI controls in this part.The dq-axis output voltages generated from the inverter are represented by [26] where R f , L f , and ω g represent the resistance and inductance of the filter and the grid angular frequency, respectively.These two relations can be rearranged as follows 139242 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.It can be observed that the values of the filter can be substituted using PI controller as follows.
From ( 26) and ( 27), it is noticed that the output dq-axis currents of the inverter are managed by adjusting the dq-axis  voltages (v id , v iq ) where voltage compensation is used to remove the coupling effect.Meanwhile, the reference q-axis current is maintained at zero value to achieve a unity power factor.The overall control diagram is shown in Fig. 10.

IV. POWER LOSS ANALYSIS
The power loss analysis for the proposed topology is divided into (i) front-end dc-dc converters and (ii) inverters, including level generators.The dc-dc converter has high-power losses due to operating at a high switching frequency.Still, in the case of polarity changes and levels generators are switched at a low switching frequency.The power losses are measured using the PLECS software using the IGB30N60T_IGBT switch datasheet.During a simulation period t s , the number of switching times n can be determined by detecting the voltage's rising and falling edges.The peak voltage and current can also be measured.The datasheet specifies the switching energy to calculate the power switch's average turn-on and turn-off loss as expressed in (28).
where is i peak (n) and v peak (n) are the current and peak voltage measured at n th rising and falling edges of voltage, respectively.f Eon and f Eoff are the switching energy function corresponding to the peak voltage and current when the power switch is turned ON and OFF, respectively.The average conduction loss of the power switch can be expressed in (22).
139244 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
where i c and v CE are the collector current and voltage across the college and emitter.The cycle-average loss calculation in the schematic method is shown in Fig. 11 (a), and the simulated component losses are shown in Fig. 11 (b) for the power output power of 650W and 750W.

V. RESULTS AND DISCUSSIONS
The performance of the proposed topology is evaluated using both simulation and developed prototype model for an output power of 750W and Sunpower-SPR-305 PV array is used as a source in MATLAB software.Fig. 12 (a)-(c) shows the simulated output waveforms of grid voltage, current and inverter voltage, respectively, during the power factor changes from lagging to leading.However, it is a fact that if any changes occur in the system there will be small distribution as shown in Fig. 12 (c) at 0.4s.In the simulation, the minimum irradiance is 800W/m 2 at 0 to 2s, during the 2s to 2.5s the irradiance is increased to 900W/m 2 and further raised from 900 W/m 2 to 1000 W/m 2 at a time of 5s to 7s.Additionally, several cases are simulated to check the performance of the proposed topology and the results are shown in Fig. 13 (a)-(f).Initially, the irradiance is kept as 800 W/m 2 varied to a maximum of 1400W/m 2 and the corresponding output power, grid current and power are shown in Fig. 13 (b), (d)-(e).Here worth to mention that the proposed topology regulates the dc-link voltage to a reference value of 400V and maintains the grid voltage as shown in Fig. 13 (c) and (f).Since the MPPT is implemented in the proposed topology, it tracks the reference and injects the maximum power into the grid.Further to validate the performance of the proposed topology is tested in a prototype-hardware setup is shown in Fig. 14.The experimental parameters and its specifications are given in Table 2. Various experimental results are obtained using the Keysight-3034T DSO.
In this standalone mode, the input voltage is kept at 66V, and the maximum output voltage and current is 390V and 3.7A, respectively for the load R=100 , L=100mH at a power factor of 0.95 as shown in Fig. 15(a).The boost switch (S T ) is switched at 20kHz with a duty cycle of 50%, and the inductor voltage (v L ) and current (i L ) are 66V and 11.3A, respectively.Further, the load variation is performed under the load value of R=100 , L=100mH to R=80 , L=100mH for the power factor 0.93.As shown in Fig. 15 (b), the capacitor voltages are maintained during the load variations and confirm the proposed system's dynamic response under sudden load changes.As mentioned earlier, the proposed topology is more opt for PV applications.Any power converter should be able to respond to the sudden irradiance and source voltage changes.To confirm this, step-input changes are applied to the source voltage from 50V to 66V and the corresponding output voltage, current and capacitors voltage waveform are depicted in Fig. 15 (c) and (d).In addition, the modulation index variation is another important parameter to evaluate the inverter.Here, the modulation index varies from 1.0 to 0.5 and the measured waveforms are shown in Fig. 15 (e) with a maximum and minimum load current of  3.7A and 1.8A, respectively.Also, the blocking voltage of the switch S T , S B , S 1 and S 3 are shown in Fig. 15 (f) which is lower than the peak output voltage.However, the proposed topology h-bridge switches should be able to withstand the peak output voltage.The capacitor (v CT , v CB and v VS ) voltage and current waveform are shown in Fig. 16 (a)-(b), respectively.Fig. 16 (b) clearly shows that each capacitor is charged through the inductor, which limits the large charging current, i.e., inrush current.In contrast, in a switched capacitor inverter, the charging current is higher than 20 times than the load current.
The capacitor voltages are maintained to desired voltage and ripple is higher in v CT than in v CB .The maximum capacitor current is 20A and the average current is 9.8A.The proposed topology is connected to the laboratory's distribution panel to check the grid connection's feasibility and the corresponding grid voltage and current with a unity power factor as shown in Fig. 17  corresponding inverter output voltage also presented.During the irradiance variations the proposed control system maintains the dc-link voltage to 400V.This is another proven result that the proposed topology can inject power into the grid.The detailed comparison is presented in Table 3.It is clear that the proposed topology has maximum voltage gain compared to all the topologies without using any high-frequency transformers.Also, the proposed topology has a low device count with easy MPPT control.Further, the proposed topology's maximum efficiency is 96.7% for the output power of 750W, which is lower than the simulation, as shown in Fig. 18.The efficiency of the proposed topology is measured by varying the load power from 150W to 750W under the unity power factor condition i.e pure resistive load.The proposed topology has low efficiency at low power due to the high internal resistance of the semiconductor devices.Further, the efficiency of the simulation and experimental is becoming very close when the output power is high.From the above experimental validation, the proposed topology is a good candidate and promising inverter for photovoltaic applications.

VI. CONCLUSION
A new seven-level high voltage boosting inverter topology was presented with a reduced device count.The modes of operation with various mathematical analyses were derived.Further, the model predictive control was implemented to track the maximum power point in the PV system, and detailed explanations were included.Several simulation and experimental results were examined under different loading conditions such as lagging, leading power factor, step changes, etc. Further, the proposed topology does not have a high inrush current, and it has high voltage boosting achieved.The combination of the proposed topology and MPC mppt is a suitable candidate for high voltage boosting with grid-tied PV applications.

Fig. 1
Fig.1shows the proposed seven-level circuit diagram, which consists of two DC-DC boost converters (conv A and conv B ), a single-phase full bridge inverter (H 1 -H 4 ), and level-generating switches (S 1 -S 4 ).The string of PV panels is

FIGURE 5 .
FIGURE 5. Various voltage gains with respect to D1 and D2.

FIGURE 6 .
FIGURE 6. Flowchart of the incremental conductance (IC) algorithm for the MPP extraction.

FIGURE 8 .
FIGURE 8.The basic block diagram of the PLL technique.

FIGURE 9 .
FIGURE 9.The instruction of the enhanced PLL technique.

FIGURE 10 .
FIGURE 10.The overall block diagram of the differences for the proposed system.

[ 25 ]
. The active and reactive power relations for the single phase can be expressed by P = v gα i gα + v gβ i gβ 2(19)

FIGURE 11 .
FIGURE 11.(a) Schematic of calculation of total cycle average losses [8] and (b) Power loess breakdown for components.

FIGURE 12 .
FIGURE 12. Simulation result of leading and lagging power factor (a) grid voltage, (b) grid current, and (c) inverter output voltage.

FIGURE 17 .
FIGURE 17. Experimental result of (a) grid voltage and current and (b)PV input current and dc-link voltage.
(a).The PV input voltage and 139246VOLUME 11, 2023    Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE 1 .
Switching sequence for positive half cycle.

TABLE 3 .
Comparison of various PV seven level inverter topologies with proposed topology.