A Synchronization Shift Phase-Locked Loop Strategy for Three-Phase Grid-Tied Inverters Under Unbalanced Grid Voltage Scenarios

The phase-locked loop (PLL) is one of the most commonly used approaches for the inverter to achieve grid-connected operation. However, when unbalanced grid voltages occur, the double-line frequency oscillation exists in the system. With the conventional PLL method, the synchronous reference frame (SRF) voltage will be oscillated because of the double-line frequency oscillation. As a result, the electrical angle of the grid cannot be estimated accurately. Moreover, inverter output currents will be distorted and the current total harmonic distortion (iTHD) will be increased. To solve this issue, an enhanced synchronization shift phase-locked loop (SSPLL) strategy is proposed in this paper. With the proposed SSPLL, the inherent double-line frequency oscillation in the control loop can be eliminated. Therefore, the electrical angle of the grid can precisely be calculated, whereas the current THD can be suppressed. The developed SSPLL can be realized by the digital signal processor (DSP) without adding extra circuits and components. Comprehensive theoretical analysis and mathematical derivations of the SSPLL are also revealed. Eventually, both simulation and experimental results obtained from a 5kVA prototype circuit will be presented to verify the performance and feasibility of the proposed SSPLL. Compare to conventional PLL methods, a maximum 65.22% improvement of current THD and a maximum 51.2% improvement of the controller execution time can be achieved with the proposed strategy.


I. INTRODUCTION
To achieve carbon neutral and net zero emission, renewable energy systems (RESs) have received significant attention in recent years [1], [2], whereas the energy storage systems (ESSs) are often included in the RESs [3], [4].In order to regulate the electrical energy of the renewable energy source, the battery and the grid, power electronic technologies and grid-tied inverters play vital roles in the system [5], [6].In addition, grid-connected power converters provide the capability of active and reactive power compensating, which can stabilize the voltage amplitude and frequency of the power grid [7], [8].Besides, during the grid-fault occurs, the The associate editor coordinating the review of this manuscript and approving it for publication was Huiqing Wen .
inverter with the low-voltage ride-through (LVRT) capability contributes to the recovery of the grid [9], [10].In other words, the power system quality can be increased by the adoption of grid-tied inverters.To ensure the stable operation of the grid-tied inverter, simultaneous diagnosis methods and the voltage sag state estimation of the inverter are also necessary [11], [12], [13].
The phase-locked loop (PLL) is a commonly adopted function for the grid-tied inverter to estimate the electrical angle of the grid.With PLL, the phase-shift between the inverter output current and the grid voltage can be controlled, whereas the active and reactive power of the inverter can be regulated [14].Generally, the synchronous reference frame phase-locked loop (SRF-PLL) is one of the most commonly used methods for the three-phase system [15], [16].
With SRF-PLL, the three-phase ac components will be converted into two dc components, whereas the control can be simplified.
However, when the grid fault occurs, the three-phase voltage might be unbalanced.The double-line frequency oscillation exists in the system under unbalanced grid voltage scenarios.Unfortunately, the double-line frequency oscillation can also be observed in the output signals of SRF-PLL.The electrical angle of the grid will inaccurately be estimated.As a result, the output currents will be distorted and the total harmonic distortion (THD) of inverter output currents will be increased.
Some literatures focused on improving the performance of the grid-tied inverter under weak grid conditions [17], [18].First, a passivity enhancement method to attain the positive output resistance of the grid-connected inverter (GCI) in the qq channel was proposed in [17].Besides, GCI's complete harmonic state-space (HSS) model considering PLL under the asymmetrical network was established in [18].With eigenvalue locus analysis, the stability boundaries of the system's critical parameters involving the current reference, current controller, and PLL controller are determined under different grid impedance asymmetrical indexes.In these two literatures, a prefilter and an impedance phase regulator were included to remove the oscillation of the PLL control loop.
In addition, the PLL-based and PLL-less control strategies were analyzed and compared in [19] and [20].These two articles revealed that the PLL-less method falls behind in two conditions: 1) when the grid frequency offsets occur and 2) when unbalanced grid voltage faults occur.Therefore, a band-pass filter (BPF) was introduced for the PLL-less control to achieve the same performance of the PLL-based control under weak grid conditions.The conclusion is that the PLL-based approach is still a superior choice if the controller and the PLL are designed well.Therefore, the PLL-based control will be selected in this paper.
On the other hand, the dual second-order generalized integrator phase-locked loop (DSOGI-PLL) was proposed to suppress the double-line frequency oscillation in the control loop [21], [22].However, this method is relative complex.With DSOGI-PLL, it is necessary to include an extra conversion frame and two second-order generalized integrators (SOGIs).Consequently, the control complexity and the MCU calculating period will be increased.
This paper proposes an enhanced synchronization shift phase-locked loop (SSPLL) strategy for three-phase inverters under unbalanced grid voltages.One of the main features of the proposed SSPLL is the simplicity.With the SSPLL, the double-line frequency oscillation can be eliminated without adding extra circuits, components, and complex computing processes.Moreover, the electrical angle of the grid can precisely be estimated.Comprehensive theoretical analysis, operational principles and mathematical derivations of the proposed control strategy will be presented in this paper.Finally, a 5kVA prototype circuit of a three-phase T-type inverter will be implemented.Both simulation and experimental results verify the performance and feasibility of the proposed strategy.From the comparison results, a maximum 37.9% improvement of current THD can be confirmed with the proposed SSPLL strategy.

II. THE THREE-PHASE GRID-TIED INVERTER AND CONVENTIONAL PLL UNDER UNBALANCE GRID VOLTAGES
Fig. 1 shows the circuit diagram of the T-type three-phase grid-tied inverter.It can be seen that twelve power switches, two dc capacitors and three ac inductors are included in the circuit.Fig. 2 shows the control block diagram of the conventional SRF-PLL.With the SRF-PLL, three-phase ac voltage signals, v a , v b , and v c will be converted into two dc components, v d and v q , by the synchronous reference frame, T dq .The conversion equation can be expressed as: In Fig. 2, ω ff is the feedforward line frequency, which is set the same as the line frequency.ω o is the estimated line frequency from PLL. θ PLL is the angle calculated by PLL.Under normal condition, three-phase voltages are balance.The amplitude of three-phase voltages should be equal, and there should be a 120 degree out of phase shift between each phase.However, non-ideal conditions, such as unbalanced power loads and grid faults might cause unbalanced grid voltages.If the unbalanced grid fault occurs, both positive-sequence and negative-sequence voltage components exist in the power system.There will be double-line frequency oscillation on the d-axis and q-axis voltages.In addition, the average value of the d-axis voltage will be decreased due to the grid voltage attenuation, as shown in Eq. (2). )) Besides, if the unbalanced phase of grid voltages occurs, the double-line frequency oscillation can still be observed in v d and v q , as shown in Eq. (3).
where θ a represents the diverged phase angle under the unbalanced grid phase scenarios.Fig. 3 shows relation diagrams of v d , v q , θ PLL , and ω o under unbalanced grid voltages.It can be seen that the double-line frequency oscillation occurs on v d and v q .As a result, ω o is oscillated while θ PLL will be distorted.
Due to the oscillation of ω o and the distortion of θ PLL , the three-phase current commands will be distorted, whereas unexpected harmonic components will be generated, as shown in Fig. 4. From Fig. 4, it can be confirmed that the first-order and the third order harmonic components are main factors to distort current commands.It is worth mentioning that the first-order harmonic will cause error amplitude of current commands while the third order harmonic increases the current THD.According to Eq. ( 2) and Eq. ( 3), it can be observed that the more severe the unbalanced grid voltage is,  the larger the line frequency (ω o ) error will be.Therefore, there will be a linear relationship between the current command error and the phase voltage drop, as depicted in Fig. 5.

III. THE PROPOSED SYNCHRONIZATION SHIFT PHASE-LOCKED LOOP STRATEGY
In order to eliminate the line frequency (ω o ) error and the PLL angle (θ PLL ) distortion, the synchronization shift phase-locked loop (SSPLL) is proposed.Fig. 6 shows the control block diagram of the proposed SSPLL.The main difference between the conventional PLL and the proposed one is to include an adaptive high-pass filter (AHPF) in the control block.From Fig. 6, the v d signal will be fed into the AHPF and a new signal, v * d will be generated.Then, the summation of v * d and v q will be utilized for the PLL controller.It should be mentioned that the double-line frequency oscillation will be removed with the adopting of AHPF.There is no need to modify the inherent controller parameters.As a result, ω o error and θ PLL distortion can be eliminated under unbalanced grid voltages with the proposed SSPLL.In the following, operational principles of the AHPF will be described in detail.
The control block diagram of the proposed AHPF is shown in Fig. 7. First, from Eq. ( 1) and Eq. ( 2), it can be confirmed that the average value of v d will be decreased due to the grid voltage attenuation or the grid phase diversion.Besides, the double-line frequency oscillation occurs on both v d and v q .According to mathematical derivations and Fig. 3, it can be   observed that there is a 90 degree out of phase shift between the oscillated v d and v q waveform.Therefore, the major objective of the AHPF is to produce a 90 degree out of phase shift between the input signal and the output signal.
From Fig. 7, the transfer function, H(s), of the AHPF can be derived as Eq. ( 4).The frequency response bode plot of the AHPF can be depicted in Fig. 8.
The conceptual diagram of the AHPF is shown in Fig. 9. v * d represents the output signal of the AHPF.It is worth mentioning that using a high pass filter with a setpoint crossover frequency can remove the DC offset.However, this is still not enough for the proposed SSPLL.There are two main purposes of the AHPF: (1) Remove the dc offset of the signal and (2) Create a 90 • out of phase shift from the input signal.Compare to the conventional high pass filter, the AHPF can  not only remove the dc offset but also achieve a 90 • out of phase shift.It should be mentioned that there is an inherent 90 • phase shift between the original v d and v q signal under unbalanced grid conditions, as shown in Fig. 9.In Fig. 9, it can be confirmed that the AHPF output signal (v * d ) is with the same magnitude and same phase of v q .That is to say, the oscillation of v q can be eliminate via the integration of v The v * d and v q under the grid voltage magnitude unbalanced can be expressed as: )) )). ( Besides, v * d and v q under the grid voltage phase unbalanced are derived as: According to Eq. ( 5) and Eq. ( 6), it can be seen that v * d and v q will be equal under both grid voltage magnitude unbalanced and grid voltage phase unbalanced scenarios.Therefore, the difference between v * d and v q will be zero, as indicated in Eq. (7).
From Eq. ( 7), the ac component can be removed via the proposed SSPLL and AHPF.That is to say, the oscillated ac component will not be fed into the PLL controller.Fig. 10 shows relation diagrams of v * d , v q,SSPLL , θ SSPLL , and ω o with the proposed SSPLL under unbalanced grid voltages.It can be confirmed that with the proposed strategy, θ PLL will not be distorted, whereas ω o will not be oscillated.As a result, the inverter output current distortion can be mitigated.
According to the above analysis, the line frequency (ω o ) error and the PLL angle (θ PLL ) distortion can easily be 121166 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.compensated via SSPLL under unbalanced grid voltages.Compare to the conventional SRF-PLL and DSOGI-PLL, only one filter, the AHPF, should be included with the proposed strategy.There is no need to add extra circuits and components.Moreover, the AHPF and SSPLL can be implemented in the digital signal processor (DSP) without adding external circuits.Eventually, iTHDs can effectively be suppressed while the circuit performance can be increased.
Overall control block diagrams of the proposed circuit and control strategy are shown in Fig. 11.The proposed SSPLL control, the DC capacitor voltage balancing control, the feed-forward duty generator, three-phase current regulators, and the sinusoidal pulse-width-modulation (SPWM) are included in the system control diagram.It is worth mentioning that the three-phase individual control is adopted in this work.The proportional-integral (PI) control is adopted for the current controller.The transfer function of the current controller is expressed in Eq. (8).where K p and K i are the proportional gain and the integral gain, respectively.ω i is shifted frequency of the current controller.Traditionally, the pole of the PI controller is located at 0Hz.However, in order to prevent the unexpected dc-bias component in the control loop, ω i is introduced.With the adoption of ω i , the pole can be located in higher frequency, whereas the low-frequency gain can be suppressed.It should be noticed that in Fig. 11, v bal is the dc-link voltage balancing comment and it is not only used in the Phase-A current regular, but also included in the B-phase and C-phase current regulator.
In order to highlight the contribution and feasibility of the proposed SSPLL strategy, comparative analysis with respect to the state-of-art will be presented.Different PLL methods are investigated and compared, as illustrated in Table 1.First, main features of the PLL-less and the SRF-PLL control are the simplicity and fast response.However, ω o error and θ PLL distortion cannot be neglected with the PLL-less and the SRF-PLL control under unbalanced grid voltages, whereas the iTHD might be increased.To overcome this issue, the PLL-less with BPF [19] and the enhanced  [17], [18] were developed.These two methods can the iTHD.However, extra filters or an impedance phase regulator are required.Finally, Both DSOGI-PLL and the proposed SSPLL provide the ability to eliminate ω o error, θ PLL distortion and to reduce iTHD.However, the control of DSOGI-PLL is relative complex while the controller response will be decreased.On the other hand, with the proposed SSPLL, ω o error, θ PLL distortion can be eliminate with simple control and fast response.

SRF-PLL
It is worth mentioning that there is almost no impact on the controller response and complexity with the adoption of AHPF, and it will be verified in the experiments.

IV. SIMULATION AND EXPERIMENTAL RESULTS
A T-type three-phase grid-tied inverter is implemented to verify the proposed circuit and control strategy.Table 2 shows circuit specifications of the three-phase grid-tied inverter.The rated power is 5kVA.The input DC voltage is set as 800V.The output three-phase line-to-line voltages are 220V rms /60Hz.The DC-link capacitance and the output inductance are 0.825mF and 2mH, respectively.The switching frequency is 121168 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.set as 20kHz.The IGBT module, 10-FZ12NMA080SH01-M260F, is chosen as the main circuit switches.The sampling time of the proposed circuit is 50us and it is set the same as the switching period.
In order to verify the proposed SSPLL, three voltage unbalanced scenarios will be built.For Scenario I, the a-phase voltage is decreased to 0.7p.u.(154V rms ).For Scenario II, the a-phase voltage is decreased to 0.5p.u.(110V rms ).Scenario III demonstrates the two-phase voltage unbalanced condition.In this case, a-phase voltage is decreased to 0.7p.u.(154V rms ) while the b-phase voltage is set as 0.5p.u.(110V rms ).Under this scenario, all three voltages are unequal together.
It should be noticed that because of the limitation of the experimental equipment, the distorted or dc-biased grid voltage conditions are not presented.However, the cross-over frequency of the controller is designed as 1kHz.The gain with the controller will be greater than 0dB in the grid distortion frequency range, whereas the range is usually within 300Hz∼500Hz.Besides, the dc gain of the controller will be very large, which can eliminate the dc-biased component of the grid voltage.That is to say, the designed controller has the ability to compensate and suppress the harmonic distortion and the dc-biased components of the grid voltage theoretically.
In the following, both simulation and experimental results will be presented to demonstrate the performance and feasibility of the proposed SSPLL.

A. SIMULATION RESULTS
The computer simulation software, PLECS, is selected for verifying the proposed strategy.Fig. 12 shows simulation waveforms of the grid voltages and the estimation of ω under Scenario I.In this scenario, a-phase voltage is decreased to 0.7p.u.(154V rms ).It can be seen that the double-line frequency oscillation exists in the line frequency with the conventional SRF-PLL.This oscillation can be removed by the DSOGI-PLL.However, a certain response time is required to reach the steady-state operation with the DSOGI-PLL.On the other hand, with the proposed SSPLL, the double-line frequency oscillation can effectively be eliminated with faster dynamic response.The key factor to affect the dynamic response will be the controller execution time, and it will be verified via experiments.Besides, circuit diagrams of the T-type three-phase grid-tied inverter and the proposed SSPLL with PLECS are shown in Fig. 13.
Simulation results of grid voltages, output currents with different PLL strategies under Scenario I are shown in Fig. 14.It can be seen that output currents with conventional SRF-PLL will be significantly distorted.However, the current distortion phenomenon can be mitigated by both the DSOGI-PLL and the proposed SSPLL.Simulation results of Scenario II are shown in Fig. 15.In this scenario, v a is decreased to 0.5p.u.(110V rms ).Therefore, compare to Scenario I, ω o error and the output current distortion will be increased.On the other hand, simulation results of Scenario III are shown in Fig. 16.In this scenario, v a is decreased to 0.7p.u.(154V rms ) while v b is decreased to 0.5p.u.(110V rms ). it can be confirmed that the proposed SSPLL is still effectively under the two-phase voltage unbalanced condition.

B. EXPERIMENTAL VALIDATIONS
In this section, experimental validations will be presented.Fig. 17 shows the experimental setup.The DC source, Keysight RP7953A, is connected to the input of the inverter.The grid simulator, Chroma 61815 is connected to the output of the inverter.The IEC 61000-4-7 regulation is adopted for the current THD measurement.
Experimental waveforms of grid voltages and output currents with different PLL strategies in full load operation under Scenario I are shown in Fig. 18.From the results, it can be confirmed that with full load operation under Scenario I, the current THD with the conventional SRF PLL is 2.93%.However, the current THD is reduced to 1.63% and 1.57% with the DSOGI-PLL and the proposed SSPLL, respectively, under the same operating condition.Experimental waveforms of grid voltages and output currents with different PLL strategies under Scenario II are shown in Fig. 19.Under this scenario, the current THD with the conventional SRF-PLL is 4.4%.The current THD with the DSOGI-PLL is 1.63%, whereas the current THD with the proposed SSPLL is decreased to 1.53%.Finally, experimental waveforms of grid voltages and output currents with different PLL strategies in full load operation under Scenario III are presented in Fig. 20.In this case, the current THD of the SRF-PLL, the DSOGI-PLL and the proposed SSPLL are measured as 2.7%, 1.93% and 1.83%, respectively.

C. PERFORMANCE COMPARISON
In order to comprehensively demonstrate the feasibility of the proposed PLL strategy, performance comparisons will be presented in this section.Current THD comparisons of 121170 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.different PLL strategies with different load conditions and different scenarios are shown in Table 3, Table 4 and Table 5.
The measured results in Table 3, Table 4 and Table 5 are also depicted in Fig. 21 From Table 3, Table 4, Table 5 and Fig. 21, it can be confirmed that under different unbalanced voltage scenarios and different load conditions, the proposed SSPLL strategy can effectively reduce the current THD.Under the full load operation of Scenario II, the maximum current THD improvement rate can be obtained, which is calculated as 65.22%.Fig. 22 shows the execution time comparison of different PLL strategies.First, the execution time of the conventional SRF-PLL is 801ns, as shown in Fig. 22 execution time of the SRF-PLL, but is much lower than the execution time of the DSOGI-PLL.Both of the DSOGI-PLL and the proposed SSPLL provide the ability to suppress iTHD under unbalanced grid conditions.However, with the proposed SSPLL, the execution time can be improved with 51.2%.In other words, the dynamic response can be increased while the executing loading of the controller can be decreased with the proposed control strategy.

V. CONCLUSION
In this paper, an enhanced synchronization shift phase-locked loop (SSPLL) strategy is proposed.Under unbalanced grid voltage scenarios, the line frequency error and the PLL angle distortion can be eliminated with the proposed strategy, whereas the current THD can be suppressed.Compare to the conventional PLL method, only one adaptive high-pass filter should be included in the controller.Moreover, the SSPLL can be implemented in the DSPs.There is no need to add extra circuits and components.Thorough theoretical analysis and mathematical derivations are revealed in this paper.Finally, both simulation and experimental results obtained from a 5kVA prototype circuit verify the performance and feasibility of the proposed SSPLL strategy.

FIGURE 1 .
FIGURE 1.The circuit diagram of the T-type three-phase grid-tied inverter.

FIGURE 2 .
FIGURE 2. The control block diagram of the conventional PLL.

FIGURE 3 .
FIGURE 3. Relation diagrams of v d , v q , θ PLL , and ω o under unbalanced grid voltages.

FIGURE 4 .
FIGURE 4. Conceptual diagram of distorted current commands and harmonic components caused by the θ PLL oscillation.

FIGURE 5 .
FIGURE 5.The relation between the current command error and the grid voltage dropping rate.

FIGURE 6 .
FIGURE 6.The control block diagram of the proposed SSPLL.

FIGURE 7 .
FIGURE 7. The control block diagram of the proposed AHPF.

FIGURE 8 .
FIGURE 8.The frequency response bode plot of the AHPF.

FIGURE 9 .
FIGURE 9.The conceptual diagram of the AHPF.

FIGURE 11 .
FIGURE 11.Overall control block diagrams of the proposed circuit and control strategy.

FIGURE 12 .
FIGURE 12. Simulation waveforms of unbalanced grid voltages and the line frequency with different PLL methods under Scenario I.

FIGURE 13 .
FIGURE 13. Circuit diagrams of the T-type three-phase grid-tied inverter and the proposed SSPLL in PLECS.

FIGURE 15 .
FIGURE 15.Simulation results of different PLL strategies in full load operation under Scenario II.

FIGURE 16 .
FIGURE 16.Simulation results of different PLL strategies in full load operation under Scenario III.

FIGURE 17 .
FIGURE 17.The photo of the experimental setup.

FIGURE 18 .
FIGURE 18. Experimental results of different PLL strategies in full load operation under Scenario I.

FIGURE 19 .
FIGURE 19.Experimental results of different PLL strategies in full load operation under Scenario II.

FIGURE 20 .
FIGURE 20.Experimental results of different PLL strategies in full load operation under Scenario III.

21 .
The current THD comparison under different load conditions.(a) Scenario I. (b) Scenario II.(c) Scenario III.
(a).The execution time of the DSOGI-PLL is measured as 2116ns, as indicated in Fig.22(b).Finally, Fig.22(c)shows the execution time of proposed SSPLL, which is 1033ns.It can be confirmed that the SSPLL execution time is slightly higher than the 22.The execution time comparison of different PLL strategies.(a) The SRF-PLL.(b) The DSOGI-PLL.(c) The proposed SSPLL.

TABLE 1 .
State of the art comparison of different PLL methods under unbalanced grid voltages.

TABLE 2 .
Circuit specifications of the three-phase grid-tied inverter.

TABLE 3 .
Current THD comparison of different PLL Strategies with different load conditions under scenario I.

TABLE 4 .
Current THD comparison of different PLL Strategies with different load conditions under scenario II.

TABLE 5 .
Current THD comparison of different PLL strategies with different load conditions under scenario III.
FIGURE 14. Simulation results of different PLL strategies in full load operation under Scenario I.