Circuit-Specific and Technology-Independent Criterion for Selection of Power MOSFETs That Minimize Energy Dissipation

We investigate the impact of power MOSFET channel width on the power efficiency of a switch-mode power supply. With this analysis, we derive a circuit-specific criterion that minimizes the power dissipated by a power MOSFET, which is based on the ratio between on resistance and output capacitance of the MOSFET and is independent of its technological parameters. The effect of channel width on the power dissipation is illustrated by simulation-based analysis, which also provide an example of a published non-optimum selection of a power MOSFET and demonstrate the advantage of the newly proposed method for MOSFET selection.


I. INTRODUCTION
Switch-mode energy converters are utilized for power conversions, such as AC to DC, DC to AC, AC to AC, and DC to DC, because ideal switches do not dissipate power.Among several semiconductor implementations of power switches, the dominant device is the metal-oxide-semiconductor fieldeffect transistor (MOSFET).The resistance of a MOSFET when it acts as a switch in on mode is not zero, which results in undesired power dissipation.To minimize this conduction power loss, circuit designers tend to select MOSFETs with the smallest on resistance.However, the internal structure of MOSFETs creates parasitic capacitances, whose charging and discharging during device switching are responsible for dynamic power loss [1].As the switching frequency is increased, in response to ever increasing demand for The associate editor coordinating the review of this manuscript and approving it for publication was Sneh Saurabh .miniaturization of the power converters, the dynamic power dissipation becomes the dominant component of the total power loss.Therefore, the MOSFET with the lower on resistance is no longer the optimum selection for the highest conversion efficiency.
The recent development of SiC-based MOSFETs provides alternatives to both conventional and super-junction Si MOSFETs.SiC MOSFETs utilize the higher breakdown field of this material to offer devices for the design of circuits operating at higher switching frequencies.Several manufacturers offer families of power SiC MOSFETs with a wide range of on resistances.
Devices in a single family are fabricated by the same technology with the difference between them being the effective channel width (W ).A MOSFET with a larger W has smaller on resistance, providing smaller conduction losses, but it increases the switching losses due to its larger parasitic capacitances.Therefore, the selection of a MOSFET with the optimum channel width depends on specific circuit parameters and switching frequency.Because the circuit designers do not have information about channel width, we have developed and published an approach that selects the most suitable MOSFETs, determined by their on resistance alone [2].We have also published a figure of merit for the selection of the best family of SiC MOSFETs in terms of device reliability [3].However, the currently available SiC MOSFETs may or may not maximize the power-conversion efficiency in a specific circuit.Super-junction Si MOSFETs are competitive for many applications [4], and GaN-based high electron mobility transistors (HEMTs) are promising future devices for further increase in the switching frequency [5], [6], [7].Therefore, we propose in this paper a general approach for the selection of power switches that will reduce the power loss in a specific switch-mode power converter.This method is based on a newly derived equation, which enables circuit designers to use desired circuit parameters for the calculation of the optimum ratio between on resistance and output capacitance of a MOSFET.The circuit designers can use this information in combination with other selection criteria, such as reliability [8], short-circuit capability [9], packaging for heat dissipation [10], price, availability, and so on, to decide on the most suitable power MOSFET for their specific applications.

II. THEORETICAL DERIVATION OF NEW CRITERION
In this section, we analyze the impact of a MOSFET's channel width on its power dissipation.Applying the condition for the channel width that minimizes the power dissipation, we derive a criterion for the optimum ratio between the on resistance and output capacitance.Irrespective of the MOSFET technology, this criterion presents an approach for choosing a power MOSFET that will reduce power loss in a specific circuit.
The total power dissipation by a MOSFET in a switchmode power converter consists of two components: Conduction or static power loss due to the on resistance and switching or dynamic power loss due to the parasitic capacitances.
There are three parasitic capacitances in every MOS-FET structure: gate-drain capacitance (C GD ), gate-source capacitance (C GS ), and drain-source capacitance (C DS ).To facilitate circuit analysis, manufacturer datasheets show the equivalent output (C OSS ) and input (C ISS ) capacitances: Both C DS and C GD , as the constituting elements of C OSS , are voltage-dependent capacitances due to the voltage dependence of the depletion layer in the n-type drift region.This voltage dependence is given by [11], [12], [13], [14], [15]: where V DS is the voltage between drain and source, C OSS (0) is defined as the output capacitance at V DS = 0, V bi is the built-in voltage at the drain-to-body n-p junction, and m is the junction grading coefficient whose value is between 1/2 for the case of an abrupt junction and 1/3 for the case of a linear junction.For high drain-to-source voltages, V DS V bi ≫ 1, (3) can be simplified to It was recently shown that the power dissipation due to charging of this voltage-dependent capacitance to V DS and its discharging to 0 is given by [11]: where f is the switching frequency and γ = 1 (2 − m).Since 1 3 ≤ m ≤ 1 2, the value of γ is in the range between 0.60 and 0.67.Both C DS and C GD are proportional to the effective channel width of the MOSFET (W ): The area of the drain-tosource junction (A DS ) is proportional to W , and C DS = A DS ε s W depl where ε s is the permittivity of semiconductor and W depl is the depletion-layer width of the drain-to-source junction; likewise, the area of the gate-to-drain overlap (A GD ) is proportional to W and C GD = A GD ε ox t ox where ε ox is the permittivity of gate-oxide and t ox is the gate-oxide thickness.Therefore, (1) shows that C OSS is also proportional to W . Defining c oss/w as the output capacitance per unit of channel width, (5) becomes: Regarding the power dissipation due to charging and discharging of the input capacitance, P SW −ISS , we have shown in a recently published paper [2] that this power is independent of the channel width.It should be noted that the external gate resistance and the maximum output current of the driver IC limit the charging and discharging current of C ISS .This impacts the charging and discharging times but not the energy that is stored or dissipated by the C ISS during a switching cycle.Also, the voltage that dominates in the energy dissipation is the voltage between the drain and source terminals (V DS ), which is much higher than the gate-to-source voltage (V GS ).Consequently, the energy losses caused by V GS are negligible in comparison to the energy losses due to V DS .Apart from the output and input capacitances, the body diode can contribute to the switching losses due to its reverserecovery losses.In some circuit configurations, such as H-bridges, the reverse recovery losses can be significant.However, these losses are usually eliminated by connecting a Schottky diode in parallel with the body diode [16].Therefore, this power loss can be neglected for the purpose of selecting a MOSFET that will minimize the power dissipation.With these considerations, the total switching power dissipation can be expressed as: The conduction power dissipation is due to the on resistance, and is given by: where R ON is the on resistance, D is the duty cycle and I is the root-mean-square value of the drain current.
The R ON consists of several internal resistances in the MOSFET structure: the source contact resistance (R CS ), the source region resistance (R N + ), the channel resistance (R CH ), the accumulation resistance (R A ), the JFET resistance R JFET , the drift region resistance (R drift ), the N + substrate resistance (R SUB ), and the drain contact resistance (R DS ) [14].However, the contribution of R CH , R A , R JFET , and R drift is significantly higher than the other resistances, therefore, R ON is approximately given by [14]: In ( 9), all resulting resistances are inversely proportional to the effective channel width,W [13], [14].Defining r on−w as the specific on resistance of a MOSFET with a unit of channel width, the total on resistance is given by: From ( 8) and ( 10), the conduction power dissipation can be expressed as: Adding the switching power dissipation and the conduction power dissipation from ( 7) and ( 14), we obtain the following equation for the total power dissipation: The first derivative of ( 12) is set to zero to minimize the overall power losses with reference to W , which results in the following equation for the optimum channel width: Given that the optimum output capacitance is C OSS−opt = c oss/w W opt and the optimum R ON is R ON −opt = r on−w /W opt , ( 14) can be written in terms of C OSS−opt and R ON −opt : which leads to the following condition for the ratio between the optimum R ON and the optimum output capacitance: Equation (16) shows that the ratio of optimum R ON −opt and C OSS−opt is determined by the circuit parameters V DS , I , f , and D, since the value of the only non-circuit parameter (γ ) is in the narrow range between 0.60 and 0.67.This means that, based on the specific circuit parameters, a circuit designer can use (16) to calculate the ratio between R ON −opt and C OSS−opt

III. EXPERIMENTAL VERIFICATION
A conventional boost converter, shown in Fig. 1, is utilized to demonstrate the effect of channel width on power dissipation and to show that a MOSFET selected according to the criterion in (16) minimizes the total power dissipation.This boost converter was presented in [17] with the following circuit parameters: input DC voltage V IN = 150 V, output DC voltage V OUT = 300 V, output power P OUT = 750 W, maximum inductor current ripple iL = 10 A, and maximum voltage ripple It is important to note that the dependence of power dissipation on the channel width of a MOSFET cannot be demonstrated experimentally because the channel width of a fabricated MOSFET cannot be varied.However, this effect can be demonstrated by simulation, using adequately calibrated device model and parameters.Several studies examined how well SPICE models fit the characteristics of 4H-SiC power MOSFETs in both actual and simulated devices [18], [19].A 10 kV DMOSFET was tested and simulated using a SPICE LEVEL 1 model that had been modified to account for temperature effects [19].Tanner et al. [18] published a selection of SPICE LEVEL 3 parameters for SiC MOSFETs that provides an adequate match to measured characteristics.
In this section, we use SPICE LEVEL 3 MOSFET model, which is relatively simple, provides sufficient accuracy, and enables the model parameters to be set to match measured current-voltage and capacitance-voltage characteristics.In the first subsection, we show measured characteristics of a commercially available SiC power MOSFET (C3M0350120D) and the related extraction of SPICE parameters.In the second subsection, we show the dependence of power dissipation on the channel width to demonstrate that the minimum power dissipation corresponds to the newly proposed criterion by (16).

A. PARAMETER EXTRACTION FOR SPICE LEVEL 3 MOSFET MODEL
The SPICE parameters in MOSFET LEVEL 3 model, required for simulation of the boost converter shown in Fig. 1, are listed in Table 1.
SPICE uses these parameters in the following equations for the current-voltage characteristics: For In ( 17)- (20), q is the electron charge, I D is the drain current, n s is a coefficient analogous to the emission coefficient n of diodes, V TS is the threshold voltage, ε ox is the permittivity of gate oxide, V t is the thermal voltage, V GS is the gateto-source voltage, and V DS is the drain-to-source voltage.
Power MOSFETs operate as switches, and the on mode of the device relates to high V GS and small V DS , whereas the off mode relates to sub-threshold V GS (small current).The selected parameters correspond to the transfer characteristic for small V DS values.The equation for sub-threshold current (I D for V GS < V TS ) takes into consideration the gradual and nonlinear rise in drain current with gate voltage.The default value of the parameter THETA in SPICE is THETA = 0, which can be used as the initial value for the nonlinear fitting.The parameter NFS, on the other hand, can be determined to fit the sub-threshold current of the transfer characteristic.In the case of SiC power MOSFETs, a high NFS value corresponds to a high density of near interface-traps (NITs), causing the slow drain-current increase with gate voltage [18].It is possible to get the MOSFET LEVEL 3 parameters by nonlinear fitting to experimental data.The transfer characteristic, shown by the solid line in Fig. 2, was measured using Agilent B1505A power device analyzer.The gate-oxide thickness was measured using Fowler-Nordheim tunneling method [21], and the value is Tox= 40 nm.After the nonlinear fitting, the parameter values are entered into SPICE and the simulated transfer characteristic for is compared with the experimental results shown in Fig. 2.
The channel width and length, W and L, are technological parameters that are designed by the manufacturers and are usually not disclosed.However, the ratio of these parameters, W L, can determined from the measured slope of the transfer characteristic.By assuming the typical channel length of L = 2 µm, the effective channel width for this MOSFET is The MOSFET LEVEL 3 model additionally incorporates dynamic parameters, which consist of voltage independent gate-to-drain and gate-to-source overlap capacitances, Cgdo and Cgso respectively, which are defined as capacitances per unit channel-width.It can be observed from datasheet that the C GS and C GD are essentially constant for most of the drain-voltage range.The energy dissipated by constant capacitance in SPICE is close to energy dissipated by the voltage-dependent capacitance because the capacitance change is limited to very small voltages.The data for C GS and C GD is taken from datasheet and subsequently divided by the effective channelwidth to obtain the values of Cgdo and Cgso. Figure 3 shows the extracted capacitance data from datasheet for SiC MOSFET.
Also, a diode model for the MOSFET P-N junction is also included in the MOSFET LEVEL 3 model [20], [22], and it may be used to simulate the non-linear C DS for power MOSFETs with the SPICE parameters C jo , PB, and M j .SPICE uses these parameters in the following equation: These parameters can also be determined by non-linear fitting to the measured characteristic shown in Fig. 4 by the solid line.The initial value of C jo should be the C DS value from the datasheet at V DS = 0 V.The initial value for M j can be set to 0.5, and the initial value for PB can be set to 2 V.The result of the non-linear fitting and the obtained values of these SPICE parameters are shown in Fig. 4.

B. RESULTS
Based on the circuit parameters of the specific boost converter, shown in Fig. 1, the optimum This optimum value is 30.8 times smaller than the R ON −opt C OSS−opt value of the SiC power MOSFET used in this analysis.This result shows that the on resistance of the MOSFET is √ 30.8 = 5.5 times larger and its capacitance is 5.55 times smaller than the optimum value, which means that a MOSFET with 5.5 larger effective channel width is required to minimize the power dissipation.This means a reduction of the on resistance from the actual 350 m to around 60 m and an increase in the output capacitance at V DS = 300 V from the actual 26.4 pF to around 150 pF.
This conclusion is confirmed by the simulation results shown by the symbols in Fig. 5, which are in a good agreement with the theoretical equations (lines): (6) for the switching loss due to the output capacitance (P SW −OSS ), ( 8) for the conduction loss (P CON ), and ( 12) for the sum of these two losses (P SW −OSS + P CON = P TOT − P SW −ISS ).As expected, the results shown in Fig. 5 illustrate that the conduction loss drops as the channel width is increased, due to proportional reduction in on resistance [( 8) and ( 10)], whereas the switching loss increases proportionally with the channel width, due to the proportional increase in the output capacitance [( 5) and ( 6)].The minimum power dissipation corresponds to the channel-width scaling factor of 5.5, as determined from the newly proposed criterion.
Figure 5 also shows that the dependence of the total power dissipation on the channel-width scaling factor does not exhibit a sharp minimum at the value of 5.5.The implication 116476 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.12) (the black line) demonstrate that C3M0350120D does not minimize the power dissipation.The selected MOSFET corresponds to the channel-width scaling factor of 1, whereas the minimum power dissipation is for a MOSFET with 5.5 times larger channel width (the scaling factor of around 5.5).The channel-width independent power dissipation is is that a channel-width scaling factor as small as 4 is also acceptable, but this value is still much larger than the channelwidth scaling factor of 1 for the MOSFET selected without the application of the newly proposed criterion.The practical implication is that either a larger MOSFET or four MOSFETs operating in parallel is required to minimize the power dissipation.

IV. APPLICATION OF NEW CRITERION: EXAMPLE
The MOSFET used by the authors of ref. [17] was IRFP450, and we will show in this section that this MOSFET does not minimize the power dissipation.To minimize the power dissipation, we need a MOSFET with R ON −opt C OSS−opt according to the criterion in (16).Based on the circuit parameters of the specific boost converter, shown in Fig. 1, the optimum R ON −opt C OSS−opt is: The MOSFET used in [17] is IRFP450, which also comes with a SPICE model provided by the manufacturer.The R ON of this MOSFET is 0.4 and C OSS in the SPICE model is 3.57 nF.Hence, R ON C OSS = 0.112 × 10 9 /F, which is much smaller than the optimum value of 1.6 × 10 9 /F obtained by the criterion in (16).This means that the choice of the relatively small R ON resulted in a too large C OSS , and a power loss that will be higher than the minimum power dissipation due the switching losses by the output capacitance.The simulation results shown in Fig. 6 illustrates this scenario.The good agreement between the simulation results (the symbols in Fig. 6) and ( 12) (the black line in Fig. 6) confirms that the minimum power dissipation corresponds to a smaller channel width that is FIGURE The simulation results (symbols) and ( 12) (the black line) demonstrate that IRFP450, which is the MOSFET selected in ref. [16] for the circuit shown in Fig. 1, does not minimize the power dissipation.The selected MOSFET corresponds to the channel-width scaling factor of 1, whereas the minimum power dissipation is for a MOSFET with three times smaller channel width (the scaling factor of around 0.3).The channel-width independent power dissipation is P SW −ISS = 16 W. 0.3 times the channel width of IRFP450.The larger than optimum channel width and the corresponding smaller R ON reduce the conduction losses, but the larger C OSS due to the larger channel width causes a much larger dynamic power dissipation.This confirms that the smaller R ON C OSS ratio than the derived optimum in (16) means that R ON is too small and C OSS is too large.
Searching through datasheets of available MOSFETs, we found a MOSFET with on resistance of 95m and output capacitance at V DS = 300 V of 58 pF, which has the ratio R ON −opt C OSS−opt = 1.6 × 10 9 /F.This MOSFET is in the family of super-junction MOSFETs fabricated by Rohm, and its part number is R6035VNX.The channel width of this MOSFET is not provided by the manufacturer, but the criterion given by ( 17) should guarantee that this MOSFET minimizes the power dissipation.
The manufacturer provides LTSPICE model for R6035VNX to enable circuit designers to design their circuit using SPICE-based simulations.To demonstrate that the selected MOSFET minimizes the power dissipation, we performed simulations with scaled channel width above its nominal value (scaling factors larger than 1) and below its nominal value (scaling factors smaller than 1).We were able to do these simulations because the parameters of the provided MOSFET model could be changed in the ''SPICE model editor.''The provided LTSPICE model used the transconductance parameter, KP, rather than the channel width, so we scaled KP knowing that: In (24), µ n is the channel-carrier mobility, C ox is the gateoxide capacitance per unit area, and L is the channel length.
As discussed in Section II, the R ON of different MOSFETs (parts) in a family of MOSFETs is adjusted by varying the channel width, W .This means that µ n , C ox , and L, are constant in a group of MOSFETs fabricated with similar technology.Therefore, scaling KP values above and below its nominal value was equivalent to scaling the channel width by the same factor.Figure 7 shows that the minimum power dissipation is for the nominal channel width, corresponding to the channelwidth scaling factor of 1.This verifies that a MOSFET can be chosen using (16) to reduce power dissipation, even when the channel-width values are not provided by the device manufacturers.

V. CONCLUSION
Power MOSFETs with larger effective channel widths (a large number of cells) exhibit small on resistances, but they may not provide the minimum power dissipation because the increased output capacitances result in increased dynamic power dissipation.There is an optimum channel width that minimizes power dissipation, but this parameter is not available to circuit designers.In this paper, we have derived a general criterion for the ratio of on resistance and output capacitance, R ON −opt /C OSS−opt , given by ( 16).The numerical value of the optimum R ON −opt /C OSS−opt ratio depends on the circuit parameters (voltage, current, duty cycle, and frequency).Given that the onresistance and the output capacitance are provided by the MOSFET manufacturers in the device datasheets, the circuit designers can search for a MOSFET that satisfies the optimum R ON −opt /C OSS−opt ratio, knowing that this will minimize the power dissipation irrespective of the specific technology, manufacturer, and device family.The proposed criterion is verified by using SiC MOSFET LEVEL 3 parameters through nonlinear fitting to experimental data and circuit simulation using LTSPICE MOSFET models provided by the device manufacturers.An example of a published typical boost converter was used to illustrate the power-minimization effect that can be achieved by applying the proposed criterion.

FIGURE 1 .
FIGURE 1.A standard boost converter circuit.

FIGURE 2 .
FIGURE 2. Transfer characteristics of SiC power MOSFET: measurements (line) and simulation with the extracted parameters (circles).

FIGURE 4 .
FIGURE 4. C DS -V DS characteristic of SiC power MOSFET: measurements (line) and (21) with the extracted parameters (circles).

FIGURE 5 .
FIGURE 5.The simulation results (symbols) and (12) (the black line) demonstrate that C3M0350120D does not minimize the power dissipation.The selected MOSFET corresponds to the channel-width scaling factor of 1, whereas the minimum power dissipation is for a MOSFET with 5.5 times larger channel width (the scaling factor of around 5.5).The channel-width independent power dissipation is P SW −ISS = 0.24 W.

FIGURE 7 .
FIGURE 7. The simulation results (symbols) and (12) (the black line) demonstrate that the minimum power dissipation is for the channel-width scaling factor of 1, which corresponds to the nominal channel width of the selected MOSFET (R6035VNX).The channel-width independent power dissipation is P SW −ISS = 25.2W.

TABLE 1 .
Static and dynamic parameters for spice level 3 model.