FPGA Implementation of Variable Step Power Inversion Array for BeiDou Receiver

Given the susceptibility of satellite signals to intentional or unintentional interference; it is imperative to incorporate hardware-based navigation anti-jamming algorithms. Currently, spatial domain filtering is widely applied. While numerous variable step size (VSS) algorithms were used to improve the performance, most of these are either computationally complex or depend on many parameters that are hard to tune manually. Some algorithms might improve one index but worsen overall performance, making them unreliable in practical scenarios. To address these challenges, we propose a novel variable step power inversion (PI) that involves just one adaptive parameter. By establishing a new non-linear function model between step size and system output, the parameter can be adapted based on the output. Meanwhile, a variable step PI that can be easily implemented by field programmable gate array (FPGA) is proposed, thereby achieving a balance between accuracy and iteration speed. The proposed algorithm can converge within 10 iterations, effectively suppressing individual interference below −300dB. In comparison to existing algorithms, the proposed algorithm is characterized by swift convergence, high convergence accuracy, low complexity, and robust anti-jamming capabilities. Finally, FPGA hardware testing is conducted, and the experimental and simulation results are in good agreement, affirming anti-jamming capabilities.


I. INTRODUCTION
Due to the considerable distance between the navigation satellite and the Earth, the signal reaching the ground is very weak [1] (for instance, the anticipated maximum value of the GPS L1 signal does not surpass −153dBW).These signals become submerged within the intricate electromagnetic surroundings on the surface, resulting in an extremely low signal-to-noise ratio (SNR).Therefore, the implementation of effective anti-jamming technology becomes a crucial assurance for the operation of satellite navigation system [2].
Suppression jamming is prevalent in warfare due to its favorable cost-effectiveness ratio and straightforward implementation.During the Russo-Ukrainian conflict, Russia employed an electronic warfare system to execute high-power suppression jamming, failing Ukraine's GPS.Thus, recent research has focused on not only the performance The associate editor coordinating the review of this manuscript and approving it for publication was Yunlong Cai .measures of the algorithm but also on FPGA implementations [3], [4], [5].
Due to the motion of navigation satellites, it is hard to obtain reliable and useful signal prior information for anti-interference processing.Receivers often need to receive navigation signals from multiple satellites, and both least mean square (LMS) and direct matrix inversion (DMI) algorithm need useful signals to align the beam, which proved to be difficult.In contrast, PI algorithm does not rely on prior information regarding useful signals, nor does it require beam alignment with them, which makes it suitable for scenarios involving simultaneous reception of navigation signals from multiple satellites.
However, PI algorithm using fixed step size must compromise between fast convergence rate and low level of steady-state MSE.Scholars have proposed many algorithms to reduce the steady-state error with computational complexity [6], [7], [8], [9], [10], [11], [12], [13].Mayyas [6] proposed a VSS selective partial update LMS algorithm, to reduce computational complexity by updating only a fraction of the adaptive filter coefficients during each iteration.Hongmei and Wangang [7] proposed a VSS LMS algorithm and analyzed the influences of key parameters on the adaptive filtering algorithms.Jiang et al. [8] proposed an adaptive step-size approach, which utilized an improved particle swarm optimization (IPSO) algorithm to determine the key parameters for setting specific step-size adjustment strategies, but the algorithm complexity was large, which is not suitable for the RF front-end.Kumar et al. [9] introduced a family of VSS-LMS algorithms that utilize logarithmic, hyperbolic, and sigmoid cost functions, resulting in robust performance.
The conventional PI algorithm solves weights iteratively, avoiding matrix inversion and thus reducing computation.However, its convergence speed is relatively slow, and it cannot guarantee simultaneous achievement of optimal convergence speed and steady-state error.To address these limitations, we propose a VSS-PI with adaptive parameter adjustment and another VSS-PI that can be easily implemented by FPGA.Compared to existing VSS algorithms, the enhanced approach achieves faster convergence speed and lower steady-state errors without introducing additional complexity.Therefore, it can meet the requirements of highly dynamic navigation scenarios such as missile-borne and space-borne.

II. TRADITIONAL PI ALGORITHM
The PI algorithm adopts the array output as the error signal, aiming to minimize the MSE by optimizing the array output power.For hardware implementation, the Linearly Constrained Minimum Variance (LCMV) criterion is commonly employed.In this approach, the first input serves as the reference signal, while the weight remains unchanged.The weights of other array elements are adjusted to nullify interference and align with the opposite beam's directional pattern, thereby minimizing the output power.FIGURE 1 shows a PI adaptive processor with M array elements.
Solving the optimal weight vector is equivalent to solving the optimization problem where R xx represents the correlation matrices of the input signals.The weight vector w is M-dimensional while s is the constraint vector, s = [1, 0, . . ., 0] T .The weight vector optimal solution can be expressed as It is practical not feasible to estimate R xx using instantaneous sampling values, considering the resource constraints of FPGA.Therefore, PI is typically implemented using random gradient descent, allowing the weight to gradually approach the optimal value.Where R xx is estimated at nth snapshot as x(n)x H (n). The weight update rule is given by where, µ is the fixed step size, with the convergence condition, 0 < µ ≤ 1 tr(R xx ) .I is the identity matrix.

III. IMPROVED PI ALGORITHM A. NORMALIZED PI ALGORITHM
The M -dimensional input vector to the adaptive filter is given by , where the superscript T means transpose.Starting from the NLMS weight update recursion [14]: where e(n) = d(n) − x T (n)w(n), with d(n) and e(n) are the desired signal and the error signal, respectively.As the PI has no reference signal, with y(n) = e(n), the normalized PI (NPI) weight update recursion is In practice, it is necessary to regularize adaptive algorithms to prevent divisions by small numbers.This entails adding a positive constant to the denominator of the step size [15].In the navigation anti-jamming scenario, the step size could be given by where ζ is in the same order of magnitude as the average power of the input signal during a stationary period, to satisfy the sufficient condition for convergence of weight vector and achieve better performance.NPI not only converges even in the presence of changing interference power but also accelerates the convergence and deepens the null.

B. IMPROVED VSS-NPI ALGORITHM
In previous studies [2], [7], [8], Most improvement methods of VSS use hyperbolic tangent, exponential, or other functions to express the definite relationship between error signal and step size.Like (7) or (8): Constant parameters α, β, a, b, and m determine the shape of the curve to affect algorithm performance.Where the values of these parameters are determined by using multiple simulations.The algorithm adjusting the step size with ( 8) is called E-NPI, for the relation between the step size and error e(n) is a nonlinear function model based on the exponential function.In practical applications, different input data require a lot of simulation to get the ideal parameter, which affects the real-time performance of the algorithm.Moreover, simulation results indicate that the algorithm becomes unstable when the step change rate is too large, leading to uncertainty with the introduction of these adaptive parameters.Literature [7] introduced two adaptive parameters.However, it also defined another constant that needs to be selected to mitigate the impact of rapid fluctuations in e(n) on these parameters.This can result in weight oscillation divergence and increased complexity.
To address these issues, a modified version of E-NPI, called APE-NPI (E-NPI based on adaptive parameter), is proposed.APE-NPI allows for adaptive step size updates without the need to adjust any parameters, resulting in low computational complexity.The gain of the normalized power µ NPI (n) is determined using a deformed Sigmoid function, and the step is defined as where α(n) is the adaptive parameter adapted based on the output |y(n)| and |y(n − 1)|.When |y(n)| > |y(n − 1)|, it indicates that the interference increases and the null is misaligned with the interference.In such case, the step size should increase to expedite the convergence rate.Conversely, when the step size needs to be steadily reduced, it allows the weight to approach a steady state.Thus, α(n) can be derived as In this paper, we propose an improvement in the step size approach that gains different values based on the amplitudes of the in-phase error signal, which not only considers the VSS design principle to avoid weight oscillation but also reduces algorithm complexity, called PL-NPI (NPI based on piecewise linear function).The hardware design can incorporate a cascade switch, and convergence of the algorithm can be ensured by simply judging the threshold of the output error signal in the same phase path, without requiring the module of the complex signal.The step size can be expressed as As shown in FIGURE 2, the piecewise function formed by multiplying constants in each segment can be fitted with a Sigmoid function, which conforms to the design principle of VSS.The fitting curve of the piecewise function formed by each segment constant can be expressed as where A=1.463, B=−0.2609,C=0.05067, confidence boundary is 95%, confidence interval is (1.451, 1.476), (−0.2735, −0.2483), (0.04692, 0.05441) respectively.

A. SIGNAL MODEL
Consider N narrowband source signals from the directions θ 0 , θ 1 , • • • , θ N −1 , impinge on uniform circuit array (UCA) of 4 omnidirectional elements (N < 4) apart by half-wavelength, without regard to the mutual coupling effect.The received signal x(n) ∈ C M ×1 at nth snapshot is expressed by where s 0 (n) is the navigation signal, which is generated in B3I format, with the center frequency at 1268.52 MHz and 109392 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

2) ANALYSIS OF WEIGHT ACCURACY
In 200 simulations, it was observed that the weights of NPI, APE-NPI, and PL-NPI all converge and stabilize within 10 iterations, and E-NPI reaches 96.5% of the reference weight after 10 iterations (considering NPI zero depth exceeds −300dB, it is taken as the reference), and 97.7% of the reference weight after 30 iterations.The reference weight approaches but does not reach within 300 iterations.APE-NPI reaches 99.6% of the reference weight after 10 iterations and keeps approaching but not reaching the reference weight   within 300 iterations, but the difference is smaller than that of E-NPI.FIGURE 5 shows how the ratios of weights of E-NPI, APE-NPI, and PL-NPI to the correct weight change with the number of iterations.Ratio1, ratio2, and ratioa3 indicate the ratio of E-NPI, APE-NPI, and PL-NPI to the correct weight, Therefore, PL-NPI can approximate the reference weight faster than the other three algorithms.

3) ANALYSIS OF OUTPUT STEADY-STATE ERROR
In 200 simulations, the weights of NPI, APE-NPI, and PL-NPI and stabilize within 10 iterations, while the steady-state error (SSE) of E-NPI always exhibits a gradually decreasing fluctuation of 10 −1 orders of within 300 iterations.At the 5th iteration, the modulus of error of APE-NPI, and is −1 , which are 100%, 71.1%, and 188.1% of NPI respectively.At the 10th iteration, the error modulus of E-NPI is still 10 −1 , the error of PL-NPI and NPI both reach 10 −8 , and the error modulus of APE-NPI fluctuates within 10 −1 .As the number of iterations increases, the fluctuation of APE-NPI gradually decreases to 10 −3 orders of magnitude.FIGURE 6 shows how the differences in SSE of E-NPI, APE-NPI, and PL-NPI to NPI change with the number of 109394 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Difference1, difference2, and difference3 indicate the differences of E-NPI, APE-NPI, and PL-NPI to NPI, respectively.Therefore, PL-NPI can reduce the interference signal power more effectively than the other three algorithms.

4) ANALYSIS OF STEP SIZE
The step value dynamic range for all four algorithms falls within [0, 1 × 10 −5 ], providing a consistent condition for discussing convergence performance.Once the weights have converged, the step sizes of PL-NPI and E-NPI are equal, differing only when the interference suddenly changes.When the INR of the input signal is large, the step size vibration amplitude is large, and the mathematical expectation is small, and vice versa.The change of step size relative error signal of E-NPI and APE-NPI can be intuitively considered as an exponential function.As the weights approach convergence, the step of E-NPI and APE-NPI fluctuate around 0 within magnitude of 10 −9 and 10 −8 , respectively.

5) ANALYSIS OF COMPUTATIONAL COMPLEXITY
The computational cost is evaluated by calculating the number of complex multiplications per iteration and compared with NPI and E-NPI algorithms.The results are summarized in TABLE 1.All algorithms involve the computations for weight vector and array pattern.The total computational cost of PL-NPI per iteration is O((3M + 4)+M ), where the computational cost for calculating the weight vector is O((3M + 4), and for the array pattern is O(M ), with representing the angular range to be scanned.It is revealed that the PL-NPI has a lower computational cost compared to E-NPI and APE-NPI.Although the computational cost of PL-NPI is slightly higher than NPI, PL-NPI performs better.

V. DESIGN AND IMPLEMENTATION A. OVERALL DESIGN
The proposed design of PL-NPI is implemented on a Kintex-7 xc7k325t-2ffg676 FPGA chip.Fixed point words, with 20 data signed bits are used for inputs x(n), weights w(n) and output y(n).The hardware design language Verilog is used for the design and synthesis in the Vivado.The optimized implementation is run with the speed mode as the optimization goal.
The implementation sequence of the main functions on the hardware platform is shown in FIGURE 7. The signal is received by the active four-array antenna, transmitted to the RF transceiver AD9361 through four channels, amplified, shaper filtered, and digitized, then down-converted to the baseband and sent to the anti-interference module of the FPGA.FPGA provides DSP with pseudo-range, Doppler, carrier phase and navigation message data.According to the approximate position of the satellite and receiver, DSP calculates the approximate elevation and azimuth angle of the satellite, and provides the capture information for the FPGA to assist the rapid capture of the satellite signal.On the user's computer, BDS satellite distribution, data session view, and map tracking can be viewed through the upper computer software.The experimental scene is shown in FIGURE 8.

B. ALGORITHM BLOCK IMPLEMENTATION
PL-NPI algorithm block is divided into three parts: normalized power variable step module, piecewise function adjustment step module, and PI algorithm module.
Input four channels of signed 20bit I-Q data, and enter the normalized power variable step module and PI algorithm module simultaneously.The normalized power variable step module calculates the instantaneous power of the I and Q channels in parallel, and updates the step size once every clock cycle.Then the normalized step size enters the step size adjustment module of the piecewise function.The multiplexer and comparator realize the adaptive multiplication of the step by different gains, according to the amplitude of the output signal from the in-phase.PI algorithm module firstly computes x(n)y(n) in parallel.After the product is multiplied by the variable step size, the new weight value is obtained by calculating w(n) − 2µ(n)x(n)y(n).The initial value of the weight vector is set to [1, 0, 0, 0], which is constantly updated in the iteration.The weight vector is multiplied by the input signal vector, then accumulated, and output after taking the high level.The register-level schematic of PL-NPI algorithm is shown in FIGURE 9.The resource utilizations for the scheme are shown in TABLE 2.

C. ALGORITHM BLOCK TESTING
To better observe the anti-interference performance, the input signal is set to 80 snapshots, with the interference signal following the same change as described in IV.As shown in FIGURE 10, the top row shows software simulation results, proceeding from left to right: the convergence of in-phase and orthogonal components of the second to fourth channel weights, the amplitude fluctuations of in-phase and orthogonal components of the output signal, and the step changes.The second row corresponds to the FPGA simulation tests, and the step length is twice of that in software simulation due to the different calculation order.The results exhibit that the error of the weight convergence implemented by hardware is less than 2% compared to the full precision case in software.

VI. CONCLUSION
This paper presents two novel algorithms: a variable step PI algorithm based on the logarithmic function of the error signal change, and a hardware-friendly piecewise linear function variable step PI algorithm.Comparative evaluations demonstrate that both improved algorithms outperform existing approaches in terms of convergence speed, convergence accuracy, and complexity.Notably, the PL-NPI achieves convergence within 10 iterations and exhibit exceptional suppression of single wideband interference, exceeding −300dB, and this level of suppression remains independent of the input signal power.The piecewise linear function-based variable step length method is particularly advantageous for hardware implementation.Experimental results from FPGA hardware testing corroborate the simulation findings, affirming the hardware system's robust anti-jamming capabilities.

FIGURE 1 .
FIGURE 1. Structure of the traditional PI algorithm.

B
. PERFORMANCE EVALUATION In this section, the performance of the proposed algorithm is evaluated by the numerical simulations in terms of array pattern, weight accuracy, output steady-state error and computational complexity, and compared with NPI, E-NPI, APE-NPI and PL-NPI algorithm.The adaptive array pattern is determined by one Monte Carlo simulation, whereas the weight accuracy and output steady-state error are calculated by an average of 200 independent Monte Carlo simulations.The simulation parameters used for NPI and E-NPI are C = 1 × 10 5 , a=2, b=0.05, and m=2.

FIGURE
FIGURE Software and hardware simulation comparison.

TABLE 2 .
The resource utilizations for the scheme.