Double Node Upset Immune RHBD-14T SRAM Cell for Space and Satellite Applications

Deep sub-micron memory devices play a crucial role in space electronic applications due to their susceptibility to single-event upset and double-node upset types of soft errors. When a charged particle from space hit a scaled memory circuit, the critical charge of sensitive storage nodes drops, and a node upset happens across the storage nodes. This paper describes the soft error immune RHBD-14T SRAM cell (SEI-14T) for space and satellite applications. The SEI-14T memory cell consists of two latch circuits coupled in a self-recovering, state-restoring feedback manner. In addition, SEI-14T memory cell mitigate single event upset (SEU) in all sensitive nodes and a portion of double node upset. By considering the sensitive node area separation approach, the remaining upset pairs were recovered. To show the relative performance of the SEI-14T, the state-of-the-art of other radiation-resistant memory cells, such as the Quatro-10T, RHM-12T, RHD-12T, RSP-14T, RHPD-12T, RH-14T, EDP-12T, and QCCS-12T are considered. Compared to all other mentioned memory cells, SEI-14T has superior write stability, and greater read stability than all other memory cells. Furthermore, at 0.8 V supply voltage, SEI-14T minimizes 23%, 12.28% and 20.82% of read access time, write access time and static power consumption respectively compared to existing memory cells. Moreover, the critical charge of SEI-14T was $8.85\times / 6.56\times / 3.4\times / 5.75\times / 2.54\times / 2.47\times / 1.81\times / 1.63\times / 1.44\times $ times larger than 6T-SRAM/ Quatro-10T/ RHM-12T/ RHD-12T/ RSP-14T/ RHPD-12T/ RH-14T/ EDP-12T/ QCCS-12T memory cells.


I. INTRODUCTION
The several space agencies in charge of space exploration have created man-made spacecraft and shuttles made up of hundreds of electrical components and circuits. However, our cosmos is rife with radiation. Beyond the earth's atmosphere, radiation is referred to as ''space radiation''. Space radiation includes high-velocity particles and electromagnetic waves. This radiation causes several issues with the stability and reliability of electronic devices. Even a low-intensity alpha particle hit causes electronic devices to malfunction [1]. Single event effects (SEE) played a significant role among the many sorts of soft errors throughout the half of the decade. The impact of radiation on integrated circuits is mainly related to scaling the device dimensions [2].
The associate editor coordinating the review of this manuscript and approving it for publication was Chaitanya U. Kshirsagar.
Binder et al. investigated single event upset, a significant type of soft error, following the finding of single event effects (SEE) in space and on earth [3], [4], [5]. As seen in Fig. 1, a single high-energy radiation particle strike initiates an ion track inside the memory device and generates a transient charge pulse due to drift and diffusion. This causes a disruption or bit flip in memory devices [6]. When a radiation particle hits a memory device, the energy injected or created is more than the critical charge, causing a malfunction in the memory device [6]. Author Kerns et al. identify various methods to get resilience from SEU, such as device, circuit, and system-level approaches [2]. According to a recent literature review [7] on radiation-hardened memory cells, the majority of radiation-hardened memory cells come from the circuit-level method, i.e., radiation-hardened-bydesign (RHBD), because of their reliability and ease of verification.
In contrast, SRAM plays a crucial role in on-chip cache memory due to its quicker data access, high stability, and low power consumption [8]. However, these SRAM memories consume more significant than 95% of an SoC's total area [9]. To maintain the area of the SoC, designers reduce the size of the transistors and the supply voltage [10]. According to [11] and [12], reducing VDD and transistor dimension degrade the storage node's charge and the memory cell's stability. Further, it is highly vulnerable to radiation particles. Therefore, several authors have proposed various RHBD SRAM circuits to be resistant to high-energy particle strikes, despite the fact that there is a trade-off between the probability of soft error rate and performance of the memory cell [7]. This paper follows as Section II describes the state-ofthe-art of reliable RHBD SRAM memory cells. Section III includes proposed SEI-14T memory cell fundamental working and soft error recovery analysis, and Section IV consists of performance metrics simulations and discussions. Finally, Section V conclusion of the paper.

II. STATE-OF-THE-ART OF RELIABLE RHBD SRAM MEMORY CELLS
Conventional 6T SRAM is connected in a cross-coupled, positive-feedback configuration. When a high-energy radiation particle is induced on one of the sensitive nodes of the memory cell, then the stored bit is flipped because the critical charge exceeds the injected charge [7]. Due to the cross-coupled connection of conventional SRAM, this problem may also impact the other storage nodes. Therefore, typical SRAM is not a memory cell resistant to mild errors, this is experimentally proven in [13] and [14]. After conventional SRAM cell, numerous authors have suggested radiation-resistant memory cells such as Quatro-10T, RHM-12T, RHD-12T, RSP-14T, RHPD-12T, RH-14T, EDP-12T, and QCCS-12T.

A. QUATRO-10T
In this design, the author incorporated a negative feedback state restoration latch to the standard SRAM cell to recover the lost data due to radiation particle struck, as shown in Fig. 2(a). The best part of the design is its read stability under PVT variations [15]. The primary issue with this architecture is that it cannot recover lost data if the memory cell is set to logic 0. Additionally, the critical charge is lower than that of the remaining memory cells.

B. RHM-12T
In this design, the author changed the Quatro-10T by adding two PMOS transistors stacked on top of each other, as depicted in Fig. 2(b). Static power consumption and read access time of the memory cell are minimized by stacking PMOS transistors, as described in [16]. The primary issue with this design is the time required to access the write mode when operating in temperatures ranging from −45 • C to 120 • C. In addition, the critical charge is reduced at lower supply voltages.

C. RHD-12T
This design is also an enhanced version of the Quatro-10T design, as illustrated in Fig. 2(c). The best part of this design is its recovery procedure [17]. The primary issue with this design is the write access delay during PVT variations. Furthermore, the critical charge is lower at the worst-case supply voltage.

D. RSP-14T
This design improves the RHD-12T cell by including P7 and P8 transistors, as seen in Fig. 2(d). The best line of action is to increase its write ability at lower supply voltages [18]. Furthermore, all the sensitive nodes of the memory cell have been restored, and this design only recovers the lost bit when the memory cell is stored at logic 1. Moreover, the failure probability rises as more charge is shared across sensitive node pairs.

E. RHPD-12T
The RHPD-12T structure is shown in Fig. 2(e) and it consist of two additional access transistors (N9, N10) in this design to boost the memory cell write capabilities. The design's best feature is that its read stability and critical charge are enhanced over earlier hardened memory cells [19]. The problem with this memory cell is its write access time under PVT analysis.

F. RH-14T
Figure 2(f) shows schematic diagram of RH-14T SRAM cell and it includes stacked PMOS transistors P1 and P2 and added VOLUME 11, 2023 96257 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. P. K. Mukku, R. Lorenzo: DNU Immune RHBD-14T SRAM Cell for Space and Satellite Applications an inverter pair P7 and N5 to make five storage nodes. The design's most robust feature is its ability to hold and write in the worst-case corners analysis [20]. Furthermore, the critical charge is enhanced as compared to existing memory cells.
The key issue with this design is the high failure rate when charge sharing is used across sensitive node pairs.

G. EDP-12T
This design improves on the RSP-14T by using N5 and N6 transistors, as illustrated in Fig. 2(g). This design's greatest feature is its shorter write access time under PVT analysis [21]. The issue with this design is that it has poor read and write stability under worst-case corner and temperature analysis.

H. QCCS-12T
QCCS-12T is an enhanced dual interlocked storage cell design (DICE) [22]. Fig. 2(h) shows a four inverter pairs are cross-coupled with each other. This design's most robust feature is its minimized access time at PVT analysis and an enhanced critical charge compared to the other hardened memory cells [23], [24]. The only issue in this design is the soft error recovery failure at 70 fC charge shared among sensitive node pairs.

III. SEI-14T MEMORY CELL WORKING AND SOFT ERROR RECOVERY ANALYSIS
A resilient, soft error-immune RHBD-14T (SEI-14T) memory cell is offered as a solution to the problems mentioned earlier. The following are the technical specifications for SEI-14T: 1) SEI-14T exhibits better read stability and write ability even at worst case corner and temperature analysis. 2) SEI-14T memory cell have lower write access time and static power consumption under the PVT analysis.
3) The proposed SEI-14T achieves higher effective critical charge even at worst case corner and supply voltage. 4) SEI-14T completely immune to soft error at all the senstive nodes. 5) SEI-14T also immune to double node upset across the sensitive node pairs by considering sensitive area separation method. The concept and layout of the proposed soft error immune RHBD-14T (SEI-14T) memory cell are depicted in Fig. 3 and 4, respectively. As seen in Fig. 3, SEI-14T memory cell include two NMOS (N7, N8) and two PMOS (P5, P6) access transistors to enhance the memory cell's write capability. In addition, two sets of latches are linked in a state restoration feedback fashion. Also, the NMOS transistors were stacked so that the read current through the pull-down and access transistors would be as small as possible. Bit lines are linked to access transistors to access the data from the storage nodes. We can read or write data from the memory cell when both word lines (WL, WWL) are enabled. SEI-14T has four storage nodes: Q, QB, S0, and S1. Q and QB are the primary storage nodes, and S0 and S1 are the secondary storage nodes. When a high-energy radiation particle strikes a primary storage node, it restores the state at the secondary storage node, and vice-versa. If the memory cell has logic 1, then the storage nodes Q, S1, and QB, S0 have logic 1 and 0, respectively. We provide fundamental functioning and soft error analysis by considering this logic state.
96258 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.   During hold operation, both the word lines (WL and WWL) are disabled. Hence the access transistors are turned off. Furthermore, bitlines are linked to the supply voltage (VDD) to reduce transistor wakeup time [21]. As a result, transistors N1, N3, N5, P1 and P4 are ON, while the remaining transistors are OFF. Therefore, memory stores its initial data.

2) READ ANALYSIS
To read the data from the storage nodes, both bit lines (BL, BLB) serve as output lines to retrieve data from the storage nodes. The word line must be at supply voltage while the bit lines are connected to the precharge network. If logic 1 is stored in a memory cell, then the N1, N3, and N5 transistors are turned ON. As illustrated in Fig. 5(a) [25], the BLB value discharged via the N1, N3, N7, P5 and N5 transistors. This process will continue until the N2 and N4 transistors switched ON. As soon as a voltage differential of at least 50 mV is detected between the bit lines, the sense amplifier becomes active and supplies the relevant data [16]. Figure 6 shows the proposed SEI-14T memory cell read-0 and read-1 transient analysis when wordline is enable.

3) WRITE ANALYSIS
Both bit lines act as input to the memory cell to write the stored data in the memory cell. If we wish to write the stored data to logic 0 from 1 then we need to connect BL and BLB to GND and supply voltage, respectively. This results in storage node Q discharges via N8 and P6 transistors and QB charges via P5 and N7 transistors. Further, N2 and N4 transistors are turned ON, and Q writes data to logic 0. This is shown in Fig. 5(b) by considering the [25]. The primary storage node's voltage difference is increased by the cross-coupled N3 and N4 transistors [21], [26]. Figure 6 depicts the write-0 and write-1 transient analysis of the proposed SEI-14T memory cell with respect to the bitline voltages.

B. SOFT ERROR RECOVERY ANALYSIS
This subsection explains how the soft error triggers the sensitive nodes of the proposed SEI-14T memory cell. Any circuit VOLUME 11, 2023 P. K. Mukku, R. Lorenzo: DNU Immune RHBD-14T SRAM Cell for Space and Satellite Applications OFF transistor's reverse biased drain region is referred to as a circuit's sensitive node [21]. This vulnerable node has a significant effect on radiation particles. If a high-energy particle strikes a PMOS/ NMOS transistor, it will emit a 0 to 1 or 1 to 1/ 1 to 0 or 0 to 0 transient pulse, depending on the initial logic value stored in the memory cell.
By considering the above approach to SEI-14T, hence all the storage nodes are the sensitive nodes. Considering the memory cell is at logic 1, means Q, QB, S0 and S1 stores logic 1, 0, 0 and 1 respectively.

1) SOFT ERROR ANALYSIS AT SENSITIVE NODE Q
When a high-energy particle hits the primary storage node Q, the data is temporarily converted from '1' to '0'. As a result, the transistors N3, N5 are temporarily disabled. Then, the storage nodes QB, S0, and S1 are in a condition of high impedance. According to the articles [21], [26], the high impedance condition cannot alter the logic state when induced by a high-energy particle. Thus, QB, S0, and S1 retain their original states. Initially S0 and S1 stores logic 0 and 1 respectively. As result, Q restores its logic 1 through P4 transistor This recovery issue is shown in Fig. 7(a) single event upset (SEU) at Q storage node.

2) SOFT ERROR ANALYSIS AT SENSITIVE NODE QB
When a high-energy particle comes into contact with the storage node QB, the stored data flips from '0' to '1' for a short instant. As a consequence, N2, N4, and N6 are temporarily in ON condition. Other storage nodes, S1, S0, and Q, were also temporarily changed to logic 0, 1, and 0, respectively. For this reason, we maintain the P1 transistor is stronger (2x) than N6. This results P1 transistor force to move logic 1 to S1 storage node. Therefore, QB back to logic 0 due to P4, N1 and N3 transistors are in ON condition, as shown in Fig. 7(b) single event upset (SEU) at storage node QB.

3) SOFT ERROR ANALYSIS AT SENSITIVE NODE S0
When a high-energy particle impacts node S0, storage data temporarily flips from '0' to '1'. This leads to P1 and P4 transistors temporarily OFF and N2 being ON. The OFF state of the transistors N2 and P4 causes the storage node Q to be in a high impedance state. Consequently, Q keeps its initial logic 1, makes N5 always active, and restores the S0 value to 0, as shown in Fig. 7(c), SEU @ S0.

4) SOFT ERROR ANALYSIS AT SENSITIVE NODE S1
When a particle with a high energy threshold impacts node S1, the data temporarily changes from '1' to '0'. This bit flip makes P2, N2 turned ON and N1, P1, P4 are turned OFF. As a result, other storage nodes stored data is also temporarily changed. For this reason, we maintain N5 transistor is stronger (2x) than P2. As well as P1 is stronger than N6 transistor. Therefore, these two conditions pulls S0 and S1 to logic 0 and 1 respectively. Figure 7(d) shows the single event upset (SEU) recovery at storage node S1.

5) SOFT ERROR ANALYSIS AT SENSITIVE NODE PAIRS Q-QB
If a high energy particle strikes node pair Q and QB, then Q (QB) temporarily alters stored data from 1 to 0 (0 to 1). As a consequence, N4, N6, and N3, N5 are temporarily turned ON and OFF. This is the same case as when QB induced a high-energy particle impact. Stronger PMOS transistor (P1) pulls logic 1 to S1 storage node. Therefore Q and QB recovers there storage data due to P4 and N3,N1 ON transistors respectively, as seen in Fig. 7(e), DNU @ Q-QB.

6) SOFT ERROR ANALYSIS AT SENSITIVE NODE PAIRS Q-S1
If a high energy particle strikes node pair Q and S1, then Q (S1) temporarily alters stored data from 1 to 0 (1 to 0). As a consequence, N3, N5, and N2, P2, P3 are temporarily turned OFF and ON, respectively. This makes other storage nodes also temporarily flip the stored data. However, as mentioned in the previous section P1 transistor is stronger than N6 and P2 transistors. This leads to push the vdd voltage towards the storage node S1, as a result S1 recovers the storage data. Further P4 transistor is in ON condition makes Q recovers its lost data, as shown in Fig. 7(f) DNU @ Q-S1.

7) SOFT ERROR ANALYSIS AT SENSITIVE NODE PAIRS QB-S1
If a high-energy particle strikes node pair QB and S1, then QB (S1) temporarily alters stored data from 0 to 1 (1 to 0). As a consequence, N4, N6, P2, and P3 are temporarily turned ON. This causes storage nodes Q, QB and S0 temporarily change the state. However, as mentioned in the SEU at QB and SEU at S1, due to the stronger transistors P1 and N5 makes S1 and QB recovers the flip data, as shown in Fig. 7(g) DNU @ QB-S1.
Further, monte-carlo 500 simulation steps analysis was also considered for the reliability of the SEI-14T memory cell at 0.8V VDD. When energy particles impact storage node combinations Q-S0 and QB-S0, storage nodes temporarily flip the bits. This may also cause other storage nodes to flip the initial bits. According to the articles [16], [27], [28], any of the sensitive storage node pairs have charge sharing between the two NMOS or PMOS transistors happen if the storage node pairs have less than or equal to 2 µm area and between FIGURE 7. Soft error recovery simulation of SEI-14T memory cell at 70fC injected charge with monte-carlo simulation a) single event upset at node Q b) single event upset at node QB c) SEU at node S0 d) SEU at node S1 e) double node upset at Q-QB node pair f) double node upset at Q-S1 node pair g) double node upset at QB-S1 node pair.
NMOS to PMOS transistors have 0.6 µm area. To minimize the charge-sharing issue, we keep a 2.2 µm space between Q and S0 and 2.1 µm between QB and S0, as shown in Fig. 4 layout design.
The probability of two or more storage nodes simultaneously flipped due to single high energy ion strike is low. If this happen, charge dispersion spread across the other nearer storage nodes [21], [27]. By considering larger source isolation and stacking of additional PMOS transistors to P3 and P4 overcomes the parasitic bipolar effect and pulse quenching [17], [18]. This also results increasing the dynamic power consumption and more layout area. There is always a trade-off between the robustness and soft error upset probability of a memory cell. By considering thin-cell layout based interconnections scaling with various metals miniaturization of cell area. In our layout design, we considered thin-cell layout procedure as shown in Fig. 4.

IV. PERFORMANCE METRICS SIMULATIONS AND DISCUSSIONS
Various performance metrics of all radiation-hardened memory cells were performed after post layout simulations in commercial 45nm bulk CMOS PDK. The proposed SEI-14T cell was compared to other reliable radiation-hardened cells such as 6T-SRAM, Quatro-10T, RHM-12T, RHD-12T, RSP-14T, RHPD-12T, RH-14T, EDP-12T, and QCCS-12T. The transistor sizes are considered as specified in their respective articles.

A. ACCESS TIME
The read access time is (RAT) measured when the word line is enable, time required to develop a minimum of 50mV potential difference between BL and BLB [29]. During the read-0 operation, the voltage at the '0' storage node rises owing to the influence of the voltage divider between the access and driver transistors. This drastically limits the driving ability throughout the storage node and significantly reduces the memory cell's read access time due to the body effect problem [30].
RAT is typically calculated using the read current and bit line capacitance of the memory cell [16], [17]. All the presented memory cells have one access transistor linked to the bit line; consequently, the bit line capacitance of the existing memory cells is equivalent. The proposed SEI-14T cell has two more access transistors than existing cells. However, the read discharge path towards the PMOS and NMOS access transistors has approximately the same bit line capacitance as the existing cell's capacitance. In addition, the read current is approximated based on the current that flows from the pre-charged bit line value and the conducting path from access and driver transistors to ground [31]. This is also known as the cell ratio (CR) of the memory cell [21]. To make fair comparisons, we assumed that all memory cells VOLUME 11, 2023 had a equal CR ratio. The Quatro-10T, RHD-12T, and RH-14T, as well as the RSP-14T, have a longer read access time and a smaller read current because the driving strength at logic 0 to their internal storage nodes is lower. The RHPD-12T and EDP-12T pull-down transistors have low driving capabilities at logic 1, resulting in a longer RAT. The reduced RAT of QCCS-12T and SEI-14T memory cells is due to their enhanced driving capabilities across storage nodes in both logic states.
Storage cells, such as latches and SRAMs, are particularly susceptible to process, voltage, and temperature (PVT) change [23], [32]. Therefore, we test the read access time of each memory cell under PVT variations, with an average temperature of 27 • C and temperature variations ranging from -45 • C to 120 • C. Moreover, the nominal supply voltage is 0.8V, and the supply voltage varies from 0.5V to 1V. Additional changes in threshold voltage between 0.05V and 0.09V. Fig. 8(a), (b), and (c) shows the comparison of all presented memory cells read access time under PVT variations.
The time difference between the intersection of both storage nodes' time to word line rising by 50% of its full swing voltage time is used to calculate write access time (WAT) [16]. This WAT depends on discharging feedback path to the storage nodes and driving ability to write the stored data. When the memory cell is at logic 1, RHD-12T and RHPD-12T take longer time to discharge the storage node than the other memory cells due to longer feedback paths. Hence, these two memory cells exhibit poor write capability.
We evaluate the WAT of each memory cell under various PVT conditions. Figure 8(d), (e), and (f) show that the WAT is about the same for all memory cells except RHD-12T and RHPD-12T. At lower supply voltages, higher temperatures, and threshold values, the write delay of RHD-12T and RHPD-12T cells is significantly increased. Due to the additional write access path to the storage nodes, strong driving capability across storage nodes, SEI-14T exhibits a lower write delay than all memory cells.

B. STATIC POWER DISSIPATION
During the hold state of a memory cell, power dissipation is referred to as static or hold power dissipation. The leakage in the inverter pairs and the bit line determine the static power dissipation of a memory cell [30]. The static power dissipation or leakage power is a crucial parameter for SRAM cell because it directly impacts the overall power efficiency, especially as technology nodes advances to nano-meter. On the other hand dynamic power can be minimized by reducing the clock frequency, but static power remains constant and cannot easily controlled. Hence, all mentioned memory cells static power dissipation was verified under PVT variations. Compared to other memory cells, Quatro-10T, RHD-12T, RH-14T, and RSP-14T have more leakage in their inverter pairs, which means they lose more static power. Since the SEI-14T and QCCS-12T have additional access transistors to the bit line, static power dissipation is reduced. We verified all memory cell's static power dissipation under PVT variations. As shown in Fig. 8(g), (h), (i), SEI-14T exhibits lower static power under voltage and temperature variation.
By seeing all PVT variation results, memory cells occupy higher read and write access time and static power dissipation at higher temperatures. This is because the transistor's majority carriers mobility has risen [23], [32]. However, the temperature has a low impact on write access time. Moreover, the temperature has a more significant effect on RHD-12T. The lower supply voltage will impact the read access time but not the write access time, except for RHD-12T and RHPD-12T memory cells. When threshold voltage increases, access time and static power dissipation increase and decrease, respectively [32]. This has been demonstrated in PVT variations.

C. DYNAMIC POWER CONSUMPTION
During the read and write operation, charging and discharging of bitline capacitance is stated as dynamic power consumption. This is formulated as follows: where α bitline is the switching factor for bitline, C eff is total effective capacitance, VDD is supply voltage and f read/write is read/write operating frequency. Fig. 9 shows the dynamic read and write power consumption of all existing and SEI-14T memory cells. For a differential bitlines of a memory cell, switching activity factor is stated as 1 [33]. This is due to either one of bitline discharges for every instant of operation. From the Fig. 9, 6T-SRAM, Quatro-10T, RHD-12T, EDP-12T exhibits lower read power due to lower f read . RHM-12T also exhibits lower f read but capacitance of the bitline increase which causes C eff drastically increases as a result higher read power. QCCS-12T, SEI-14T, RHPD-12T have additional access transistors connected to bitline to storage nodes leads to increase the overall effective capacitance as a result higher read and write power consumption compared to the other mentioned one set of access transistors. RHD-12T and RH-14T memory cells exhibits lower write power due to lower f write .
Moreover, for extreme fabrication and environment variations, process corner simulations ensure the reliability of the memory circuits performance [34]. As a result, all mentioned memory cells read, write access time, dynamic and static power dissipation was verified under various process corners (TT, FS, SF, FF, SS).
As shown in Fig. 10(a), SEI-14T and QCCS-12T achieves lower read access time even at variations in process corners. From Fig. 10(b), all mentioned memories achieves approximate write access time at process corners variations except RHD-12T and RHPD-12T due to longer feedback path to the primary storage nodes. Figure 10(c) shows that at TT and SF corners there is only a slight variations in the dynamic power of all mentioned memory cells. Due to increasing in the overall effective capacitance, QCCS-12T, SEI-14T achieves maximum dynamic power consumption that other memory 96262 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.  cells. Due to lower inverter leakage and stacking transistors, SEI-14T and QCCS-12T achieves lower static power dissipation even at variations in the process corners, as shown in Fig. 10(d).

D. STABILITY
Stability is another essential memory cell performance metric. Most of the memory cells reported in the literature involve a trade-off between stability and soft error probability. So, it is necessary to determine the stability of memory cells. The read, write and hold static noise margins are measures for memory cell stability. During a memory cell read operation, an external noise voltage is delivered across the main storage node, and the voltage transfer curve at the primary storage nodes is observed. These curves combine to form a butterfly curve. The side length of the biggest square that can be placed in the smallest lobe of the butterfly curve is used to calculate the RSNM of a memory cell [7]. The logic state driving capabilities govern RSNM among storage nodes and the memory cell ratio (CR) [35]. For a fair comparison, we analyze all memory cells with an identical cell ratio of 2. Figure 11 depicts the RSNM of all radiation hardening memory cells. Among all the memory cells, proposed SEI-14T exhibits higher RSNM at a typical typical corner of 1V supply voltage.
According to [36], corner and temperature variations impact memory cell stability. As a result, we analyze each memory cell's RSNM values via various corners (TT, SS, SF, FS, FF) and temperatures values (−45 • C to 120 • C).  Among all the variations we considered worst case corners (FS, SF and FF) and temperatures (125 • C and −45 • C) due to inadequate design tolerance for space and satellite applications [34]. Figure 12 depicts all memory cells' worst-case corner and temperature SNM values. By comparing all the memory cells RSNM, RHM-12T, RHPD-12T, RSP-14T, and RHD-12T cells have worse read stability owing to weak driven logic 1 over the primary storage node Q. SEI-14T and RH-14T exhibits higher RSNM due to stronger driven logic states at both the storage nodes.
The ability to flip stored data during a memory cell's write operation is stated as write SNM (WSNM). According to [37], word line write trip voltage is an accurate measure for analyzing memory cell write margin. The write margin is determined by setting bitlines with required data to be written and then ramp up the WL voltage upto VDD. The potential difference between VDD and WL when the Q and QB cross each other is used to calculate the write margin of a memory cell [21]. The write ability of a memory cell is primarily determined by its strong write ability across the storage nodes and time to write the stored data [21], [38]. We verified all presented memory cells write margins under worst case corner and temperature analysis, as seen in Fig. 12. Among all radiation hardening memory cells, RHD-12T and RHPD-12T have a reduced write margins due to the longer feedback path to the storage nodes and higher write time to write the storage data. The proposed SEI-14T and QCCS-12T cells exhibits higher write ability due to their strong writing data across the storage nodes and lower feedback path to write the data. After that, RHM-12T exhibits higher WM due to higher pull-up ratio. Hold SNM is assess same as like read SNM except wordline is disabled. We also analyzed the worst case hold static noise margin during the memory cell's hold operation. Under the worst-case analysis, RH-14T and SEI-14T exhibit stronger hold stability than other memory cells, as illustrated in Fig. 12. VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.   The N-curve method can also be used to quantify read stability of a memory cell. It is measured by connecting a voltage source across the '0' storing primary storage node, when the memory cell is in the read mode. Further, observe the current across the external voltage source, which indicates the voltage and current parameters for the read procedure [37]. Figure 13 shows the comparison of all presented radiation hardening memory cells N-curve waveforms. All curves touches three points on x-axis. First two points voltage difference is stated as static voltage noise margin (SVNM) and amplitude of the curve is stated as static current noise margin (SINM). Among all the memory cells, RHPD-12T exhibits higher SVNM even they have less RSNM value. After that proposed SEI-14T exhibits higher SVNM and SINM compared to the all existing memory cells. The higher SVNM and SINM exhibits more reliable for read stability.

E. SOFT ERROR ANALYSIS AND COMPARISONS
The reverse-biased diffusion area of the memory cell is referred to as the sensitive node to the charged particles. In addition, when high-energy charged particles impact MOS devices, they create positive and negative glitches in PMOS and NMOS transistors, respectively, as shown in Fig. 14. For modeling the soft error robustness of an SRAM cell, we employ a double exponential current source [26], denoted by Eq. 2.
here, I peak denotes the peak amplitude of the injected current pulse, whereas τ α and τ β indicate the collection time and ion track constant time, respectively. For high-energy particles, linear energy transfer (LET) ranging >10MeV-cm 2 /mg, we have to consider τ α and τ β as 200ps and 50ps respectively according to [26] and [39]. The I peak value chosen as 468 µA to simulate a 70 fC disruptions at all sensitive nodes. Creating a positive and negative pulses across PMOS and NMOS is by applying a double exponential current source in forward and reverse orientations as shown in Fig. 15. This procedure applied to proposed SEI-14T and verify the soft error analysis to all sensitive nodes of the circuit. As discussed in the section III, soft error recovery analysis, Fig. 7 simulation was performed by considering the above approach when the memory cell is in the hold mode [7]. Single event upset (SEU) assessed by applying a double exponential current source across the individual sensitive nodes. Whereas, double node upset (DNU) assessed by considering sensitive node pairs and add one node as worst case charge deposited and other node vary the charge injection with double exponential and varying different injected charges [40].
The key term to assess the memory cell's soft error rate is critical charge (Q crit ). Q crit of the memory cell represents the minimal quantity of charge collected at the sensitive node of a memory cell that causes a bit flip. The effective Q crit is the least sensitive node's Q crit value in a circuit. This Q crit is primarily determined by the magnitude of the applied double exponential current source and the ion track time constant of the memory cell [39]. Q crit is calculated with the following equation: where I inj (t) is the injected current pulse at the sensitive nodes i.e. Eq. 2, T crit stands for critical time at which the VOLUME 11, 2023 FIGURE 16. Basic simulation flow graph for critical charge calculation [41].
storage bit be flipped. The detailed critical charge measuring is shown by using the flow graph, seen in Fig. 16. The lowest value of Q crit among all sensitive nodes is referred to as the effective critical charge of a memory cell. Figure 17 shows the proposed SEI-14T critical charge graphical estimation when the storage node flipped at 0.8V supply voltage. Table 1 shows the effective critical charge values of all presented radiation hardening SRAM cells at 0.8V supply voltage. On the other hand, this critical charge is more susceptible to supply voltage, temperature and corner fluctuations [42]. So, we verified all mentioned memory cells effective critical charge under various corners. Among all the corners, Fast NMOS Slow PMOS (FNSP) exhibits lower effective critical charge values. Hence, all mentioned memory cells effective critical charge is varied with various VDD values (0.5V to 1.2V) and temperature values (−45 • C to 125 • C) at FNSP worst case corner. From Fig. 18 noted that, critical charge increases with supply voltage and decreases with temperature variations. By considering this discussions, change in critical charge can modeled as shown in Eq. 4.
where k,n are the material and technology dependent constants. k and n are linearly and exponentially depends on supply voltage and temperature, respectively. VDD and T are the change in supply voltage and temperature. Among all the mentioned memory cells, the SEI-14T memory cell has a greater effective critical charge even at lower supply voltage and higher temperature conditions due to additional parallel PMOS transistors connected to the storage  nodes weaken the pull-up path. This increases the sensitive node capacitance and achieves higher critical charge. In other words proposed SEI-14T memory cell can withstand the charge upto 74.8 fC at critical voltage and temperatures. At 0.5V, RHD-12T has the lowest effective critical charge among all presented memory cells due to lower sensitive node capacitance.
We also verified how τ α and τ β impacts the effective critical charge of the memory cells. Among all the memory cells, maximum effective critical charge exhibited designs like QCCS-12T, EDP-12T and suggested SEI-14T (shown in Table 1) τ α and τ β values varied in double exponential source. Figure 19 demonstrates the change in τ α will also impacts the critical charge of all three memory cells. This is because of 96266 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.   τ α denotes the collection time of total charge stored at the sensitive node of a memory cell. Whereas, change in τ β not influenced more on critical charge. Double node upset critical charge is validated by considering a worst-case critical charge (effective critical) storage node with constant injected charge, while changing the other storage node injected charge using Eq. 2 and 3 (not shown in the paper). In extreme radiation environments, process, voltage and temperature changes in the memory cell are responsible for the highest failure probability [43]. Therefore, we validated the soft error failure probability (P F ) towards double node upset by assuming 70 fC charge sharing across sensitive primary storage node pair (Q-QB) of all mentioned memory cells and performing PVT analysis by considering Monte-Carlo 2000 simulation steps. The failure probability is assessed by using following expression: Simulations fails to recover at 70fC Total no. of simulation steps (5) Table 2 shows the comparison of mentioned memory cells double node upset failure probability at 2000 step MC simulation. Figure 20 shows the 2000 step Monte-Carlo simulation at a charge share of 70 fC across the primary sensitive storage node pair. Comparing all memory cells failure probability, SEI-14T had no failure even at a charge share of 70 fC across the sensitive primary storage node pair under PVT variations.
In geosynchronous orbit, various high-energy particles like protons, alpha particles, neutrons trapped inside the earth's magnetic field and induced a few MeV to 100 MeV energy [6]. At deep sub-micron technologies, these high energy particles are more susceptible to memory circuits due to lower critical charge [12]. The susceptibility of soft error to memory circuits was assessed by effective critical charge across the sensitive node of the circuit. The soft error upset rate (SER) was depends on sensitive volume, charged particle flux intensity, collected and critical charge of the device when it is impacted with high-energy particle [6], [41]. It is expressed as (6) where N flux stands for neutron particles flux, Q crit and Q coll stands for critical and collected charges. SER has exponential dependent on critical charge of the device. Means a small increasing in critical charge leads to large reduction in soft error upset rate [41], [44]. So, we verified all existing and proposed memory cells critical charge under various supply voltages and temperature conditions at worst case corner as shown in Fig. 18. This clearly states that SEI-14T exhibits  larger critical charge across lower VDD and higher temperature conditions due to higher node capacitance. As a result, SEI-14T exhibits lower soft error upset rate by considering Eq. 6.

F. AREA AND OVERALL METRICS COMPARISON
A 3 × 3 structure is used to compare the area of all literature and proposed memory cells. Fig. 21 depicts the SEI-14T 3×3 layout. The inner cell area of a 3×3 layout is considered the minimal area of a cell [21]. From the layout areas of each memory cell, the probability of soft error upset (P s ) can be calculated. The ratio of the sensitive area to the total area of the memory cell is used to estimate soft error probability [7], [16], [23]. Table 3 shows the sensitive area, total layout area, and P s values comparison across all existing and proposed memory cells. Among all memory cells layout area, SEI-14T exhibits lower area compared to RHPD-12T and other 12T cells due to less number of double width transistors and thin-cell layout design with more metals as interconnections. Further, EDP-12T and SEI-14T exhibits lower soft error probability due to lower sensitive area.
After SEI-14T, EDP-12T have the lowest soft error failure probability among all memory cells, as seen in Table 3.
We also examined overall performance metrics at worst case PVT analysis, as shown in Table 3. We describe the access time overhead rates by evaluating the compared memory cells access time to the proposed SEI-14T cell access time [26]. The columns RAT and WAT in Table 3 represent relative read access and write access time, respectively, where Eq. 8 denotes dependence.

Compared Cell − Proposed Cell
Proposed Cell (8)

G. YIELD COMPARISON
Another critical performance parameter for memory cell reliability and stability is yield estimation [45]. The yield estimate determines memory cell performance under various process changes. As a result, we validate memory cell stability yield prediction using Monte-Carlo 2000 step simulations with a mean of the gaussian distribution equal to the Vth of the related device [46]. This simulation is carried out with VDD ranging from 0.6 to 1V. For a 1MB SRAM to attain a 90% yield, the read and write SNM must surpass 4% of the supply voltage, according to [46] and [47]. Due to the maximum read and write performance, EDP-12T and QCCS-12T considered for yield comparison to the suggested SEI-14T. The yield criteria for read and write SNM are illustrated in Fig. 22(a) and (b), respectively. EDP-12T, QCCS-12T, and the proposed SEI-14T have a higher margin yield than the yield criteria. The suggested SEI-14T SRAM cell has a much more significant write yield margin than the EDP-12T and QCCS-12T cells 96268 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.   due to strong driving capability across the storage nodes and additional access transistors to the secondary storage nodes.

H. SOFT ERROR IMMUNE ROBUSTNESS FIGURE OF MERIT
Overall memory cell efficiency to immune from soft error and reliability of memory cell is stated with figure of merit of a memory cell. The ratio of effective critical charge (Q crit ) product with the stability to the access time, average power consumption and area of the memory cell is stated as figure of merit towards soft error immune robustness and reliability [7].
From the Fig. 23, the proposed SEI-14T memory cell exhibits higher FOM than the existing memory cells due to additional access transistors achieve higher write margin, higher node capacitance increases effective critical charge across the sensitive storage node but this increases dynamic power consumption, and decreasing the write access time of the memory cell leads to improve more FOM than existing memory cells. Figure 23 shows the comparison of existing memory cells relative FOM value to the proposed FOM value.

I. IMPACT ON SCALING TECHNOLOGY NODE
The scalability of an SRAM cell is essential in deep submicron technologies. Scaling the size of a transistor makes it more susceptible to threshold voltage changes and soft error probability, according to [48] and [49]. Therefore, a 16-nm predictive technology MOS model (16-nm PTM HP model) is used to verify the suggested cell's efficiency in scaled technologies compared to the existing cells. To ensure that the design is scalable, we use the same methods as in [50]. All the verification results comparison with RH-14T, EDP-12T and QCCS-12T due to their better stability and soft error resilience probability. The proposed SEI-14T has a static power consumption of 1.39×/ 1.24×/ 0.64× times lower and read SNM is about 1.09×/ 1.45×/ 1.08×/ times higher than the RH-14T/ EDP-12T/ QCCS-12T. Moreover, read access time is 1.69×/ 1.40× times lower than RH-14T/ EDP-12T and 0.68× higher than QCCS-12T, due to the additional access transistors. Further write access time was improved 1.57×/ 1.46×/ 1.18×/ than the mentioned memory cells at a 0.7V supply voltage. Although effective critical charge is exhibited 1.82×/ 1.41×/ 1.28× higher than RH-14T/ EDP-12T/ QCCS-12T. Hence, the above observations, SEI-14T is not impacted more on performance metrics while scale down the technology node.

V. CONCLUSION AND FUTURE SCOPE
A soft error immune RHBD-14T SRAM cell (SEI-14T) for space and satellite applications has been presented. SEI-14T memory cell are resistant to soft errors in all sensitive nodes. Additionally, sensitive node pairs attenuate across all node pairs except Q-S0 and QB-S0. A sensitive layout area separation will prevent charge-sharing issues in this case. Under varying PVT conditions, SEI-14T exhibits reduced write access time and static power dissipation. After QCCS-12T for read access time, SEI-14T has a reduced access time. In addition read, write and hold stability is enhanced during the worst corner and temperature analysis. However, SEI-14T produces a higher effective critical charge at worst case corner and VDD variability. As a result, the soft error rate will be reduced. In addition, SEI-14T has better read and write yield probability with the highest figure of merit. Hence, the SEI-14T SRAM memory cell is a good alternative for reliable space and satellite applications.