Phase-Shedding Control in Two Parallel Interleaved Three-Phase ZVS Inverters for Improved Light Load Efficiency

The parallel interleaved three-phase inverters are suitable for high-power applications due to the current ripple canceling effect. The power density and efficiency can be further improved with the current ripple prediction (CRP) based high frequency zero-voltage switching (ZVS). However, the variable switching frequency increases rapidly as the power decrease, resulting in higher turn-off loss at light load despite the elimination of turn-on loss. In this paper, a phase-shedding control strategy is proposed along with the CRP based ZVS method to improve the light load efficiency. Only four phase-legs of the two parallel inverters operate at light load to reduce the switching frequency and the circulating current between the two clamping phase-legs. The proposed method can achieve full-range ZVS for all the switches without any auxiliary circuits or high frequency sensors. Current sharing can also be realized between the two clamping phase-legs based on accurate gate signal modulation. A 5 kW simulation and experimental prototype using SiC devices interfacing 400 V dc with three-phase 110 V ac grid is developed to verify the effectiveness of the proposed control strategy.


I. INTRODUCTION
Two-level three-phase voltage-source inverters (VSI) is widely used in various kinds of applications, including photovoltaic inverter, electric vehicle, energy storage system, etc. Even though the efficiency of some commercial inverters is pretty high, their power density has not been improved significantly due to the relatively low switching frequency of silicon IGBTs. The silicon carbide (SiC) MOSFETs have faster switching speeds and lower switching loss compared with their Si counterparts [1]. Nevertheless, the total switching loss still increases sharply when operating at hundreds of kilohertz. Since the turn-on loss of the SiC MOSFET is The associate editor coordinating the review of this manuscript and approving it for publication was Pinjia Zhang . much higher than the turn-off loss, the zero-voltage-switching (ZVS) technique can be used to eliminate the turn-on loss and improve the efficiency even operating at high frequency [2].
Various kinds of soft-switching methods have been proposed and conducted over the recent years [3], [4], [5], [6], [7], [8]. Most of them need auxiliary circuits to produce high current ripple to realize the ZVS of power devices. They can be divided into resonant DC link (RDCL) inverters [3], [4], [5] and auxiliary resonant commutated pole (ARCP) inverters [6], [7], [8] based on the position of the auxiliary circuits. These methods can realize soft switching of the main switches and the auxiliary switches at a fixed switching frequency, but the costs and complexity are greatly increased.
A simple way to achieve ZVS without additional circuits is to increase the inductor current ripple and change its direction in each switching cycle. The output capacitor of the power device can then be charged and discharged during the dead time. This idea known as critical conduction mode (CRM) or triangular current mode (TCM) has been successfully implemented to realize the ZVS of buck/boost converter [9], totem-pole bridgeless power factor correction (PFC) rectifier [10], and three-phase inverter [11], [12], [13]. Zero current detection (ZCD) circuit and high frequency current sensor is needed to determine the switching instant. However, the switching frequency variation range is quite large in a line cycle. In [14], discontinuous pulse width modulation (DPWM) and frequency synchronization concept is adopted to reduce the frequency range. The switching state of one phase-leg is fixed, and the other two phase-legs switch at high frequency. To synchronize the switching frequency of the two phase-legs, the former phase-leg runs in discontinuous conduction mode (DCM), and the latter phase-leg works in CRM. Zero-current switching (ZCS) instead of ZVS is achieved for some switches.
A current ripple prediction (CRP) and DPWM-based fully digital control ZVS technique is proposed in [15]. No additional sensor or auxiliary circuit is needed. The variable switching frequency can be simply calculated based on the sampled voltage and current information. This method has also been used in two parallel interleaved three-phase inverters to achieve higher power level [16]. The high current ripple can be cancelled by the interleaving structure so the filter size is further reduced. According to the operating principle of these methods, lower current ripple is required at light load, so the switching frequency increases sharply as power decreases. Although the turn-on loss is eliminated, the turn-off loss is significantly increased at light load due to the high frequency.
A phase-shedding control method is used in multi-phase dc-dc converters [17], [18] and PFC circuits to improve the light load efficiency [19], [20]. The main idea is to reduce the number of operating phase-legs at a light load. Then the switching frequency will decrease, and the switching loss and the driving loss will also drop. In [21], a CRM-based phase shedding control for two-channel parallel three-phase inverter is proposed. The switching frequency is decreased with only four phase-legs operation. However, dynamic current sharing between the two clamping phase-legs is not achieved, and circulating current exists. Meanwhile, ZCD circuits and high frequency current sensors are still indispensable.
In this paper, the phase shedding control is applied to the CRP based two parallel interleaved three-phase inverters. A new variable switching frequency control method is proposed with only four operating phase-legs. To further improve the light load efficiency, a current-sharing method is proposed, and the circulating current is eliminated. Compared with the six phase-legs operation, the switching frequency is greatly reduced with only four phase-legs under the same light load. The switching loss is further decreased, so the light load efficiency is improved. The modulation scheme and the current ripple control method are analyzed in Section II. The switching frequency calculation is discussed in Section II-B. The simulation and experimental verification are illustrated in Section III. Finally, Section IV gives the conclusion. Fig. 1 shows the configuration of the two parallel interleaved three-phase inverters. The six inverter-side inductors L 1 and L 2 have the same inductance. The three filter capacitors are denoted as C. The inverter-side inductor currents for the two inverters are i x1 (x = a, b, c) and i x2 respectively. The summation of the two parallel inductor currents is i x3 . i cx is the filter capacitor current. i gx and v x are the grid phase current and voltage. V dc is the DC voltage. Q 1 to Q 12 are the switches for the two inverters. The phase delay of the carrier waves between the two inverters is 180 • .

A. ANALYSES OF CIRCULATING CURRENT AND FOUR PHASE-LEGS OPERATION
Under heavy load conditions, DPWM method is used so that at any time only two phases (four phase-legs) are switching. The other phase (two phase-legs) is in clamping mode whose switching state remains constant in a sector. In this way, not only the ZVS realization condition is weakened from 12 switches to 8 switches, but the three-phase currents are also decoupled [16]. To reduce the unnecessary current ripple at light load, the switching frequency increases with the decrease of the phase current. For the parallel interleaving structure, two inverters share the grid current, so the switching frequency is quite high at light load. The turn-off loss increases significantly despite the elimination of the turn-on loss.
To improve the light load efficiency, the phase-shedding technique can be used. The second inverter stops switching (three phase-legs shedding), so the entire power is processed by the first one. However, undesired circulating currents appear between the two clamping phase-legs. The simulation waveforms are illustrated in Fig. 2. m x (x = a, b, c) are the discontinuous modulation waves. It can be seen that i a1 and i a2 have different current directions during the clamping state causing increased conduction loss. Fig. 3 shows the   current flowing path from 150 • to 210 • when Q 2 is constant on. Although Q 7 to Q 12 are all turned off, i a2 can still flow through the body diode of Q 8 with the same slope as i a1 , resulting in a positive current. The detailed analysis of the circulating current has been given in [21] and is omitted here.
Since there is no switching loss during the clamping state, when the phase-leg of inverter 1 is in the clamping state, the corresponding phase-leg of inverter 2 can also be clamped in the same state. In this way (two phase-legs shedding), not only the circulating current is eliminated, but two clamping phase-legs can also share the phase current and further reduce the conduction loss. Fig. 4 shows the switching patterns of inverter 2 in a line cycle. Each of the six switches is turned on for 60 • consecutively.

B. CURRENT RIPPLE ANALYSIS UNDER FOUR PHASE-LEGS OPERATION
Sector 1 is taken as an example to show the operating principle with four phase-legs. As shown in Fig. 5 (a), from 0 • ∼30 • , phase a is clamped, so Q 1 and Q 7 are turned on. ZVS is only needed to be achieved for Q 3 to Q 6 . From 30 • ∼60 • , Q 6 and Q 12 are turned on because phase c is clamped as shown in Fig. 5 (b). ZVS should be realized for Q 1 to Q 4 . Assume the reactive current caused by the filter capacitors C is neglected and the voltage across C is equal to the corresponding grid voltage v x . Thus, for the high-frequency switching phase-legs, i gx can be regarded as the average value of i x1 in a switching cycle. Owing to the symmetry of the carrier wave, the relationships between i x1 and i gx are given by The requirements to achieve ZVS for phase x are i x1 (t on ) < −I bias , i x1 t off > I bias (2) where t on and t off are the turn-on and turn-off instants of the upper switch. I bias is the bias current to charge/discharge the output capacitors of the switches. SiC MOSFET is used as the switching device in this paper. Due to its small output capacitance, I bias is designed as 2 A. The specific design consideration is given in [22]. VOLUME 11, 2023 77795 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.
According to (1), equation (2) can be rewritten as In Fig. 5 (a), the current ripple of i c1 can be directly calculated based on the equivalent circuit between t 2 and t 4 , and the equivalent circuit is shown in Fig. 6 (a). Similarly, the current ripple of i b1 can be calculated between t 5 and t 1 , and c is shown in Fig. 6 (b).
Based on Thevenin's theorem, from t 2 to t 4 , i c1 can be expressed as From t 5 to t 1 , i b1 is calculated as The time duration of each mode can be expressed by the modulation wave m x and the switching frequency f s , i.e.
Thus, equation (5) can be rewritten as It means switches Q 3 to Q 6 can achieve ZVS during 0 • ∼30 • if the corresponding switching frequency conditions are satisfied. Since all the gate signals share a single carrier wave in the inverter, the switching frequencies of both phases are the same. Therefore, to achieve ZVS for all the switches, the lower critical frequency should be chosen as the unified switching frequency. The detailed frequency selection is analyzed in Section II-B.
Similarly, during 30 • ∼60 • , the ZVS condition can also be derived as

C. SWITCHING INSTANT SYNCHRONIZATION OF THE FOURTH PHASE-LEG
In this part, the turn-on instant of the fourth phase-leg is discussed. In a digital controller, the compare value in a PWM module is generally updated at the peak or the valley of the carrier wave. Therefore, after the change of the clamping state, a straightforward way to turn on the fourth phase-leg is also at the peak or the valley. Take phase a at 330 • as an example. As shown in Fig. 7 (a), m a jumps to 0 at the peak value of the carrier wave at t 3 . If Q 7 is turned on at t 3 , i a2 starts to rise from zero with the same slope as i a1 . However, since i a1 is not zero at t 3 , the initial current difference between i a1 and i a2 will remain for a long time due to the low damping resistance, as shown in Fig. 8. The current direction of i a1 and   i a2 may even be opposite causing additional circulation loss or grid current distortion.
To avoid the circulation current and achieve dynamic current sharing, Q 7 should be turned on when i a1 is around zero. Zero current instant can be obtained with a ZCD circuit, but it increases the complexity of the circuit. Fortunately, according to the proposed CRP based ZVS method, when the grid current i gx is positive, i x1 is designed to be -I bias at the turn-on of the upper switch. If i gx is negative, i x1 is designed as I bias at the turn-off of the upper switch. As shown in Fig. 7 (b), i a1 is -I bias at t 1 , which is close to zero. Therefore, Q 7 can be turned on at t 1 leading to only a little current difference.

III. SWITCHING FREQUENCY SELECTION AND COMPARISON
The critical switching frequencies in sector 1 with four operating phase-legs are derived in (7) and (8). To achieve ZVS for all the switches and minimize the unnecessary current ripple, the lower critical frequency should be chosen as the inverter 77796 VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.  unified switching frequency. Assuming the circuit parameters are listed in Table 1, the critical switching frequencies for both phases to achieve ZVS at different loads in sector 1 are shown in Fig. 9. The dashed lines are f sb , while the solid lines are f sc and f sa during 0 • ∼30 • and 30 • ∼60 • respectively. It can be seen that the critical switching frequencies are symmetry and continuous even at 30 • . The solid lines are always lower than the corresponding dashed lines. Therefore, f sa and f sc can be chosen as the unified switching frequency.
For other sectors, the three-phase voltages and currents simply exchange their positions, so the current ripple analyses and critical frequency calculations are the same. The derivation of the equations in other sectors is omitted. The general frequency calculation equation operating with four phase-legs is concluded as where x, y, and z are given in Table 2. Every 30 • is a subsector. For example, in the last 30 • of sector 4, the frequency calculation equation can be obtained by substituting c and a into f sy . Fig. 10 shows the switching frequency variation with six phase-legs operation and four phase-legs operation at different loads in a line cycle. It can be seen that if two inverters keep operating under light load lower than 2500 W, the switching frequency will increase to above 300 kHz. Frequency limitation is necessary to avoid high turn-off loss at lighter load. However, with the proposed four phase-legs  operation mode, the switching frequency at light load significantly reduces. Therefore, the frequency variation range of the whole load condition is narrower than the conventional operation.
The whole control method can be easily implemented in a digital controller without using any additional auxiliary circuits or sensors. The control block diagram is shown in Fig. 11. The driving signals of each phase-leg in inverter 1 are always complementary based on the DPWM modulation. The only difference of inverter 1 between six and four phase-leg modes is the calculation of the switching frequency. Inverter 2 also works in DPWM mode with 180 • phase delay of the carrier wave in six phase-leg mode. However, in four phaseleg mode, the driving signal of inverter 2 is generated directly based on the clamping state. The selection criteria between the two modes is based on the output power calculated by the grid voltage and current. When the power is lower than the preset value, four phase-leg mode is used instead of six phase-leg. The specific power of the mode change can be determined by the efficiency curves shown in the experiment section. In this paper, 50% power is set as the changing point. VOLUME 11, 2023 77797 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.

IV. SIMULATION AND EXPERIMENT VERIFICATION
To verify the effectiveness of the control strategy, the simulation and experiment waveforms are illustrated in this section. The specifications and parameters of the inverter are given in Table 1. Fig. 12 shows the simulation waveform at half load in a line cycle. In sector 1, the upper envelop lines of i c1 from 0 • to 30 • and the lower envelop line of i a1 from 30 • to 60 • are well maintained at ±I bias to achieve critical ZVS. Over ZVS is achieved for phase b because the current ripple is relatively large. For the non-switching phase, such as i a1 from 0 • to 30 • , or i c1 from 30 • to 60 • , the amplitude of the current ripple is approximately equal to the grid current owing to the sharing between two clamping phase-legs. For other sectors, the current envelop lines are just duplications or mirror images of sector 1. During the clamping state, i x1 and i x2 are almost identical, so there is no circulating current.
The high-frequency current ripples in the inverter side flow through the filter capacitors and are filtered out, so the grid currents have very low distortion even with small filter parameters. The switching frequency variation is the same for all the sectors, and the frequency is continuous and smooth in a line cycle. Fig. 13 shows i a1 , i a2 , and the gate signals of phase a around 150 • . It can be seen that m a is clamped to 1 at the valley point of the carrier wave at t 5 . Before t 4 , Q 2 is normally turned on and off. Q 8 is off and i a2 is zero. At t 4 , i a1 is designed as 2 A. Both Q 2 and Q 8 are turned on synchronously. Then i a1 and i a2 are almost the same during the whole clamping state. Fig. 14 shows the photograph of the experimental prototype. It is fabricated using twelve SiC MOSFETs (C3M0060065K, 650 V, 60 m ). Six inverter side inductors are built with ferrite cores PQ3535 and Litz wire to reduce  the power loss. A three-phase common mode choke is used to suppress the common mode component of the current. The leakage inductance of this choke is also used as L g to further reduce the current ripple. DSP TMS320F28379S is chosen as the digital controller. The sampling and control frequency is set at 100 kHz.
To verify the effectiveness of the proposed method at light load, the experiment is conducted at 50% load. The steady-state experimental waveform of phase a is shown in Fig. 15. The inductor current i a2 is identical to i a1 when phase a is clamped, and i a2 remains zero for the rest of the time. The grid current i ga is in phase with the grid voltage v ga and is always the average value of the sum of i a1 and i a2 . Owing to the high switching frequency, although the inverter side currents have high current ripple, i ga still has very low distortion. The waveform is almost the same as the simulation. ZVS can always be guaranteed, for example, during the left 30 • of sector 3 and the right 30 • of sector 4, the maximum current of i a1 is kept at around 2 A. Similarly, at the left 30 • of sector 6 and the right 30 • of sector 1, the minimum current is kept at -2 A. A little variation is caused by the sampling inaccuracy. In sectors 2 and 5, phase a operates at over-ZVS condition. For other regions, ZVS is not needed because the switching state of phase a is fixed.
The ZVS waveforms of the top switch Q 1 are shown in Fig. 16 (a). The minimum value of i a1 is controlled to -2A. Thus, Q 1 can achieve critical ZVS. During the maximum and the minimum 60 • of the grid voltage, the switching state of Q 1 is fixed, so ZVS is not needed during this period (Fig. 16 (b)).   In Fig. 16 (c) and (d), the minimum current of i a1 is much lower than -2A, therefore, the voltage of the output capacitor is discharged rapidly after Q 2 is turned off, and the ZVS of Q 1 can be easily achieved.
For the bottom switch Q 2 , the ZVS waveforms are shown in Fig. 17. It can achieve ZVS if i a1 is higher than 2 A at the turn-on instant. In Fig. 17 (a), Q 2 is kept on. In Fig. 17 (b), i a1 is maintained at 2 A at the turn-on instant of Q 2 , so it can achieve critical ZVS. In Fig. 17 (c) and (d), the maximum current is much higher than 2 A, so over-ZVS is achieved.  It can be seen that the drain-source voltages of Q 1 and Q 2 always decrease to zero before the driving signals become high. Thus, ZVS can be realized for all the switches at any time. Fig. 18 shows the inductor currents and the driving signals of the two phase-legs of phase a at 150 • and 330 • . The bias current can be clearly seen in i a1 before the change of the clamping state. i a2 is always 0 before the 4 th phase-leg is turned on. With the proposed synchronous turn-on, the current difference between i a1 and i a2 is very little, resulting in good current sharing. Fig. 19 shows the dynamic response of the inverter during the load step change from 60% to 20%. It can be seen that i a1 , i a2 and i ga have quick response during the transient.  The inverter successfully switches from six phase-legs mode to four phase-leg mode. Meanwhile, ZVS can always be achieved. The switching cycle T s is generated by a digital-toanalog converter (DAC) in the DSP. It can be seen that even though the power decreases a lot, the switching frequency even decreases rather than increases. This agrees well with the above analysis.
The power loss of the inverter is mainly composed of the conduction loss and turn-off loss of the switches, the core loss, and copper loss of the inductors. The capacitors' losses are so small that can be omitted. The comparison of the inverter loss breakdown between the four and six phase-legs operation at 50% load is given in Fig. 20. With the proposed phase-shedding control method, the conduction loss and the copper loss of L 1 and L 2 increases a little because most of the power is processed by a single inverter. However, the frequency related loss including the turn-off loss, the driving loss, and the core loss decrease dramatically. For the turn-off loss and the driving loss, not only the switching frequency reduces from around 300 kHz to 100 kHz, the number of switching devices reduces from 8 to 4. Fig. 21 shows the comparison of the measured efficiency between the two control methods. With the proposed phase-shedding control, the efficiency has a greater increase as the load becomes lower. At around 50% load, the efficiencies are about the same, therefore, the phase-shedding control can be used when the load is lower than 50%.

V. CONCLUSION
In this paper, a phase-shedding control is proposed for CRP based two parallel interleaved three-phase ZVS inverters to improve the light load efficiency. DPWM and variable switching frequency are used to achieve ZVS for all the switches. The critical switching frequency can be easily calculated in a digital controller based on current ripple prediction. Compared with the previous six phase-legs operation, the switching frequency under four phase-legs operation is greatly decreased. The turn-off loss is minimized and the frequency variation range is much narrower. Inductor current sharing can be achieved between the two inverters during the clamping mode, so the circulating current is eliminated. Owing to the high switching frequency and the low inductance, the size and the cost of the inverter can be greatly reduced. Fast dynamic response is realized and ZVS can also be achieved during transients. With the proposed control strategy, higher efficiency is achieved for the two parallel interleaved inverters at light load.