A Three-Phase Frequency-Fixed DSOGI-PLL With Low Computational Effort

This paper offers a detailed analysis as well as a tuning and discretization approach of the presented frequency-fixed dual second order generalized integrator based phase-locked loop (FFDSOGI-PLL) for three-phase power systems. The method combines different single- and three-phase PLL approaches by ensuring high phase- and frequency tracking properties. The comparison with the standard frequency-variable DSOGI-PLL and three different recently published three-phase frequency and phase-angle estimation systems shows, that this approach gives a fast and stable phase and frequency detection of the grid voltage with very low computational burden. The results are applicable to, for instance, photovoltaic or frequency converters or active power filters.


I. INTRODUCTION
Synchronizing converters with the electrical grid voltage is essential for their desired tasks, e.g., for a changeable power factor [1] or for harmonic compensation with active power filters [2]. Therefore a system is needed that calculates the frequency and/or phase-angle from the measured supplying voltage, independent of distortions [3].
A phase-locked loop (PLL) is a closed-loop phase tracking method that is used for synchronization due to its simplicity, fast dynamic response, and robustness [4], [5]. It is commonly realized in dq-coordinates by Park's transformation [6] as a synchronous reference frame-PLL (SRF-PLL) which is shown in Fig. 1 [7]. Since the grid voltage can be disturbed and systematic or unsystematic frequency-and phase variations can occur, a lot of PLLs ''with enhanced filtering capability'' [8] were presented in the past. All of them have in common that an additional filter is required. Based on this, three main strategies can be identified: using an in-loop or pre-loop filter, using an infinite (IIR) or a finite impulse response-(FIR) filter and using a frequency-adaptive or frequency-fixed filter. In short, for three-phase PLLs it can be summarized that in-loop filters have to handle one signal by higher tuning effort and less stability or tracking speed, whereas pre-loop filters are confrontated with two or three signals with higher implementation complexity [8].
The associate editor coordinating the review of this manuscript and approving it for publication was Chao Zuo . The advantages of IIR filters are few calculation steps and low memory size, since they are based on digitalized analog filters or resonators in the time domain. The FIR filters, which are based on calculations in the frequency domain, can detect disturbances more precisely, but have a higher complexity. Moreover, the memory size increases if the step size decreases due to the storage of a half or full period [9]. Frequency-variable filters need the frequency from either the PLL itself or from an additional system. The former leads to reduced dynamics and the latter to higher implementation and computation efforts. By using frequency-fixed filters, amplitude and phase errors occur which is why an additional recalculation is needed [8], [10].
A frequency-variable SOGI-PLL was presented first in [25] and analyzed in detail in [27]. The ''Frequency-fixed SOGI-PLL'' (FFSOGI-PLL) approach was introduced in [28] while the ''Derivative Elements-PLL'' (DE-PLL) was presented in [35]. These single-phase PLLs (SOGI-PLL, FFSOGI-PLL and DE-PLL) were compared and discussed in [29]. For three-phase systems a frequency variable method was introduced as ''Dual SOGI-PLL'' (DSOGI-PLL) in [26], where two SOGI-structures generate four output signals from the input voltage's αand β-component. With these signals it is possible to calculate the voltage's positive sequence (PS). Frequency-fixed equivalents were presented in [30] as a ''Decoupled DSOGI-PLL'' and in [31] as a ''Frequencyfixed DSOGI-PLL'' (FFDSOGI-PLL). Both approaches use a phase compensation for off-nominal frequencies. The first compensates in front of the PLL and, in consequence, it is not possible to determine the PS without additional effort. The second compensates the phase error at the end of the PLL by retaining the PS with an amplitude error compensation [31], which is why it is a noteworthy approach. However, an analytical description as well as a tuning approach and a detailed comparison with a performance test is missing. This paper's aim is to provide a fast and stable frequency and phase-angle estimation system which yields persuasive results compared to other recently puplished approaches. For this purpose, a detailed analysis of the FFDSOGI-PLL and a disturbance suppression based tuning approach with a concluding experimental comparison to advanced PLLs with IIR and FIR filters are given. Starting with the principle of the DSOGI-PLL in section II, section III will introduce a detailed analytical description, a tuning and a digitalization approach of the FFDSOGI. This will be compared with the DSOGI-PLL for different experimental test scenarios in section IV. The results of the FFDSOGI-PLL in comparison to three advanced frequency and phase-angle estimation systems will be discussed in section V and summarized in section VI.
The main contribution of this paper is an in-depth mathematical analysis of the three-phase FFDSOGI-PLL, a tuning approach of the SRF-PLL which is a direct outcome of the mathematical model, a discretization approach for a fast implementation and a comparison to other PLL systems with the focus on tracking behavior and computational effort.

II. FREQUENCY-VARIABLE DSOGI-PLL A. SRF-PLL WITH ANS
The SRF-PLL in Fig. 1 uses two orthogonal input signals v α and v β , which will be transformed with an estimated phase-angleθ to a representation of the difference between the real phase-angle θ andθ. Controlling this value yields the estimated frequencyω, where its time integration providesθ =ωt. For a better performance, an amplitude normalization scheme (ANS) and a feed-forward component ω ff can be added [8], [36]. A low-pass filter for the ANS is optional and will not be applied in this paper. The SRF-PLLs performance depends on the accuracy of the input, the dynamic properties and the stability criteria of the whole system [8].

B. BASICS OF SOGI
In Fig. 2 a SOGI withω as a tuning frequency and k as damping factor is given. Its closed-loop transfer functions can be determined by The bode plots of G(s) and G ρ (s) in Fig. 3 show example values of k. As can be seen, v ′ and v ′ ρ are exactly in phase and quadrature phase with the input and have no amplitude losses ifω matches ω. Higher frequencies and, for k < 1 also lower frequencies, will be damped (compare G ρ (s) in Fig. 3). Therefore it receives attention as an SRF-PLL prefilter. For a detailed analysis, a sinusoidal excitation of v(t) = sin(ωt) can be assumed. After Laplace transformation of v(t), multiplying with (1a) and (1b) respectively and inverse Laplace transformation with some rearrangements, the SOGI yields:  with The Parameters A, φ 1 and φ 2 affect the amplitudes and phases of the oscillating terms which converge to zero with a time constant τ = 2/kω. In steady-state conditions (ω ∼ = ω, t ≫ τ ) the phase-shifting term δ becomes zero and the amplitudes of v ′ (t) and v ′ ρ (t) are equal. Note that a smaller k leads to higher damping of harmonics, but also to a higher settling time of transients.

C. POSITIVE SEQUENCE CALCULATOR
In case of unbalanced grid conditions, the PS of the supplying voltage has to be determined. A positive sequence calculator (PSC) uses the principle of symmetrical component calculation by Lyon [37], which can be expressed as For the SRF-PLL, the PSC has to be applied in α and β coordinates. The multiplication of the Clarke transformation with (4) and Clarke's inverse leads to Instead of shifting each phase by 120 • , a rotation of 90 • of v α and v β suffices for calculating their positive sequence [26], and from (5) follows A SOGI offers this rotation with harmonic damping at once and can be used for the PSC. The whole system, including two SOGI as pre-filters, the PSC and the SRF-PLL with ANS, is presented in [31], Fig. 2.

III. FREQUENCY-FIXED DSOGI-PLL
The idea of the frequency-fixed approach is to replace the tuning frequency ω by a fixed ω 0 while compensating any phase errors that may occur. The resulting model is depicted in Fig. 4 and explained in the following. To examine the behavior of the FFDSOGI-PLL the signals v α (t) = V α sin (ωt) and v β (t) = − V β cos (ωt) are assumed to excite both SOGI, which are tuned to a fixed frequency ω 0 . Applying this to (1a) and (1b) gives after mathematical manipulations VOLUME 11, 2023 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.
B. Hoepfner, R. Vick: Three-Phase Frequency-Fixed DSOGI-PLL With Low Computational Effort with By comparing (8a) with (8b) and (8c) with (8d) it can be determined that their amplitudes V ′ FF are not equal in steady state. Actually, if ω differs from If a frequency drift occurs with unbalances, different PSC amplitudes and, as a consequence, second order ripple would appear in the SRF. To handle this problem, an amplitude adjustment equal to [28] will be suggested by multiplying the quadrature signals withω/ω 0 .

A. POSITIVE SEQUENCE WITH FFDSOGI
With the suggested amplitude adjustment and by applying (7) -(9e), the output signals of the PSC are Assumingω = ω + ω, (10) can be expressed as: where Due to irrelevance of the exact expressions of the oscillating and decaying terms, both are summarized as α (t) and β (t) and decay to zero with a time constant τ p = 2 kω 0 . As can be seen from (11a) and (11b) with (9e), a phase shift δ FF is present if the input frequency ω does not match ω 0 .
In addition, if the estimated frequencyω is not equal to ω, two terms with a dependency of ω 2ω occur, which would lead to unbalances if the input voltage is also unbalanced. Furthermore, the amplitudes of both expressions (11a) and (11b) depending on the frequency difference as can be seen in (12). If a recalculation of the amplitude is required, (12) can be approximated with for small deviations of ω over ω 0 . The error of this approximation is depicted in Figure 5.

B. ANALYSIS OF THE FFDSOGI-PLL
By applying the Park-transformation with an αto q-axis alignment to (11a) and (11b) withθ ϵ =ωt − δ FF and θ FF = ωt − δ FF respectively, the d-and q-component can be calculated as: sin ω +ω t − 2δ FF (15c) VOLUME 11, 2023 and the amplitudes of the decaying terms are summarized as d (t) and q (t). Under locked conditions cos(θ FF − θ ϵ ) ∼ = 1 and sin(θ FF −θ ϵ ) ∼ = θ FF −θ ϵ respectively, for which v d (t) yields the amplitude and v q (t) the systems phase error information. Note that unbalances with a frequency drift lead to disturbances D ω (t), where their influence is marginal because of ω ≪ 2ω. Moreover, higher frequency conducted distortions respectively harmonics could lead to off-nominal conditions. To examine their influence it is useful to assume a positive sequence harmonic of order h with V h sin(hωt + φ h ) and −V h cos(hωt + φ h ). Processing this to equations (8a)-(14b) results in respectively, if ω ∼ =ω ∼ = ω 0 . From (16a) and (16b) it is obvious that, e.g., a PS of a third-order harmonic 1 would lead to second-order ripple. Note that a negative sequence yields a h + 1 oscillation with a h−1 2 amplitude. The frequency drift and the harmonic term can be summarized to a combined distortion can be replaced by d or q. Because of the low-pass filter characteristic, a phase step will be delayed with τ p . From (14b) it can be seen that θ FF −θ ϵ will be summed up with D q (t). With respect to the ANS, the q-axis can be expressed in the Laplace domain as [28] V q (s) = (θ FF (s) − θ ϵ (s)) + D ′ q (s) with θ FF (s) = θ (s) 1 1 Four wire systems can contain unbalanced third-order harmonics. From (9e) it is known that θ FF and, hence, θ ϵ includes a phase drift of −δ FF if ω does not match ω 0 . Since the European standard EN 50160 strictly regulates the frequency with a maximum deviation of 2.5 Hz and a nominal frequency of 50 Hz, (9e) can be expressed as and can be recalculated by replacing ω withω or due to better harmonic behavior, with the integrational control part ω i as suggested in [28] and Fig. 4. The error between the exact and the approximated solution of δ FF is depicted in Fig. 6. Summing up the recalculated δ FF,i with θ ϵ yields the estimation of the real phase-angleθ. Since ω i has a settling time, the phase compensator affects the phase-angle estimation with as shown in [29]. By comparing the analysis with [28] and [29] it is obvious that the FFDSOGI-PLLs dynamic behavior is quite similar to the one of the single-phase PLL. Fig. 7 shows the small-signal model which can be derived from (18), (19) and (21). It is identical to the one of the FFSOGI-PLL [29].

C. DIGITALIZATION OF FFDSOGI
For discrete systems with a step time T s , the transfer functions (1a) and (1b) have to be converted from Laplaceto Z-domain. For this purpose it is common to use either the explicit or implicit Euler or the Tustin method. It is known from [25] that the latter, in which the frequency parameter is replaced by s = ( T s 2 z−1 z+1 ), yields the best results. Applying this to (1a) and (1b) with a substitution ofω by ω 0 yields where b 0 = 2kω 0 T s 2kω 0 T s + (ω 0 T s ) 2 + 4 With respect to the amplitude adjustment, a discrete implementation scheme, depicted in Fig. 8, can be derived. Note that all coefficients in (24) are constants. This represents a first advantage over the original SOGI, since its coefficients have to be calculated during every computation cycle. However, it will be slightly mitigated due to the remaining multiplication with ω i and the phase compensator's calculation.

D. TUNING OF THE FFDSOGI-PLL
From Fig. 7 the closed loop transfer function of the FFDSOGI-PLL is determined with The third-order polynomial represents a stable system, if the following Hurwitz criteria are fulfilled [28]: Since τ p > 0 and negative values of k p and k i are nonsensical, it can be concluded that the system is always stable. This is a second, distinct advantage over the DSOGI-PLL. By separating the pre-filtering-and rearranging the remaining term into the standard second-order form, (25) can be rewritten as It is common to set the damping term ζ = 1/ √ 2, which ensures a tradeoff between overshot and settling time. In [28] a natural frequency of ω n = 2π 32 Hz was presented. However, this leads to poor behavior during harmonic excitation [29]. If a defined attenuation of a specific harmonic order Att h at a frequency hω is needed, ω n can be determined by solving which can be obtained by (16b), (17) and (26). By comparing (1a) with (26) it can be derived that k = 2ζ = √ 2 would be a suitable choice. However, with a closer look at Fig. 3 it becomes clear that k < 1 yields to a slightly DC-offset damping, which is another small advantage over the DSOGI-PLL. 2 If a third harmonic order has to be attenuated with Att 3 = −20 dB and a pre-filter gain of k = 1/ 2 as suggested in [26] leads to ω n = 2π16.877 Hz. The small signal models simulation result for a phase jump of 20 • with the former parameter set is depicted in Fig. 11a.

IV. EXPERIMENTAL RESULTS
Following the detailed analysis of the FFDSOGI-PLL, this section compares it to the DSOGI-PLL from [26] by implementing the digital conversion from Fig. 8 in a TI-TMS320F28379D digital signal processor. An internal voltage source loop was programmed to generate four test scenarios: 1) a phase jump of 20 • (Fig. 11a), 2) a frequency jump of 2.5 Hz (Fig. 11b), 3) a 20 % PS third harmonic injection (Fig. 11c), 4) a 80 % voltage sag (Fig. 11d), The source's results are read sequentially from two FFDSOGI-and one DSOGI-PLL loops with chosen sets of parameters FF,1: k = 1/ √ 2 and ω n = 2π21.975 Hz, FF,2: k = √ 2 and ω n = 2π16.877 Hz, DSOGI: k = 2.1 and ω n = 2π21.885 Hz [27] 3 and an overall sample time of 50 µs. The source voltage, the source and estimated frequency as well as the phase-angle difference (θ −θ) are shown in Fig. 11. Additionally, Fig. 11a includes the simulation results of the small signal model of  2. Fig. 11a reveals that the experimental result nearly perfectly matches the simulation from Fig. 7, which is a convincing verification of this paper's analysis.
4. By determining the execution time, it can be observed that both FFDSOGI-PLLs are faster, since they process with 1.78 µs and the DSOGI with 2.13 µs.

V. COMPARISON WITH ADVANCED 3∼ PLL
Section IV show that the frequency-fixed approach is very fast and stable. Therefore, the FFDSOGI-PLL (FF,1) will be compared with advanced three-phase frequency and phase angle estimation systems which were published in the recent past and briefly presented in the following.
The ''enhanced SOGI frequency-locked loop PLL'' (eSOGI-FLL-PLL) in [38] provides a DSOGI-related approach where two SOGI structures yield four output signals to apply a PSC. However, instead of the PLL's estimated frequency, an extra FLL was applied to the SOGI tuning and a variable gain improves its transient performance. Another approach is the ''enhanced transfer delay frequency locked loop'' (ETD-FLL) from [39]. By using relationships between the grid voltage and its delays, a doubled structure yields four signals to calculate the PS equal to the FFDSOGI-or to the eSOGI-FLL-PLL. However, it was not specified how to estimate the phase-angle which is why the inverse tangent was used. The ''cascaded delayed signal cancellation frequency detection method'' (CDSC-FD) from [40] uses multiple cascaded transfer delays with adjustable delay length as filter. For that, an additional frequency detector will be applied. To determine the phase-angle from the filtered output signals, a notable inverse tangent approximation was presented.
These PLL methods are tuned to give a tradeoff between fast response and high disturbance rejection which is why they are comparable to the presented tuning method.
The comparison will be performed in the same manner as in section IV, however, due to the increased computational burden, with a sample time of 200 µs (f s = 5 kHz) and with four more test scenarios to get a more comprehensive validity 4 : 1-4) same scenarios as in section IV (Fig. 12a-12d),

5)
unbalance of +15 % and -80 % (Fig. 12e), 6) two DC-offsets of ±10 (Fig. 12f), 7) 25 Hz/s frequency ramp (50-52.5 Hz) (Fig. 12g), 8) scenario 5) with a frequency jump of 2.5 Hz (Fig. 12h). Moreover, a performance test of all systems with a sample frequency of f s = 5 kHz and 10 kHz was carried out. The experimental setup is depicted in Fig. 9 and the results are presented in Fig. 10. It will be illustrated that the FFDSOGI-PLL is the most efficient system and that all SOGI systems are distinctly faster than the delayed one. The latter shows a dependency on f s which can be explained with more delay steps that will be needed for the same time delay. The experimental results can be interpreted as follows: VOLUME 11, 2023 34939 Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. Fig. 12a, it can be ascertained that the settling times for the frequency of the FFDSOGI and eSOGI are close together, where the ETD is faster and the CDSC slower. The phase-angle estimation of the eSOGI and CDSC have long settling times. The ETD shows the best results, followed by the FFDSOGI.

1) By observing
2) The frequency jump (Fig. 12d) shows again a fast frequency decay for the ETD, followed by the FFDSOGI. The eSOGI is slightly and the CDSC much slower. The ETD shows the best results for the phase-angle estimation whereas the eSOGI and the CDSC (for the back step) have a long settling time. The FFDSOGI is a good compromise among the systems.
3) The delayed systems yield full harmonic cancellation after decaying, whereas the SOGI based systems have remaining oscillations (Fig. 12c). The eSOGI has less damping in frequency and a slight steady-state error in phaseangle estimation.

4)
Observing scenario (Fig. 12d) reveals a large frequency deviation and phase-angle oscillations of the ETD. The other systems have similar settling times, whereas the CDCS has less overshoots. Fig. 12e again shows a poor behavior of the ETD. The eSOGI frequency oscillates and the CDSC settling time is long. The FFDSOGI shows the best results. 6) With its full DC-Offset cancellation, the ETD yields the best results followed by the FFDSOGI (for the frequency, Fig. 12f). For the phase-angle estimation the eSOGI has a slightly better damping than the FFDSOGI. The CDSC shows a poor DC behavior.

7)
A similar frequency behavior can be seen for both SOGIs in Fig. 12h, whereas the CDSC jumps and the ETD oscillates with less steady-state error.
8) The unbalances with a frequency drift yields the combination of the frequency and phase-angle estimation results. The ETD shows a large frequency deviation and phase-angle oscillations. The eSOGI has an unacceptable phase-angle settling time. The CDSC shows the best results followed by the FFDSOGI.
In summary, it can be stated that the FFDSOGI-PLL yields good results for all test scenarios by retaining a very low computational effort which is why it is a superior choice for applications with high computational load.

VI. CONCLUSION
An in-depth analysis of a three-phase frequency-fixed DSOGI-PLL has been presented in this paper. From an exhaustive mathematical description a parameter-tuning and a digitalization approach was given. The experimental scenarios showed that the FFDSOGI-PLL has certain advantages towards to the standard DSOGI-PLL and advanced frequency and phase-angle estimation systems which where published in the recent past. The presented PLL can be tuned with the focus on harmonic suppression by retaining an improved dynamic behavior.
It was demonstrated and reasoned that the FFDSOGI-PLL is the fastest system for micro controllers which yields persuasive results in all test scenarios as shown in Figures 10 and 12. Especially if phase-or frequency jumps, voltage sags or unbalances occurs, the FFDSOGI shows good results. To enhance the tracking performance of this PLL, further studies could focus the DC-rejection capability which is comparable to other methods but still improvable. Furthermore, like all presented PLLs, this method is not able to maintain the frequency and phase-angle if a permanent voltage loss occurs as a result of a grid fault. However, the FFDSOGI-PLL can unhesitatingly be used as a frequency and phase-angle detection system for three-phase applications, especially with high computational burden like active power filters or photovoltaik converters with additional grid services.
The investigations of this paper also reveals, that FIR methods (like the presented ETD and CDSC or others like the DFT/SFT or MAF based PLLs) can provide notable disturbance rejection results. However, due to the storage of a half or full period of either the fundamental-or different harmonic components, a higher computational burden is given, which can be critical for micro controllers. In addition, with increasing sampling frequency, it needs increasing number of delay steps for the calculation which leads to a dependency of computation time and sampling frequency.
If a grid connected inverter with high switching and calculation frequency needs a robust and fast phase-tracking method with low computational burden, this paper offers a persuasive solution with the FFDSOGI-PLL.