220-240-GHz High-Gain Phase Shifter Chain and Power Amplifier for Scalable Large Phased-Arrays

This paper focuses on the design aspects of the key components for a scalable phased-array system over the 200 GHz frequency range. A high-gain phase shifter chain for 220 to 240 GHz frequency range and a high-gain power amplifier (PA) with a high output power are designed in a 0.13-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> SiGe BiCMOS technology. The phase shifter chain includes a low-noise amplifier (LNA), a vector modulator phase shifter (PS), and a gain-enhancing amplifier. The LNA is a five-stage cascode design. The vector modulator core is realized by two variable gain amplifiers based on the Gilbert cell architecture. A four-stage cascode design is used for the gain-enhancing amplifier. The phase shifter chain shows a measured gain of 18 dB at 230 GHz with a <inline-formula> <tex-math notation="LaTeX">$360 {\mathrm { ^{\circ}}}$ </tex-math></inline-formula> phase tuning range and more than 10 dB of gain control. The chip achieves a minimum measured noise figure of 11.5 dB at 230 GHz and shows a wideband noise characteristic. The complete phase shifter chain chip consumes a dc power of 153 mW and occupies a 1.41 mm2 area. A high-power PA that is critical for a large phased-array system is designed. This paper presents a unique 4-way power combining technique utilizing a differential quadrature coupler. The realized balanced PA occupies an area of 0.67 mm2 and shows a measured peak gain of 21 dB at 244 GHz. The PA consumes 819 mW of dc power and delivers a maximum saturated output power <inline-formula> <tex-math notation="LaTeX">$(P_{sat})$ </tex-math></inline-formula> of 7.1 dBm at 244 GHz and more than 4.3 dBm of <inline-formula> <tex-math notation="LaTeX">$P_{sat}$ </tex-math></inline-formula> from 230 to 255 GHz.


I. INTRODUCTION
Millimeter wave (mm-wave) and terahertz (THz) bands are extremely interesting regions of electromagnetic radiation for applications such as security and medical imaging, space radiometry, and ultra-high-speed wireless communications [1]. In communications, the new standard from 5G and beyond emphasizes smaller cell sizes for wider data bandwidth per user and can feature wireless data rates of around 100 Gbit/s [2]. Even with a highly efficient modulation technique, a significant capacity increase to multi-gigabit The associate editor coordinating the review of this manuscript and approving it for publication was Yiming Huo . or even terabit wireless transmission requires larger bandwidths. However, bandwidth is bounded due to extremely limited spectral resources in the conventional frequency range. Thanks to the 200-300 GHz frequency band that can offer advantages such as providing a smaller system size with a smaller antenna aperture, thus improving the resolution of the imaging system, as well as providing high absolute bandwidth for high-speed wireless communications [3].
Traditionally, THz and upper millimeter-wave frequency (200-300 GHz) front-end circuits and systems are mainly implemented using III-V compound semiconductor technologies [4], [5], [6], [7], [8]. Due to recent improvements in silicon-based technologies, both CMOS and BiCMOS offer VOLUME 11, 2023 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ higher throughput and lower cost as compared to III-V processes, which enable the possibility of integrating circuits and systems at 200-300 GHz [9]. Recently, SiGe HBT with f t of 300 GHz and f max of 500 GHz has been presented in [10]. In the last decade, the number of circuits and systems in the 200-300 GHz using CMOS and BiCMOS has increased gradually. Several transceivers based on silicon technologies have been reported in different articles, such as a 220 and 320 GHz sub-harmonic receiver with integrated LO is presented in [11] and [12]. Also, a fully integrated CMOS transceiver in 65-nm CMOS for wireless chip-to-chip communication at 260 GHz has been presented in [13].
Although several transceivers have been demonstrated for frequencies from 200 to 300 GHz, designing a high data rate transceiver still remains a challenging task due to high path loss, a high noise figure(NF) of the receiver, and a low output power of the transmitter. A phased-array technique can be used to overcome these challenges at these frequencies.
Along with beamforming, phased-arrays have the advantages of higher effective isotropic radiated power (EIRP) in the transmitter and a higher signal-to-noise ratio (SNR) in the receiver [14]. Recent works for phased-array system-on-chip around 100 GHz have been demonstrated in [15] and [16]. A 280-GHz power generation and beam-steering array are reported in [17]. In [8], a 320-GHz 1 × 4 fully integrated phased-array transmitter using SiGe BiCMOS technology is demonstrated. A 220-250 GHz four-element RF phaseshifting array is presented in [18]. However, quite a few phased-array circuits are reported that could be used to demonstrate a large array in 200-300 GHz.
The main challenge with a large phased-array system at higher mm-wave frequencies is the lack of output power required to drive a large number of arrays in the transmitter and achieve a low noise figure with high gain in the receiver. Although the performance of both CMOS and BiCMOS has improved in recent years, the gain at higher frequencies remains very limited. So, it is evident that for building a large phased-array receiver system, the phase-shifting path needs to have a high gain and a low noise figure to have better performance as a receiver. Again, the phase-shifting path needs to provide high output power for building a large phased-array transmitter system. This work presents a high-gain phase shifter (PS) chain circuit suitable for a large phased-array system that includes a low-noise amplifier, a phase shifter, and an amplifier at 220-240 GHz. This phase shifter chain can be used both in the transmitter and the receiver. Moreover, a separate power amplifier can be added to this PS chain if more transmit power is needed when it is used as a transmitter. The phase shifter circuit achieves a high gain of 28 dB at 220 GHz. At 230 GHz, it shows a gain of 18 dB with a 360 • phase tuning range and 10 dB of gain control with a noise figure of 11.5 dB. This work also presents a power amplifier that uses a unique power combination technique at 240 GHz and can be used with the phase shifter chain circuit to provide high output power. The power amplifier shows a measured peak gain of 21 dB and a P sat of 7.1 dBm at 244 GHz and delivers a saturated power above 4.3 dBm from 230-255 GHz.
This paper starts with a detailed overview of how the designed phase shifter chain circuit and power amplifier can be used to build a large RF phase-shifting transmitter and receiver system in Section II. Section III describes the circuit design of individual blocks and the measurement results of the phase shifter chain. In Section IV, the detailed design procedure and the measurement results of the power amplifier are presented followed by the conclusion in Section V.

II. SYSTEM OVERVIEW
Phase shifters are essential components in a phased-array system. A phased-array system consists of several antennas that can direct the beam in a specific direction. By providing high gain and high output power in the phase shifter path, a large phased-array system can be built. Fig. 1 shows a block diagram of the proposed N-path transmitter and receiver RF phase-shifting system based on the designed phase shifter chain and power amplifier. In both the transmitter and the receiver, the same phase shifter chain is used. Fig. 1a represents the N-path RF phase-shifting transmitter. Each path consists of a phase shifter chain and a separate PA for high output power to the antenna. All the N-paths are connected to point A in Fig. 1a and are driven by a driver PA. In this proposed architecture, the same circuit is used as output PA and driver PA. In the case of an N-way split from point A to point B, the power at point B is 10·log(1/N) dB less than the power at point A. Depending on the increase or decrease of N, the power difference between points A and B will increase or decrease, respectively. Mathematically, if the power at point D is P D , the gain of the output PA is G PA and the gain of the PS chain is G PS , then the power at point B is: From equation (1), it is seen that if the G PA and G PS are higher, then the required power at point B is decreased. It is found from our PA design and also from literature [19] that a +5 dBm output power from PA is feasible in the 225-250 GHz range. In the RF phase-shifting transmitter path, if we want to feed the antenna with a +5 dBm power, then the power at point D will be +5 dBm. If the gain of the output PA (G PA ) is 20 dB, then the required power at point C is −15 dBm. Again, if the gain of the phase shifter chain (G PS ) is 18 dB, the power needed at point B will be −33 dBm. Now, if we want to build a 1024-element RF phase-shifting transmitter array with −33 dBm power at point B, the required power at point A will be +2 dBm according to the calculation of N-way splitting and considering a typical power division ratio of 3.5 dB from a 2-way splitter [18] around 230 GHz. So, if we use a PA that can deliver +5 dBm output power as the driver PA then it will drive the 1024-element RF phase-shifting transmitter array according to our calculation. Otherwise, if the gain of the phase shifter chain (G PS ) and gain of the PA (G PA ) are very low, then we need a very high power driver PA, which is difficult to realize at 220-250 GHz for a similar number of elements in the RF phase-shifting transmitter array. Fig. 1b shows an N-path RF phase-shifting receiver system where all the RF paths are combined at point O. In this architecture, the gain and noise figure of the phase shifter chain define the number of paths that can be connected. The number of parallel paths can be connected as long as the total noise figure does not degrade compared to the noise figure of a stand-alone phase shifter chain. Considering all the losses of the combiner and adding an amplifier and mixer after point O, the total noise figure of the system can be calculated according to Friis's formula for noise factor as in equation (2).
Here, F PS and G PS are the noise factor and the gain of a single phase shifter path, respectively. L represents the total loss due to the RF power combiners. F A and G A are the noise factor and gain of the amplifier, and F Mix is the noise factor of the mixer after point O. Fig. 2 shows the simulated noise figure for different gains for a single phase-shifter chain considering the loss of combining the 1024 paths and the characteristic of the mixer at 240 GHz as in [20]. From Fig. 2, it is found that the NF of the receiver system remains similar to the stand-alone phase shifter chain if the phase shifter chain can provide more than 20 dB gain, and the NF of the system will degrade by around 5 dB if the gain of the single phase shifter chain drops from 20 dB to 5 dB. Again, it is also seen from Fig. 2 that if we add a high-gain amplifier as in [21] after point O, then it can reduce the gain requirement of a single phase shifter chain and thus significantly reduce the power consumption of the RF phase shifting receiver system. So, from the analysis, it is evident that a large receiver array is possible if the phase shifter path can provide a high gain and a low noise figure.

III. PHASE SHIFTER CHAIN
The phase shifter chain consists of an LNA and phase shifter followed by a gain-enhancing amplifier. The block diagram of the phase shifter chain is given in Fig. 3.

A. LNA DESIGN
Since the LNA is the first block in the receiver chain, the gain and noise figure of the LNA play a critical role in determining the noise figure of the whole receiver system. Therefore, low noise figure and high gain are major requirements for the LNA design over the frequency band of interest. Common emitter (CE) and cascode topologies are the most popular topologies for LNA design. It has been seen that VOLUME 11, 2023  a CE topology can provide a lower noise figure compared to common-base (CB) and cascode topologies. However, at frequencies close to f t and f max , the gain of the CE amplifiers drops significantly. Usually, cascode amplifiers provide higher gain but have a degraded noise figure compared to a CE amplifier. It is seen in [21] that the noise figure is almost 2 to 2.5 dB better in CE at 220-260 GHz compared to cascode topology. However, cascode's maximum available gain (MAG) becomes significant (6 to 7 dB higher MAG compared to a CE). Also, if we compare the NF of a cascode to the NF of a two-stage CE, the NF is only 1 to 1.2 dB higher in a cascode. Therefore, the cascode topology was chosen for this design since the cascode topology provides better performances in terms of gain, isolation, and 3-dB bandwidth for the given technology.
The design goal for the LNA was to find the transistor size for low noise figure and higher gain. Source impedance points for minimum noise figure for different transistor sizes in a single-stage cascode amplifier were examined for choosing the correct size. In this technology, it is seen that a transistor with an emitter size of 6 × (0.90 × .07) µm 2 provides a better source impedance point with higher gain for better matching. Based on this transistor size, we have designed a stand-alone 7-stage prototype LNA. Fig. 4 shows the schematic of a single stage of the designed LNA. In this 7-stage amplifier, the bias connections for the V cc V b2 and V b1 are provided separately. The detailed design of the 7-stage LNA can be found in [21]. Fig. 5, Fig. 6 and Fig. 7 show the chip photograph, S-parameters, and noise figure of the 7-stage LNA,  respectively. The chip size is 0.45 mm 2 . The 7-stage LNA achieves a measured gain of 28.5 dB and 11.7 dB of measured noise figure at 237 GHz. The comparison of the LNA with other published LNAs could be referred to in [21]. This LNA demonstrates the highest gain and highest figure of merit in terms of GHz/mW in the frequency range of 240 GHz.
In the phase shifter chain LNA design, the transistors were optimized with high bias compared to the prototype 7-stage LNA, and bias was realized with current mirror biasing. As a result, a high gain could also be obtained if we reduced the number of amplifying stages compared to the stand-alone 7-stage LNA. Also, because we have a gain amplifier after the phase shifter in the phase shifter chain, the gain requirement from the LNA can be relaxed because LNA and gainenhancing amplifier can now control the overall gain of the chain. Considering these facts and the reduced chip area, a 5-stage cascode design was chosen for the LNA in the phase shifter chain.
Every cascode stage schematic in this 5-stage LNA is similar to the schematic shown in Fig. 4, with each transistor having an emitter size of 6 × (0.90 × .07) µm 2 . For optimization, the source impedance was selected for a low noise figure in the first stage and for a higher gain in the other stages. The output impedance of each stage was transformed into the source impedance of the next stage in such a way that the first stage could provide a low noise figure and other stages could provide a higher gain. In this way, all five stages   were optimized for higher gain while maintaining a low noise figure. The input matching, interstage matching, and output matching were realized by transmission lines and capacitors. A transmission line, equivalent to a series inductance, has been placed between the CE and CB stages in the cascode for gain enhancement and improving the NF of the amplifier.
All the transmission lines, capacitors, and other connections were EM simulated for the post-layout simulation results. The unconditional stability of the amplifier was checked by stability factor (K) simulation. Fig. 8 shows the overall amplifier's simulated stability analysis. The simulated K factor value was greater than 1 in the 1-300 GHz range, which indicates the unconditional stability of the designed five-stage cascode LNA. We also simulated the stability measure (B1) and Mu factor, which ensure the stability of the 5-stage LNA.
The 5-stage LNA occupies an area of 0.29 mm 2 . Fig. 9 and Fig. 10 show the post-layout simulation result of S-parameters and noise figure of the 5-stage LNA, respectively. The bias current is 35 mA from a 3.4 V supply. From Fig. 9, it is found that 5-stage LNA has a peak gain of 28 dB, and input and output matching are better than 10 dB from 230-250 GHz. The simulated NF of the 5-stage LNA has a good match with the measured NF of the 7-stage LNA.

B. PHASE SHIFTER DESIGN
The simplified block diagram of a vector modulator phase shifter is shown in Fig. 11. The RF input signal is converted to a differential signal using a Marchand balun. A differential signal is fed to the differential I/Q generator. A compact, low-loss, and wideband differential coupler is used as the differential I/Q generator in this work. The differential I/Q generator creates differential in-phase and quadrature signals. The differential I and Q signals are fed to the differential VGAs. The differential output is the vector sum of the outputs of I and Q VGAs. The differential signal is converted back to a single-ended signal by a Marchand balun.
Although the Marchand balun is generally large, it was employed because of its wideband characteristics. The structure is made smaller by bending the lines. Thus, it becomes feasible to use this balun in our design. The Marchand balun is made of two sections of coupled lines, each with a length of λ/4 at the design frequency. The topmost metal layer is used to realize the Marchand balun, and metal 3 is used as the ground plane. A 3D layout view of the Marchand balun is shown in Fig. 12. The Marchand balun is designed and optimized for a 50 system with ADS momentum. The optimized line spacing and width are 2 µm and 7 µm, respectively. The simulation results are shown in Fig. 13. The balun provides less than 0.6 dB of amplitude mismatch from 200 GHz to 260 GHz and less than 1 • of phase imbalance from 200 GHz to 280 GHz.
A low-loss, compact, and wideband differential coupler operating from 180 GHz to 280 GHz is used as the differential I/Q generator in the phase shifter. The physical implementation of the differential coupler is shown in Fig. 14. A differential signal is fed to Port 1, and I/Q output signals are taken from Port 2 and Port 3. The detailed design of the wideband VOLUME 11, 2023   differential coupler is presented in [22]. The main design parameters used to estimate the dimension of the differential coupler are the width of the conductors W , the spacing between the adjacent lines S, and the line length L. Top metal 1 and metal 5 layers are used to realize the coupler. A solid metal layer is placed beneath the whole coupler so that the structure is not exposed to the lossy silicon substrate. After simulation and optimization, the values are finally found to be W = 4 µm, S = 11 µm, and L = 160 µm. The realized coupler shows a very wideband response. The simulated results are shown in Fig. 15. The coupler shows less than 1 dB of amplitude imbalance from 180 GHz to 280 GHz and less than 5 • of phase imbalance from 180 GHz to 260 GHz. The vector modulator consists of two identical VGAs. The VGA is designed based on the Gilbert-cell topology. The vector modulator core is shown in Fig. 16. In this configuration, the gain of the differential I signal is controlled by the analog control signals (V c1 , V c2 ). Transistors (M 3 -M 6 ) are used for the gain control stage of the Gilbert cell. Input transistors M 1 and M 2 work as a transconductance stage. The input of the Gilbert cell is matched to the output of the differential coupler by a 100 differential transmission line, TL 1 . TL 2 -TL 5 are small lines for connecting the transistors. The I and Q signals with variable amplitudes are combined to obtain the desired signal through a symmetrical matching network that consists of differential transmission lines TL 7 -TL 11 . The differential lines TL 7 and TL 11 combine the I and Q signals by reactive matching. TL 9 is a quarter-wave short-circuited transmission line that is used for biasing. TL 8 and TL 10 work as interconnects and form a matching network with capacitor C 3 that matches the impedance of the Marchand balun. The vector modulator draws 15 mA from a 3.5-V supply.
A stand-alone compact and wideband vector modulator phase shifter operating from 200 GHz to 250 GHz is designed separately for testing the phase shifter. The chip micrograph of the stand-alone phase shifter is shown in Fig. 17. It occupies a core area of 0.09 mm 2 . This phase shifter is measured separately, and a detailed measurement procedure can be found in [22]. Fig. 18 shows the measured and simulated S-parameters of the designed phase shifter. Simulated and measured S-parameters are in fairly close agreement with   each other. The measured conversion gain of the phase shifter is −10.3 dB for the maximum gain setting at 230 GHz with a 3-dB bandwidth of 40 GHz. Both input and output matching are better than 10 dB from 220 GHz to 260 GHz. Fig. 19 shows the measured polar plot of the S 21 at 230 GHz. The phase shifter shows 360 • phase control and 10 dB of gain control. The maximum gain with a full 360 • phase control range is −17 dB. Other measured and simulated results of this phase shifter and a comparison of the performance of this phase shifter with that of other published phase shifters in the same frequency range can be found in [22]. This stand-alone phase shifter shows very wideband performance and uses an I/Q generator, which is the best I/Q generator considering the area, loss, and bandwidth.

C. GAIN ENHANCING AMPLIFIER DESIGN
In order to compensate for the losses introduced by the phase shifter and also to further increase the gain and output power capability of the phase shifter chain, an amplifier is designed and placed after the phase shifter. Fig. 20 shows the schematic of the amplifier. The amplifier consists of four cascode stages with different transistor sizes in each stage. The first two stages are optimized for higher gain, and the last two stages of the amplifier are optimized for maximum output power. For optimization, we performed a load pull simulation for each stage. From the load pull simulation, we selected an optimum load impedance based on gain or power for a certain stage. After selecting the load impedance, the source impedance was transformed in such a way that the previous stage could deliver optimum gain or power. In this way, we select load impedance for optimum power in stages three and four and load impedance for optimum gain in stages one and two. The Transmission lines (TL b1 -TL b8 ) together with capacitors (C 1 , C 3 , C 4 , C 6 , C 7 , C 9 , C 10 , and C 12 ) act as an RF choke. Although the length of the transmission lines (TL b1 -TL b8 ) is less than a quarter-wavelength, they still provide a very high impedance at the base of CE and collector of CB of the cascode stages at the designed frequency.
The input matching, interstage matching, and output matching networks are implemented by the series and openended transmission lines (TL 1 -TL 11 ). Small transmission lines (TL c1 -TL c5 ) used for the connection to transistor terminals and MIM capacitors (C B1 -C B5 ) used as a DC block are also part of the matching network. The bias current was 34 mA with a supply voltage of 3.4 V. Fig. 21 shows the S-parameters, and Fig. 22 shows the power gain and output power of the amplifier. From Fig. 21, it can be seen that the four-stage amplifier shows a peak gain of 22.5 dB with a 3-dB bandwidth from 225-250 GHz. The simulated saturation VOLUME 11, 2023      die micrograph of the phase shifter chain is shown in Fig. 23. The complete chip occupies a 1.41 mm 2 area. S-parameters of the implemented phase shifter chain were measured on-wafer over 140-325 GHz. An Agilent network analyzer is used in combination with WR3 and WR5 VNA extenders using 100-µm pitch GSG on-wafer probes. LRRM calibration was performed in this measurement. In the simulation, the 5-stage LNA and 4-stage amplifier were biased for a bias current of 35 mA and 34 mA, respectively to maximize the gain in the phase shifter chain. During the measurement with the original designed bias points as in the simulation for the LNA and the gain-enhancing amplifier, the phase shifter chain shows very peaky behavior. S 21 becomes peaky at 225 GHz and 234 GHz. The S 11 and S 22 became positive at 225 GHz. The reason for the peaky behavior in the S-parameter measurement could be due to the feedback through the input and output probes because of the high gain of the phase shifter chain chip. After reducing the bias of the LNA and gain-enhancing amplifier to 19 mA and 18 mA, respectively, the gain of the phase shifter chain decreases, and probably the feedback between the input and output probes also decreases, and as a result, the phase shifter chain becomes stable. Fig. 24 shows the measured S-parameters of the designed phase shifter chain for reduced bias current of the LNA and gain-enhancing amplifier. The measured maximum gain of the phase shifter chain is 28 dB at 220 GHz for the nominal control voltage of 0.8 V for the two controls of the phase shifter. The measured polar plot of   the S 21 at 230 GHz is shown in Fig. 25. The phase shifter chain shows 360 • phase control and 10 dB of gain control. The maximum gain with a full 360 • phase control range is 18 dB. Fig. 26 shows the measured 8 gain states of the phase shifter chain with 45 • steps. The corresponding measured 8 phase states of the phase shifter chain with a 45 • step from 220 GHz to 240 GHz are shown in Fig. 27. The maximum rms gain and phase errors are 1.55 dB and 16 • from 222 GHz to 240 GHz, respectively. The measured minimum NF of the phase shifter chain is 11.5 dB at 230 GHz, as shown in Fig. 28. If we compare the measured noise figure of the phase shifter chain with the measured noise figure of the stand-alone 7-stage LNA from Fig. 7, we can say that they match fairly with each other from 225-239 GHz, which indicates that the design procedure for the LNA in the phase shifter chain work was successful. Fig. 29 shows the measured output power vs. input power of the phase   shifter chain. The gain-enhancing amplifier was biased with 34 mA current to provide a simulated output power of 0 dBm. Due to the possible feedback oscillation in the phase shifter chain measurement, the gain-enhancing amplifier was later biased with a current of 18 mA. Hence, the phase-shifter chain did not achieve the expected output power of 0 dBm. The maximum output power from the phase shifter chain is −11 dBm at 230 GHz and −10 dBm at 225 GHz. Table 1 presents the summary of the phase shifter chain and compares the results with a published phased-array circuit [18] in a similar frequency range. From Table 1, it is seen that our designed phase shifter chain has a better performance in terms of gain with 360 • phase tuning.

IV. POWER AMPLIFIER
In addition to the high-gain phase shifter chain, transmitted power in the RF phase-shifting transmitter can be increased VOLUME 11, 2023  by providing high output power from a power amplifier. In a phased-array transmitter system, high output power from a driver PA is also needed to build a large phased-array. However, providing a large output power level above 200 GHz is challenging due to the fact that the transistor's maximum available gain decreases rapidly at these frequencies [23]. A common approach is to combine the power of several power amplifiers to achieve high output power. Different methods can be adopted for power combining. One of them is the Wilkinson power combiner, which offers better isolation between the PA units. Other approaches are to combine them using transformers or transmission lines. In these cases, the combining structure is also utilized as the matching network, achieving better PAE compared to the Wilkinson power combiner [19]. The transmission line combiner can offer more scalability and low loss, whereas a transformer-based combining network can provide a smaller area with a narrower bandwidth.
In this work, a unique 4-way combining technique using a compact, low-loss differential coupler is utilized in the PA design. The block diagram of the 4-way PA is shown in Fig. 30. In this design, two differential couplers are used, one at the input, which acts as a splitter, and another one at the output, which combines the unit PAs output, thus improving the matching of the amplifier. A similar design procedure for a differential coupler as in [22] is used here to generate differential I and Q paths, thus providing a 4-way path from a single coupler. Two units of PAs are connected to the I branch, and the other two units of PAs are connected to the Q branch of the input differential coupler. At the output, the signal from the PA connected to the input coupler's I branch is now connected with the Q branch of the output coupler, and vice versa for in-phase combination. Two compact Marchand baluns are used to realize the single-ended to the differential transformation of the signal. The unit PA is a four-stage cascode design. The schematic of the unit PA is similar to the amplifier described in Fig. 20 with a modification in the matching network to match the input and output of the coupler.
The die micrograph of the 4-way PA is shown in Fig. 31. The core PA occupies 0.67 mm 2 . S-parameters of the implemented PA were measured on-wafer over 220-325 GHz.      At 230 GHz, this PA exhibits a measured gain of 10.1 dB. The input and output matching are better than 10 dB in almost all the regions from 225-260 GHz. The bias current is 59.4 mA in a unit PA with a 3.45 V supply. Fig. 33 shows the measured output power and power gain of the PA. The measured peak P sat is 7.15 dBm at 244 GHz. At 230 GHz, P sat is 4.3 dBm and P 1dB is 4.0 dBm. Fig. 34 shows the saturated power and P 1dB against the frequency. It can be seen from Fig. 34 that P 1dB is close to 4 dBm or better from 230-250 GHz. Also, the P sat is equal to or better than 4.3 dBm over the frequency range from 230-255 GHz. In the measurement, the result shows a deviation from the simulation result. The gain in the measurement is higher than the simulation result. This could be due to the actual g m of the transistor being higher than the model we used for the simulation. Thus, the PA could achieve a higher gain even with a lower collector current compared to the simulation. The peak gain is shifted towards high frequencies by 5 GHz. This might be due to the parasitic effect of all the connections to the transistor terminals, which our EM modeling did not capture accurately. All these effects might contribute to the narrow measured bandwidth of the PA compared to the simulation bandwidth.
The PA measurement results are summarized in Table 2 with other published PAs. From Table 2, it is found that the designed PA has better gain than any other PA and better output power except the PA in [19] in the 225-255 GHz range.

V. CONCLUSION
In this paper, we have presented the design of the key elements for the phased-array scaling above 200 GHz in a 0.13-µm SiGe BiCMOS technology. The implemented phase shifter chain demonstrates a measured gain of 28 dB at 220 GHz and operates from 220 GHz to 240 GHz with a minimum measured noise figure of 11.5 dB at 230 GHz. It achieves 18 dB of peak gain at 230 GHz with 360 • phase tuning and 10 dB of gain control. Also, a 4-way power amplifier is implemented in a unique way, utilizing a differential quadrature coupler as a power combiner to increase the transmit power. The implemented PA shows a measured peak gain of 21 dB and saturated output power (Psat) of 7.1 dBm at 244 GHz. The realized PA delivers a saturated power better than of 4.3 dBm from 230-250 GHz. This PA shows better gain than any other published design in the 220-250 GHz range. To demonstrate a large phased-array, it is critical to have a very high gain, low noise figure RF phase-shifting path for a receiver. In the transmitter, along with the high-gain RF phase-shifting path, a power amplifier with high gain and high output power is needed to deliver higher transmit power. Based on the detailed discussions on VOLUME 11, 2023 the proposed architecture and measured performances of our designed circuits, a large phased-array system can be realized with our designed phase shifter chain and the power amplifier.