Quantitative Hot Carrier Injection Analysis of N-Type Tunnel Field-Effect Transistors

The hot carrier injection (HCI) of tunnel field-effect transistors (TFETs) is analyzed quantitatively under various conditions in terms of HCI-induced gate current (<inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {G}}$ </tex-math></inline-formula>), HCI probability (<inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {G}}/I_{\mathrm {D}})$ </tex-math></inline-formula>, potential energy, and lateral/vertical electric field for the first time. For example, the <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {G}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm {G}}/I_{\mathrm {D}}$ </tex-math></inline-formula> of TFETs are predicted in comparison with those of metal-oxide semiconductor FETs (MOSFETs) with the variation of gate voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {G}}$ </tex-math></inline-formula>), drain voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {D}}$ </tex-math></inline-formula>), gate insulator thickness (<inline-formula> <tex-math notation="LaTeX">$T_{\mathrm {ins}}$ </tex-math></inline-formula>), and channel length (<inline-formula> <tex-math notation="LaTeX">$L_{\mathrm {ch}}$ </tex-math></inline-formula>). According to the simulation results, TFETs show higher HCI probability than MOSFETs under the entire bias conditions because the former features strong peak lateral field at source-channel junction. For example, TFETs show <inline-formula> <tex-math notation="LaTeX">$\sim 1.8\times 10 ^{2}\text{x}$ </tex-math></inline-formula> higher HCI current and <inline-formula> <tex-math notation="LaTeX">$\sim 5.9\times 10 ^{6}\text{x}$ </tex-math></inline-formula> higher HCI probability than MOSFETs at <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {G}} =4$ </tex-math></inline-formula> V and <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {D}} =3$ </tex-math></inline-formula> V. The optimal HCI bias condition of TFETs is also analyzed.


I. INTRODUCTION
Tunnel field-effect transistors (TFET) have emerged as one of the most promising extremely low-power electron devices owing to their abrupt on-off switching, low offcurrent, weak temperature dependence, and CMOS process compatibility [1], [2]. Recently, reliability issues of TFETs have been studied extensively [3], [4], [5], [6], [7]. TFETs feature a strong peak electric field on the source side, leading to the following problems: work function variation [3], hot carrier degradation, and bulk/interface trap generation [4], [5], [6], [7]. It was revealed that the source-side bulk traps generated by the hot carrier injection (HCI) were the main causes of the threshold voltage shift of TFETs [6]. By contrast, HCI can contribute to TFET-based flash memory for extremely low-power applications [8], [9], [10]. Also, by using HCI, weight can be updated The associate editor coordinating the review of this manuscript and approving it for publication was Huamin Li . in both floating-gate memory and SONOS memory for analog in-memory-computing [10], [12], [13]. Thus, quantitative analysis of HCI has become an important research topic in TFETs. Although TFETs show more severe HCI than metaloxide field-effect transistors (MOSFET), to the best of our knowledge, contrary to MOSFETs, the HCI of TFETs has rarely been analyzed quantitatively. Previously, for example, it was reported that TFETs have more serious hot carrier degradation effects \than MOSFETs [4], [6]. However, the HCI rate and its maximum bias condition of TFETs still remain unknown. Even though some papers discussed the HCI of TFET-based flash memory cells, they showed only the HCI probability with the drain voltage (V D ), gate insulator thickness (T ins ), and channel length (L ch ) fixed [14], [15]. Also, most of previous HCI analyses of TFETs were based on the lucky-electron model [16], which has a low model accuracy of gate current (I G ) and maximum HCI location.
In this work, the HCI of TFETs was analyzed quantitatively in comparison with that of MOSFETs. The current,  current density, and probability of HCI are discussed under various bias conditions and device dimensions using technology computer-aided design (TCAD) simulation. Using the accurate HCI model based on spherical harmonic expansion of the Boltzmann transport equation (SHE-BTE), the HCI of TFETs was analyzed quantitatively. Based on the simulation results, the bias condition for the optimal HCI of TFETs was analyzed. Also, HCI programming operations of both TFET-based and MOSFET-based flash memories were compared.

II. DEVICE STRUCTURE AND SIMULATION METHODOLOGY
For the quantitative HCI analysis, two-carrier and twodimensional device simulations were performed using a commercial TCAD simulator [17]. Dynamic nonlocal band-to-band tunneling, Shockley-Read-Hall recombination, Philips unified mobility model, and Fermi distribution were used. Precisely calculated A and B parameters of Kane's model are used for band-to-band tunneling [18]. The I G was calculated using the SHE-BTE HCI model, which includes the nonlocal carrier energy and carrier distribution [19]. Also, SHE-BTE model is used for the precise HCI analysis because it is the most accurate HCI model in commercial TCAD simulator which shows the consistent result with Monte-Carlo method even in the case of short channel MOSFETs [20]. Fig. 1 shows the simulated n-type fully depleted siliconon-insulator (FD-SOI) TFET and MOSFET. For a fair comparison, both devices had the same device structure and parameters, except for the source doping type. T ch and T BOX represent the thicknesses of SOI and buried oxide (BOX) layers, respectively. The detailed simulation parameters are presented in Table 1.  All electrical properties are extracted at the silicon channel surface following A-A ′ cutline, as shown in Fig. 1. In this study, only hot electron injection is considered because avalanche-generated holes and secondary electrons are negligible in both n-channel FD-SOI TFETs [21] and MOSFETs without body bias [19], [22]. Thus, I G and the ratio of I G to the drain current (I D ) correspond to the HCI current and HCI probability, respectively. The electron energy is the average electron kinetic energy calculated using SHE-BTE. The source voltage (V S ) is fixed at 0 V.

III. RESULTS AND DISCUSSION
Before discussing the influence of bias conditions and device dimensions on the HCI, TFETs and MOSFETs were compared under the reference bias and dimension conditions. The reference bias condition was V G = V D = 4 V, and the reference device dimensions are summarized in Table 1.  ∼0.341 µA/µm and ∼13 mA/µm, respectively. Thus, TFETs feature a ∼3.8 × 10 4 x lower I D than MOSFETs. The significantly low I D of TFET is induced because of the current mechanism [23]. The I g of TFETs and MOSFETs are ∼0.314 nA/µm and ∼7.04 nA/µm, respectively. TFETs show more lower I G than that of the MOSFETs because I G , which is a result of HCI, is a function of the I D [18]. Therefore, TFETs feature a ∼22.4x lower I G and ∼1.7 × 10 3 x higher I G /I D than MOSFETs at V G = V D = 4 V reference bias condition. The higher I G /I D implies that TFETs have a higher HCI efficiency than MOSFETs. The underlying physics is explained in Fig. 3, which compares the HCI mechanisms of MOSFETs and TFETs under the reference bias condition. As shown in Figs. 3a and 3b, the HCI is affected by the following three HCI parameters: peak lateral electric field (E Y ), potential energy (PE), and vertical electric field (E X ) [16], [24]. The first two HCI parameters determine the electron energy required to overcome the 3.1-eV Si-SiO 2 energy barrier height. The probability that electrons gain energy by the first two HCI parameters can be expressed as follows [24]: where e and E are electronic charge the lateral electric field, respectively; v is electron velocity; τ is the mean time between scatterings; ε is the electron energy. While the third parameter determines the probability of momentum redirection and transmission towards the gate and image barrier height, which can be expressed as follows [19]: where m ins is the insulator effective mass; F ins is the insulator field, E im and E B0 are the image barrier lowering effect and the 3.1-eV Si-SiO 2 energy barrier height, respectively; τ is the mean time between scatterings; is the step function. In the case of TFETs, the peak E Y and abrupt PE drop occur around the source-to-channel junction owing to their p-i-n structure [25], [26]. This induces a lag in the electron energy behind the peak E Y , resulting in strong electron velocity overshoots and eventually high electron energy as the probability of gaining energy increases following (1) [27]. Thus, the electrons accelerated by E Y obtain the highest electron energy around the source-channel junction where strong E X induced by the positive gate-source voltage (V GS ) is applied, as shown in Figs. 3c and 3e. It is observed that the peak HCI of TFETs occurs around the source-channel junction. Note that the peak HCI point corresponds to the location where I G density is maximum. In contrast, in the case of MOSFETs, peak E Y and PE drop are observed around the drain pinch-off region where weak E X is applied due to the gate-drain voltage (V GD ), as shown in Figs. 3d and 3f. Thus, the hot electrons are more easily delivered towards gate electrode in TFETs than MOSFETs as the higher probability of momentum redirection is induced following (2) thanks to stronger E Y . In summary, TFETs are more HCI-efficient than MOSFETs because all three and only the two HCI parameters contribute to the HCI process in the case of the former and latter, respectively. Moreover, MOSFETs have dispersed E Y and PE drop over the channel under the reference bias condition, which lowers electron energy.

A. HCI WITH THE VARIATION OF BIAS CONDITIONS
In this section, V G becomes lower than that of the reference bias condition to compare the HCI of TFETs and MOSFETs under the V G < V D condition. When V G and V D are 3 and 4 V, respectively, TFETs have ∼19.8x lower I G and ∼4.8 × 10 3 x higher I G /I D than MOSFETs, as shown in Fig. 2. This implies that TFETs exhibit higher HCI efficiency than MOSFETs, even under V G < V D conditions. Fig. 4 shows the reason for this. Negative V GD induces negative E X around the channeldrain junction, which repels hot electrons away from the gate. In the case of MOSFETs, even if the electron energy increases as V G decreases owing to the increased peak E Y as shown in Fig. 4d, the peak HCI occurring at the channel-drain junction is disturbed by the negative E X as shown in Fig. 4f. In contrast, the HCI of TFETs is rarely affected by the negative E X . Thus, even if a lower V G reduces E Y , PE, and finally the electron energy in the case of TFETs, the peak HCI occurs around the source-channel junction where high electron energy and strong positive E X remain, as shown in Figs. 4c and 4e.  Subsequently, the HCI of TFETs and MOSFETs were compared under the V G > V D condition by lowering V D as shown in Fig. 5. MOSFETs exhibit more abrupt I G and I G /I D reductions than TFETs as V D decreases. Note that TFETs show ∼1.8 × 10 2 x higher I G and ∼5.9 × 10 6 x higher I G /I D than MOSFETs at V G = 4 V and V D = 3 V. Figs. 6a and 6b show the reason for this. Among the three HCI parameters, as V D decreases, TFETs experience only PE reduction, whereas MOSFETs experience both E Y and PE reduction. The peak E Y of TFETs rarely changes because it depends only on V G . Thus, lower V D reduces the electron energy of MOSFETs more than that of the TFETs, as shown in Figs. 6c and 6d. In addition, the strong E X of TFETs lowers the Si-SiO 2 energy barrier height owing to the image charge  effects [19], [24]. This makes the HCI of TFETs efficient even at V D = 3V, while high V D is needed for the HCI programming of MOSFET-based flash memory [28], [29]. Thus, TFETs are more HCI-efficient than MOSFETs under all bias conditions. Finally, the optimal HCI bias condition of the TFETs can be determined where the PE saturates. Fig. 7 shows I G /I D and channel potential ( CH ) as functions of V D and V G . CH is used to extract PE because PE is q·( CH -V S ) in TFETs [30], which becomes q · CH at V S = 0 V. CH is extracted in the middle of the channel. Fig. 7 shows that both I G /I D and CH saturate when V G -V D is equal to 0.26 V, which corresponds to threshold voltage (V th ). The V th of TFETs is defined as V G when CH saturates [30], [31]. Thus, the optimal HCI condition of TFETs is V G − V th = V D .

B. HCI WITH THE VARIATION OF DEVICE DIMENSIONS
The HCI of TFETs and MOSFETs were compared for various device dimensions: T ins and L ch . First, the dependency of HCI on T ins is discussed. Under the reference bias condition, with the increment of T ins , both I G and I G /I D of TFETs decrease, while those of MOSFETs increase, as shown in Fig. 8. T ins affect the channel screening length (λ ch ) by adjusting the gate controllability [32], [33]. Larger T ins lowers the peak E Y of TFETs because of λ ch increase, which decreases the peak electron energy, as shown in Figs. 9a and 9c. Thus, in the case of TFETs, large T ins lowers the peak E Y and electron energy as well as the peak E X , which suppresses HCI, as shown in Fig. 9e. However, MOSFETs exhibit the opposite trend because of the widening of the pinch-off region. Larger T ins boost the peak E Y at the channel-drain junction owing to λ ch increase and raises the electron energy, as shown in Fig. 9d. Thus, E X weakened by T ins increase is compensated by the higher electron energy [34]. Thus, contrary to MOSFETs, TFETs become more HCI-efficient as T ins decreases. This implies that TFET-based flash memory can achieve a low operating voltage with high immunity to short-channel effects.
Subsequently, Fig. 10 compares the HCI s of both the devices in terms of L ch . It is observed that L ch reduction rarely affects the I G and I G /I D of TFETs, whereas it significantly increases those of MOSFETs because the former has stronger short-channel effect immunity than the latter [35]. In the case of TFETs, all the three HCI parameters are independent of L ch as shown in Fig. 11a. In contrast, in the case of MOSFETs, short-channel effects boost the peak E Y , electron energy, and HCI rate while reducing E X as L ch decreases. In other words, the higher electron energy limited by the weak E X makes  MOSFETs less HCI efficient than TFETs. Also, although high HCI efficiency is expected in the case of short-channel MOSFET-based flash memory, severe short channel effects induce poor gate controllability which limits the downscaling of MOSFET-based flash memory [36].
Finally, the HCIs of TFETs and MOSFETs were compared under various bias and dimension conditions. As shown in Figs. 12a and 12b, even if TFETs have a lower I G than MOSFETs, the former shows higher I G /I D than the latter, regardless of the dimensions under the reference bias. Furthermore, under the V G > V D condition, TFETs show higher I G and I G /I D than MOSFETs, regardless of the dimension conditions, as shown in Figs. 12c and 12d. It is confirmed that TFETs show higher I G /I D under all simulated conditions and higher I G under V G > V D conditions than MOSFETs.

C. EXTREMELY LOW POWER PROGRAMMING OPERATION IN TFET-BASED FLASH MEMORY
The high HCI probability of TFETs can be utilized for the implementation of TFET-based flash memory for extremelylow power programming. TFET-based flash memory will be compared with MOSFET-based one. Figs. 13a and 13b show the simulated structures and program mechanism of both kinds of memory cells. N + poly-silicon floating gates are used whose doping concentration is 1 × 10 20 cm −3 . T tunnel , T floating , and T block mean the bottom oxide thickness, floating gate thickness, and blocking oxide thickness, respectively. T tunnel , T floating and T block are 8 nm, 20 nm, and 15 nm, respectively [37], [38]. L ch , T ch , T box , N S , and N D of both kinds of flash memory cells are the same as in Table 1 TFET-based flash shows smaller V th 's than MOSFET-based one due to lower I G , the former is superior to the latter in terms of program energy thanks to HCI-efficient program. Fig. 14 shows V th 's of both cases as a function of t program and program energy (V D · I D · t program ). As shown in Figs. 14a and 14b, despite longer t program , TFET-based flash memory only consumes 0.52 pJ to achieve V th = 3.42 V at V G = 10 V, V D = 4 V program condition, which is ∼4×10 5 x lower than MOSFET-based one. Figs. 14c and 14d show the program case with lower V D (V G = 10 V, V D = 3 V program condition), TFET-based flash memory shows ∼2 × 10 6 x lower program energy than MOSFET-based one in addition to shorter t program because the HCI of TFETs is less sensitive to V D than that of MOSFETs. High HCI program efficiency of TFET-based flash memory will be helpful for extremely low-power neuromorphic applications where on-chip weight training is frequently occurs.

IV. CONCLUSION
The HCI of TFETs was quantitatively analyzed in comparison with that of MOSFETs with variations in V G , V D , T ins , and L ch . TFETs show higher I G /I D than MOSFETs under the entire bias condition, meeting the two requirements simultaneously: high electron energy and strong E X . However, MOSFETs can satisfy only one of these requirements. It was revealed that the optimal HCI bias condition of TFETs is V G -V th = V D . It is confirmed that TFET-based flash memory features lower program power consumption and higher program efficiency than MOSFET-based flash memory.