Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters

Real-time simulation is important for ensuring the reliable operation of VSC-HVDC converters in power grids, particularly through the use of rapid control prototyping (RCP) and hardware-in-the-loop (HIL) based converter controllers. While real-time simulation is a common practice for modular multilevel converters (MMCs), it has been less frequently applied to the new class of hybrid cascaded multilevel converters (HCMCs). In this study, a universal equivalent model (UEM) is proposed for a range of HCMC topologies that combines accuracy and computational efficiency through the use of both CPUs and field-programmable gate arrays (FPGAs). The proposed UEM is derived using the hybrid five-level converter (H5LC), a compact, efficient, and fault-tolerant VSC within the HCMC family. The UEM relies on CPUs to simulate the main circuits and controls of the main converter, and utilizes FPGAs to calculate the instantaneous voltages of a large number of full-bridge submodules (FBSMs), flying capacitors, and DC-side pole capacitors. In addition, the FBSMs’ voltage-balancing and switching algorithms are implemented on the FPGAs. The proposed real-time CPU/FPGA-based H5LC-UEM is compared to an offline CPU-based detailed equivalent model to verify its accuracy.


I. INTRODUCTION
Hybrid cascaded multilevel converters (HCMCs) are a promising class of power converters for voltage-source converter high-voltage direct-current (VSC-HVDC) transmission applications due to their low semiconductor losses and small converter footprints. Prior to HCMCs, the classical two-and three-level converters [1], [2], [3] dominated the VSC-HVDC technology for decades until the submodulebased (SM) modular multilevel converter (MMC) became ubiquitous in the field [4].
The associate editor coordinating the review of this manuscript and approving it for publication was Tariq Masood .
The MMC has significant benefits over the two-and threelevel converters in terms of: 1) efficiency, due to its low semiconductor switching losses and conduction losses, especially if it uses half-bridge SMs (HBSM) in its arms; 2) serviceability, due to the modularity of its submodules; 3) reduced dv/dt voltage stress on transformer windings; and 4) DC shortcircuit fault-blocking capability when it uses bipolar SMs (BSMs). By inserting and bypassing its capacitor-containing SMs, the MMC can generate a stepped-sinusoidal AC-side voltage that does not need any filtering.
Despite these advantages, the MMC also has drawbacks. In particular, it lacks inherent DC-side fault blocking capability, such that large arm inductors are used to limit fault currents. Alternatively, the MMC can replace at least half of its arm SMs to be full-bridge submodules (FBSMs), or other BSMs, for their reverse voltage blocking capability against the AC-side grid voltage. A common configuration is a mixed-bridge SM (MBSM) MMC, which uses an even mixture of HBSMs and FBSMs in its arms. These solutions increase the MMC's size, upfront costs, and worsen efficiency [5], [6], [7], [8]. Moreover, the MMC has substantial energy storage requirements in its SMs compared to other recently proposed multilevel converters, which impacts its size. The two recently proposed multilevel converters are the extended-overlap alternate-arm converter [9] and the thyristor-based hybrid three-level converter [10], which respectively require 60.4% and 77% less energy storage than the MMC. These converters are operationally identical to the MMC from a systems-level perspective, but have inherent DC fault-blocking capability, higher efficiency, and smaller footprints due to their small energy storage requirements.
Building upon the expected benefits of the recently proposed converters, the new class of HCMCs combines the simplicity of two-and three-level converters with the modularity and stepped-voltage generation of the MMCs [11], [12], [13], [14], [15]. This paper focuses on the types of HCMCs with the generalized structure of Fig. 1 (a), consisting of a Main Converter (MC) that performs AC/DC conversion with slow-switching director switches (DSs), and AC-side cascaded FBSMs that filter all non-fundamental harmonics. Figs. 1 (b) and (c) present the four-level nested-neutral-point converter (4L-NNPC) and the T-type five-level converter (T-5LC), which are two such MC topologies. Fig. 1 (d) presents the generalized case of N MC nested T-type three-level converter cells, with the option of clamping them to the neutral point, n, to provide the zero-voltage level. The hybrid two-level (H2LC, [13]) and hybrid three-level converters (H3LC, [14]) are well-documented examples of the HCMCs, which correspond to N MC = 0 in Fig. 1 (d) without and with the optional midpoint DS, respectively. The H2LC and H3LC each have valuable attributes in terms of fault-blocking capability and the overall volume. From these two converters, the H3LC has improved efficiency due to fewer IGBTs in the conduction path since it needs half as many normal-operation FBSMs as the H2LC. Compared to the MBSM MMC, the H3LC has 13% less semiconductor loss, a smaller expected footprint (enabled by a 67% smaller energy storage requirement), 13.3% fewer IGBTs, while having DC-side fault blocking capability [14].
The hybrid five-level converter (H5LC) proposed in [15] is a converter structurally similar to the H3LC that corresponds to the topology of Fig. 1 (d) with N MC = 1, i.e., Fig. 1 (c). With its added two flying capacitors (FCs) per-phase, the H5LC's MC has two additional voltage levels compared to the H3LC's such that its cascaded FBSMs block a total of V DC /8 per phase, which is halved and quartered compared to the H3LC and H2LC, respectively. Therefore, the H5LC is expected to have improved efficiency compared to both the H2LC and H3LC due to requiring 37.5% and 16.7% fewer IGBTs in the conduction path, reducing its semiconductor conduction losses.
In general, the cascaded FBSMs of the HCMCs are sized to generate peak bidirectional voltages equal to half the voltage step-size of their MCs. The MC voltage step-sizes of the H2LC, H3LC, and H5LC are respectively V DC , V DC /2, and V DC /4, such that their cascaded FBSMs are sized for peak voltages of ±V DC /2, ±V DC /4, and ±V DC /8. Hence, as the number of voltage steps of the MCs increases, the number of required cascaded FBSMs, and the associated conduction losses, decreases.
However, it is noted that in all cases, the H2LC precluded, the blocking mode voltage of the cascaded FBSMs is insufficient to counteract the AC-side line-to-line voltages. Hence, to avoid using more FBSMs to reach the needed blocking voltages, the HCMCs require additional circuitry to bypass the FBSMs during DC-side short-circuit faults to protect their IGBTs. As proposed in [15] for the H5LC, the HCMCs can use bidirectional thyristor valves (BTVs) with fast mechanical switches (FMSs) to effectively decouple the AC-and DCsides. BTVs have high blocking voltages and surge current capabilities while having a simple mechanical design and a small footprint compared to FBSMs.
The real-time simulations have been achieved for the twoand three-level converters and MMCs [16], [17], [18], [19]. But it has yet to be applied to complex HCMCs such as the H5LC. Due to the intricacy of its operating principle, this paper develops a method of CPU/FPGA co-simulation for the H5LC, which will lay the groundwork for topologies of even greater complexity that use the MCs with increasing voltage levels. We derive the proposed method to be extensible to other HCMC topologies. By only redefining the inputs to controlled voltage sources, any HCMC can be simulated without modifying the converter equivalent circuit structure.
The proposed method derives a universal equivalent model (UEM), which reduces the simulation burden of the converter system without loss in simulation accuracy. Other computationally efficient simulation methods have been applied to the H3LC in [20], but the method proposed herein offers greater flexibility and applicability to any HCMC topology.
Throughout this paper, we provide a detailed description and derivation of the H5LC's topology and operating principle in both nominal and fault-blocking operations. The main contributions of this paper are as follows: 1) A novel UEM is proposed that enables representation of any HCMC having an MC connected to cascaded AC-side FBSMs. The UEM reduces HCMC circuits to eight controlled voltage sources that accurately emulate the circuits even for dynamic fault scenarios. 2) We apply the UEM framework to the H5LC (H5LC-UEM), which is based on the five-level converter of Fig. 1 Table 1, the mid-high and mid-low states each have two unique switching configurations that enable v FC,u,j and v FC,l,j , respectively, to be balanced to the set-point voltages of V DC /4.  The five-level voltage presented at v 5LC,j in Fig. 2 connects to AC-side cascaded FBSMs, which are operated together to remove the non-fundamental voltage components of v 5LC,j , such that the line-to-line voltage at v jt is close to ideal sinusoid. As the cascaded FBSMs do not take part in real power exchange, their average energy remains constant cycle-to-cycle. When the H5LC is interfaced to AC transformers with delta-winding connection, its cascaded FBSMs can use third-order harmonic voltage injection to limit their total blocking voltage to V DC /8. Compared to the H3LC and the MMC, this represents a reduction of 50% and 94% of equivalently-rated SMs, respectively. Therefore, each of the N FBSMs per phase sustains the nominal voltage of 1 8N V DC . With its low number of cascaded FBSMs and fundamental-frequency switching of its DSs, the H5LC has comparable conduction losses to the HBSM MMC (and improved conduction losses compared to the MBSM MMC), but improved semiconductor switching losses.

B. OPERATING PRINCIPLE AND CONTROL
For a symmetric five-level voltage at v 5LC,j , Fourier analysis gives the magnitude of the fundamental voltage component as 5LC,a and v * FB,a for V 1h = 0.61v DC . The variables with superscript * denote the references. For each V 1h , the two degrees of freedom in (1) lead to limitless options for α 1 and α 2 . However, with a desired blocking voltage of V DC /8 for the cascaded FBSMs, the local maxima of v * FB,a , i.e., v * FB,a (α 1 ) and v * FB,a (α 2 ), is limited to V DC /8. The third-order harmonic in (2) gives rise to added constraints Solving (1), (3) numerically, and (4) at each V 1h , the look-up table of Fig. 3 (c) is populated to give the proper values of α 1 , α 2 , and V 3h , which enable the cascaded FBSMs to be rated for a total blocking voltage ofv FB,a = V DC /8, as can be seen in Fig. 3 (i), where the addition of the third-order harmonic limits v * FB,a to be within ±v DC /8. We note that the limits of ±v DC /8 are only valid if V 1h ≤ 0.62 V DC ; hence, V 1h = 0.62 V DC is defined as the H5LC's maximum operating voltage.
The voltage v * FB,a in (2) is the desired and ideal voltage for the cascaded FBSMs. The insertion function, N ins,a , which gives the instantaneous number of FBSMs to be inserted or bypassed may be presented using nearest-level control (NLC) as where V c is the nominal voltage of the FBSMs' capacitors. The insertion function gives the number of FBSMs to be inserted or bypassed, and the polarity thereof. But it does not generate the FBSMs' individual switching signals. Another control layer, i.e., the FBSM voltage balancing algorithm (VBA) of Fig. 3 (g), determines which FBSMs to insert or bypass such that the average voltage of each FBSM's capacitor remains constant cycle-to-cycle. These methods produce three row vectors of switching signals (for the three phases), s j , of which the j th vector has N elements. The i th element of s j , s i,j (where i ∈ [1, N ]), can take values {−1, 0, 1} for negative insertion, bypassed, and positive insertion, respectively. Hence, the actual voltage produced by the N FBSMs, v FB,j , is given by where v c,j is the column vector containing all of the N instantaneous FBSM capacitor voltages for the j th phase. With proper control that compensates for the expected voltage ripple, (6) provides a value close to v * FB,j . An additional PI control layer, i.e., Fig. 3 (e), is used to regulate the cascaded FBSMs' total voltage to v DC /8 by the injection of a small fundamental-frequency voltage component, V abc , which causes the cascaded FBSMs to either absorb or dissipate power to the AC-side to balance them. The cascaded FBSMs' total voltage slowly decreases due to leakage effects of their capacitors and losses of the IGBTs. The control in Fig. 3 (e) compensates for the energy loss of the FBSMs by addition of V abc , which is typically two orders of magnitude lower than V 1h and may be neglected in (6).
Moreover, two more control layers are needed to keep the PCs and FCs balanced, as in Figs. 3 (d) and (f) and Fig. 4. The PC VBA of Fig. 3 (d) uses a PI controller to regulate the difference of the upper and lower PC to 0 by manipulation of the duration of the five-level converter V DC /2 and −V DC /2 voltage levels, i.e., the H and L states, respectively. Either the positive or negative V DC /2 voltage level interval is elongated while the other is shortened to introduce a DC offset in the output voltage such that more current flows through one of the PCs compared to the other, bringing their offset to 0. The FC voltage balancing algorithm uses hysteresis-based control with comparators to ensure that 1) the FC voltages do not exceed their limits of e.g., ±10% of their set-points, and 2) at the beginning of the ±V DC /4 voltage levels, the  DS states from Table 1  For a small footprint, the H5LC uses BTVs and FMSs for their high blocking voltages and simple mechanical design. Since BTVs' turn-OFF is uncontrollable, a single BTV sustains the entire line-to-line voltage until the next BTV turns OFF. Hence, the voltage rating of each BTVs is 1.07V DC . Consequently, only two BTVs are needed for DC fault blocking in a three-phase system. Hence, only two phases need the fully-rated BTVs and FMSs. The third phase's BTV needs to block only V DC /8 (i.e.,v FB,j ), while its FMS is optional.
During DC-side faults, the cascaded FBSMs are blocked to commutate current away from them to the BTVs. The maximum rate that the current commutates from the cascaded FBSMs to the BTVs is given by where L comm can be the stray inductance of the loop containing the cascaded FBSMs and the BTVs in Fig. 2 (and is approximately 1 mH). Hence, for a VSC-HVDC system with a DC-side voltage of 600 kV, di max comm /dt ≤ 75 A/µs, which is below a typical thyristor's critical rate-of-change of ON-state current, di crit /dt (found in most thyristors' datasheets).
The sequence of events for DC fault-handling for the H5LC is as follows: 1) Detection of the fault via measurement of v DC or i DC prompts the following simultaneously: i) the H5LC's DSs are blocked; ii) all three-phase BTVs are triggered ON; and iii) the cascaded FBSMs are all blocked (since di max comm /dt ≤ 75 A/µs). In the cases when di max comm /dt ≥ di crit /dt, fewer FBSMs can be blocked for slower commutation.
2) As the H5LC requires only two of its BTVs to be rated for the entire 1.07V DC , e.g., those of phases b and c, their FMSs open shortly after the BTVs are triggered ON since commutation occurs rapidly. Then, the b-and c-phases' BTVs' trigger signals are removed.
Once i b and i c change polarity, the BTVs are turned OFF naturally. 3) Once the BTVs in phases b and c are turn OFF naturally, phase-a's BTV's trigger signal is removed and the AC-and DC-sides become effectively decoupled. The H5LC's PCs and FCs lose their electric charges during DC-side faults. As shown in Fig. 2, charging resistors in parallel with AC-side circuit breakers (ACBs), are used to restore their charges. The PCs charge passively through the charging resistors, R charge , and the free-wheeling diodes of the {T 1,j , T 2,j , T 3,j , T 4,j } DSs. The FCs charge similarly by turning ON DSs T 7,j and T 8,j ; this drives a charging current through the free-wheeling diodes of DSs T 2,j and T 3,j and through the DSs T 7,j and T 8,j .

III. UNIVERSAL EQUIVALENT MODEL
With knowledge of the instantaneous phase currents, desired switching states, and the historical values of the capacitor voltages, the HCMCs can be reduced to an equivalent circuit model with controlled voltage sources to emulate the converter operation. The method proposed herein derives the individual capacitor voltages for all of the FBSMs, FCs, and PCs of the H5LC, although it is extensible to any HCMC based on the general discretized capacitor voltage equation using the Forward Euler method, i.e., For practical VSC-HVDC systems, the number of capacitor-containing devices, e.g., the FBSMs, may be several hundreds per phase. For the accurate simulation of realistic systems, (8) should be used for each FBSM capacitor, FC, and PC. For conventional CPU-based methods, this presents an enormous computational burden for real-time applications, since the CPU calculates each of the capacitor voltages serially. With FPGA co-simulation, the FPGA calculates all capacitor voltages in parallel, such that it invokes (8) for each of the FBSMs, the PCs, and the FCs simultaneously at each calculation step. Section IV presents the FPGA's entire role in the co-simulation.
The generalized circuit structure of the proposed HCMC-UEM is presented in Fig. 5, which is applicable to any topology of the form of Fig. 1 (a). Although identical in structure, we refer to the HCMC-UEM applied to the H5LC as the H5LC-UEM. Fig. 5 presents three phases of equivalent modules (EMs), which are placed at the AC-side of a six-pulse diode bridge. The voltage sources v PC,u and v PC,l replace the H5LC's PCs to compose the equivalent DC-side circuit. The switches, S, are opened during DC-side fault scenarios to emulate the AC-side contribution to, e.g., short-circuit faults, but are closed for nominal and energization operations.
The detailed representation of one EM is shown in Fig. 6, which is composed of two voltage sources per phase: one for nominal/de-blocking operation, v nom,j ; and one within the diode-bridge for fault-blocking operations, v blk,j . In series with v blk,j , and in parallel with the diode-bridge containing v blk,j , are the FMS and BTV, respectively, which enable the HCMCs' fault blocking capabilities. In nominal operation, the FMSs of all EMs are turned ON and the BTVs OFF.
The voltage sources v nom,j and v blk,j of the H5LC-UEM are complementary to represent different converter operation modes, such that the converter operation flag, b, dictates which of the two are triggered ON: b≡0 for nominal/deblocking operation and b ≡ 1 for blocking operations. The switches, S, are directly determined by b as S ≡ b, as in Fig. 5. An additional flag, E, enables emulation of the FCs' energization operation. Hence, we define v nom,j and v blk,j as where v 5LC,j and v FB,j are found, respectively, by Table 1 and (6). It is noted that energization is required after, e.g., DC-side pole-to-pole fault scenarios. However, as the FCs are not discretely modeled in the HCMC-UEM model of It is noted that v charge FC,j of (11) does not appear in (10) unless E ≡ 1, i.e., during the FC energization process. The energization process requires the switches to be closed, i.e., S = 1, such that b = 0 when E = 1.
During fault blocking scenarios when b ≡ 1 and the FBSMs are blocked, the FBSMs generate reverse voltages against both positive and negative current directions such that v FB,j and v blk,j are exclusively positive, which emulates the FBSMs' blocking mode and ensures rapid commutation of their currents to the BTVs. To include the functionality of the FBSMs in nominal as well as fault operations, we calculate the i th capacitor voltage of the j th phase FBSMs as where C SM is the FBSM capacitance. During DC-side faults, any polarity of current flowing through the cascaded FBSMs charges them; hence, the absolute value of the current is included in (12) for blocking mode. The inclusion of E in (12) ensures that the FBSMs during the FC energization process do not charge or discharge. Hence, with the simulation time-step, t, the i th FBSM's switching states, s i,j , and the phase current, i j , as inputs, the FBSM capacitor voltages update according to (12). For the PCs and FCs, i j and the values of b and E do not directly determine their currents. Hence, we analytically derive their currents below.
For the upper PC, we represent its current based on Fig. 2

as
where In (14): i DC,u,j is the current flowing through T 1,j of the j th phase during nominal operation and is derived in Table 1; i meas conv,u represents the measured current from the six-pulse diode bridge; and i fault FC,j refers to the current driven through the free-wheeling diodes of T 1,j and T 4,j by the FCs during the fault when their voltage exceeds that of the PCs. During normal operations, i conv,u is determined solely by i DC,u,j of the three phases, since the six-pulse diode bridge is reverse biased such that i meas conv,u ≡ 0; however, during fault operations, i meas conv,u and j i fault FC,j are used to determine the upper PC capacitor current. When the converter is blocked and the summation of the FC voltages exceeds the DC-side voltage, the FCs discharge to the PCs through the free-wheeling diodes of T 1,j VOLUME 11, 2023 and T 4,j . Hence, we define i fault FC,j as where R DS is the ON-state resistance of the diodes of each of T 1,j , . . ., T 4,j . In (15), i fault FC,j is non-zero only when the seriesconnected FCs' voltage exceeds that of the PCs'; i.e., i fault FC,j is non-zero when the DC-side voltage reduces to below approximately V DC /2. Similarly, the lower PC current is calculated as where Once the DC fault is detected, all the DSs are placed into the blocking state, i.e., the vectors T j containing the DSs' switching signals are defined as T j ≡ 0, such that i DC,u,j and i DC,l,j , as defined in Table 1, are zero. To emulate the effect of the blocked DSs during DC-side faults, switches S of Fig. 5 are also opened. Hence, only the measured converter currents, i meas conv,u and i meas conv,l , and the FC discharging currents, i fault FC,j , are considered for the PC capacitor currents when T j ≡ 0.
The nominal upper and lower FC currents are defined in Table 1 by the states of the five-level converter and phase current; however, for fault operation, the FCs' fault current, i fault FC,j of (15), flows through each phase's FCs, such that the FC currents are defined as where i SC FC,j is the short-circuit current that flows within T 2,j and T 3,j if the series FC voltage becomes negative and is defined as and i charge FC,u,j and i charge FC,l,j are currents to charge the FCs during the energization process and are defined as Thus, with the currents developed in (13)- (22), the voltages of the H5LC's PCs and FCs can be derived using (8) as where the flow diagrams of Figs. 6 (b) and (c) depict the calculations of the currents and voltages.

A. H5LC-UEM DC FAULT OPERATION
During DC-side faults, the expressions of phase voltages from (9) changes to (10) since once the DC fault is detected, the five-level converter portion of the H5LC is blocked such that the six-pulse diode bridge begins to conduct. The steps for DC fault blocking are outlined in Section II-C, where the blocking flag, b, triggers the switches S to open until the energization process begins. Once the energization process begins, i.e., once E = 1, the blocking flag is removed. It is noted that while b = 1, the FBSMs are all blocked such that s j = 1, but once E becomes 1, then b = 0 and the FBSMs are all bypassed, such that s j = 0.

B. FC ENERGIZATION PROCESS
Once the FCs lose their charge due to, e.g., DC-side shortcircuit faults, the ACB of Fig. 5 is opened to insert the charging resistor into the circuit under zero current. For the detailed H5LC of Fig. 2, this triggers each phase to turn ON DSs T 7,j and T 8,j such that the line-to-line voltage drives a current through the free-wheeling diodes T 2,j or T 3,j to charge the FCs. With T 7,j and T 8,j turned ON, the polarity of the phase current determines the voltage at v 5LC,j as: The EM of Fig. 6 can emulate this action by controlling v charge FC,j , i charge FC,u,j , and i charge FC,l,j of (10) and (11), (21), and (22), respectively. Once the energization process begins, b and E are set to 0 and 1, respectively, which prompts the cascaded FBSMs to be bypassed, i.e., s j = 0, so that they do not charge during this process. Once either the upper or lower FC voltage of the j th phase increases to its set-point value of V DC /4, charging for the j th phase is halted by turning OFF DSs T 7,j and T 8,j (i.e., by opening switch S for the H5LC-UEM). If one of the upper or lower FCs is slightly undercharged after the energizing process, the FC voltage balancing control of Figs. 3 (d) and 4 is employed to quickly drive the FC voltage towards its set-point.
The universality of the UEM is due to the overall circuit structure shown in Fig. 5. However, the specific circuitry within the EM blocks will vary depending on the specific converter that the UEM is being applied to. For instance, when using the UEM to model the H3LC (as described in [20]), the circuit structure in Fig. 6(a) would need to be modified to include the H3LC's unique DC-fault blocking hardware. The UEM can be applied to any converter, but separate calculations for voltages and currents will need to be performed for each one. The reason for choosing to apply the UEM to the H5LC rather than the H3LC or H2LC is that the H5LC is the most complex of the three, providing a solid foundation for application to other converters.

IV. CPU/FPGA CO-SIMULATION OF H5LC-UEM
To accurately calculate the 3 × 64 FBSMs' capacitor voltages at each CPU time-step while maintaining real-time performance, we describe the architecture of the FPGA implementation and the interconnections between the CPUs and FPGA based on OPAL-RT Technologies' OP5700 real-time simulator. The high-level topology of the CPU/FPGA architecture is presented in Fig. 7, which includes two CPUs and one FPGA, wherein CPU 1 and CPU 2 respectively generate the control signals and the simulation model of the H5LC-UEM system. As Fig. 7 shows, the FPGA sends to CPU 2, i.e., the CPU on which the VSC-HVDC system is simulated, the two phase voltage outputs, v nom,j and v blk,j , and the DC-side PC voltages, v PC,u and v PC,l , for the eight total controllable voltage sources of Figs. 5 and 6. For its inputs, the FPGA takes the converter reference signals from CPU 1 and the measured operational currents from CPU 2. CPU 1 is responsible for the upper-and lower-level controls of the VSC-HVDC system, i.e., those from Fig. 3 and Section II-B, with inputs from both CPU 2 and the FPGA. CPU 2 provides the measured phase voltages and currents, v j and i j , to CPU 1, while the FPGA supplies the internallycalculated PC voltages, v PC,u and v PC,l , for the controllers of CPU 2 simulates the VSC-HVDC system presented in Fig. 7, which uses the H5LC-UEM of Fig. 5 that contains a total of eight voltage sources, 18 diodes, eight ideal switches (for the switches S, the FMSs, and the charging breakers), and three BTVs, whereas the H5LC-DEM contains 24 IGBTs for the five-level converters alone. For complete functionality, CPU 2 requires only the eight voltage source signals from the FPGA as its inputs. Its outputs are the twelve currents, i j , i DC , i meas conv,u , i meas conv,l , i fault FC,j , and i SC FC,j , from which it internally calculates the currents of (13), (14), (16) to (19), and (21)  and (22). i fault FC,j and i SC FC,j are CPU-calculated quantities since the arithmetic division of (15) and (20) does not put a heavy computational burden on CPUs as it does on FPGAs.
A crucial element of FPGA/CPU co-simulation of multilevel converters is an appropriate VBA to ensure the cascaded FBSMs' capacitor voltages remain within a desired bound. Several methods to achieve balanced FBSM voltages have been proposed [21], [22], [23], all of which require a sorting algorithm to provide the maximum or minimum capacitor voltage per phase, and to determine which SMs are the best candidates to bypass or insert. This paper presents a sorting and insertion method that is built specifically for FBSMs, compared to the methods that assume each FBSM is an equivalent module of two HBSMs [24]. The FPGA model assumes 64 FBSMs per phase with capacitor voltages of bit-width Q12.30, for a resolution of 2 −30 V ≈ 9.31 × 10 −10 V, which is sufficient for most applications. Hence, there are a total of 192 FBSMs for the three-phase H5LC.

A. SORTING ALGORITHM
The extensive parallel-computing capabilities of FPGAs enable rapid sorting. However, completely sorting 3 × 64 FBSMs within each FPGA calculation time-step, T FPGA , uses many of the FPGA's logic cores, leaving little resources for the voltage calculations.
Hence, this paper assumes a serial-parallel sorting algorithm that determines only the maximum and minimum FBSM capacitor voltages at each FPGA calculation timestep, rather than producing the entire list of sorted voltages. VOLUME 11, 2023 Therefore, this method enables insertion or bypassing of only one FBSM per T FPGA cycle. In case more than one FBSM is desired to be inserted or bypassed, T FPGA should be significantly smaller than the CPU time-step, T CPU . Therefore, the number of completed FPGA calculations and FBSM insertions/bypasses within a single CPU time-step, τ , is The FBSMs of the H5LC can be either inserted, in positive or negative polarity, or bypassed. To avoid unnecessary switching operations, presently inserted or bypassed FBSMs may be precluded from the sorting algorithm depending on the polarities of N ins,j and i j . This is accomplished by prepending a bit, p, to each of the 64 FBSMs. The bit p is defined for the i th FBSM of the j th phase as  The parallel sorting method is illustrated in Fig. 9, which shows the parallel sorting method requires k max /2 comparators and k max blocks of RAM to sort the k max = 8 test voltages, v max [k]. For illustrative purposes, we assume that the descending order of the voltages, v max [k], is known beforehand (see the top of Fig. 9). Without loss of generality, we assume v max [5], i.e., the maximum voltage supplied by the k = 5 serial-sorter group, is the maximum among all the groups. Fig. 9 shows that the proposed parallel sorter takes ceil log 2 (k max ) = 3 time-steps to find the maximum FBSM capacitor voltage and its index. Hence, for this paper which uses k max = 8, the parallel sorting function requires log 2 (8) = 3t FPGA to produce the maximum and minimum capacitor voltage indexes.
Serial sorting is the most time-intensive operation, taking over twice as long as all of the succeeding operations combined. Hence, the succeeding operations can be pipelined such that once the serial sorting completes, the ready bit that the serial-sorter produces is used to trigger the parallel-sorter as well as itself for the next run. Therefore, although the entire calculation cycle of the FPGA is longer than 8t FPGA , it can be pipelined such that the voltages are updated every T FPGA = 8t FPGA , e.g., 80 ns.

D. SWITCHING FUNCTION
After the indexes of the maximum and minimum capacitor voltages are obtained, under the constraint of p i,j of (27), the switching function of Fig. 10 deter mines which one of the two indexes supplied by the parallel sorter, i.e., ind max or ind min , should be inserted or bypassed. At each T FPGA , if N ins,j from CPU 1 is greater than i s i,j , then the switching function increases the number of inserted FBSMs by inserting the FBSM with the index of either ind max or ind min ; if N ins,j < i s i,j , the FBSM with the index of either ind max or ind min is bypassed. Determining which of ind max or ind min to use depends on the desired polarity of the insertion function, N ins,j , and the polarity of the current, i j .
When the polarities of N ins,j and i j are the same, i.e., both are positive or negative, the inserted FBSMs' capacitors charge; when they are different, the inserted FBSMs' capacitors discharge. Hence, the following four cases determine which FBSM to insert or bypass.
For insertion, i.e., N ins,j > i s i,j : 1) If i j and N ins,j have the same polarity, the SM with the minimum voltage, i.e., with index ind min , is inserted in the same polarity as N ins,j to charge it. That is, s ind min ,j = sgn N ins,j if N ins,j i j > 0.
2) If i j and N ins,j have different polarities, the SM with the maximum voltage, i.e., with index ind max , is inserted in the same polarity as N ins,j to discharge it. That is, if N ins,j i j ≤ 0, then s ind max ,j = sgn N ins,j .
For bypassing, i.e., N ins,j < i s i,j : 1) If i j and N ins,j have the same polarity, then the SM with the maximum voltage is bypassed, to halt its charging. That is, if N ins,j i j > 0, then s ind max ,j = 0.
2) If the current and insertion polarity are different, then the SM with the minimum voltage is bypassed, to halt its discharging. That is, if N ins,j i j ≤ 0, then s ind min ,j = 0.
The H5LC has eight discrete switching events where at all the cascaded FBSMs change polarity. Since the sorting algorithm above only produces the maximum or minimum FBSM capacitor voltage every T FPGA , the switching function needs an additional control layer for the polarity reversals of N ins,j . If such a reversal is expected, all the inserted FBSMs change their polarity, i.e., s i,j = −s i,j , as in Fig. 10. This process completes within one FPGA calculation time-step while providing functionality that the MMC-based FPGA switching functions do not have. Fig. 10 presents a flow diagram of the switching function. At t = 0 s, the sorting function begins to produce the variables ind max and ind min , which correspond to the indexes of the FBSMs with the maximum and minimum capacitor voltages. This process completes in t = 11t FPGA such that at t = 12t FPGA , the parallel sorting function outputs ind max , ind min , and done sort , which triggers the switching function.
The flow diagram of Fig. 10, Step 2, illustrates the switching function. Once it receives the done sort pulse, a quick comparison is performed to see if the insertion function, N ins,j , has changed polarity; if it has, then all switching indexes, s i,j , change polarity. Next, the insertion function is compared with the summation of the historical values of s i,j ; if they are equal, then the switching function is terminated. However, if they are not equal, the total number of historically inserted FBSMs is compared with the absolute value of the insertion function to determine if an FBSM should be inserted or bypassed. If N ins,j > i s i,j , then a FBSM is to be inserted; otherwise, one is bypassed. The polarity of N ins,j i j is then tested. If it is positive, we insert the FBSM with the minimum voltage with the index ind min to charge it, or we bypass the FBSM with the index ind max to halt its charging. Conversely, if N ins,j i j is negative, we insert the FBSM with the ind max to discharge it, or we bypass the FBSM with ind min to halt its discharging. After updating the values of s j , the switching function generates the done sw flag.

E. FBSM, FC, AND PC VOLTAGE GENERATION
In addition to its ability to quickly partially sort the 64 FBSMs, the FPGA also calculates the capacitor voltages of all 3 × 64 FBSMs, the six FCs, and the two PCs. For the purposes of the FPGA/CPU co-simulation, we assume that the current signals supplied to the FPGA from CPU 2 in Fig. 7 are multiplied by the time-invariant factors T FPGA /C SM , T FPGA /C FC , and T FPGA /C PC within CPU 2 prior to supplying them via the PCIe to the FPGA to reduce its resource usage. Multiplication is a computationally expensive and/or slow task for FPGAs, but is simple for CPUs.
The voltages of the FBSM capacitors, the FCs, and the PCs are initialized with a toggle bit, such that the initial FBSM capacitor voltages are 1 8N V DC , the FCs are initialized to V DC /4, and the PCs are initialized to V DC /2. After it VOLUME 11, 2023 receives done sw from the switching function, the FPGA triggers the current and capacitor voltage calculation modules of Fig. 7. With the elements of s j determined by the switching function, the FBSM capacitor voltages, v c,j , are updated with (12) for each of the 3 × 64 FBSMs. The output voltages of the cascaded FBSMs, v FB,j , are determined with (6). The six FC voltages are calculated with (23) and (24) and the two PC voltages are calculated with (21) and (22). With these, and T j provided by CPU 1, v 5LC,j of Table 1 is determined, enabling calculation of v nom,j and v blk,j .
This paper not only presents the analytical derivations for the H5LC, but also provides a framework for implementing it into CPU/FPGA co-simulations, which is a challenging task. In addition to the analytical derivations, the paper also includes an overview of CPU and FPGA inputs and outputs (shown in Fig. 7), an FPGA-based sorting method (described in Figs. 8 and 9), and a flow chart for determining individual SM switching signals (shown in Fig. 10). This paper is a significant contribution to the literature on accelerated simulation of HCMCs, as previous papers in this area (such as [20], which focuses on the H3LC) did not provide this level of detail.

V. PERFORMANCE EVALUATION
In this section, the real-time H5LC-UEM model is compared against the offline detailed-equivalent model (DEM). The DEM reduces the cascaded FBSMs to a single voltage source for improved offline simulation efficiency, but otherwise implements the detailed H5LC topology of Fig. 2. As [20] shows, the DEM produces results equivalent to the detailed model. For the online simulation model, the system under test includes the 600 kV VSC-HVDC H5LC-UEM modeled in CPU 2, as in Fig. 7. The real-time simulation uses the OPAL-RT RT-LABv2019.1 simulation environment with MATLAB/Simulink 2018a, and the offline simulation uses MATLAB/Simulink with the Simscape toolbox 2020b. For a fair comparison, the real-time and offline simulations use the CPU time-step of 50 µs. It is noted that the same parameters and test system are used for both offline and real-time simulations for a fair comparison of the dynamic simulations.

A. NORMAL OPERATION
For the nominal operation test, the H5LC is commanded to transmit 0.9 GW of real power to the grid at t = 0.1s, as in Fig. 11. At t = 0.4 s, the H5LC is commanded to operate as a rectifier, transmitting −0.9 GW of real power. Key waveforms illustrating this transient are shown in Fig. 11, and comparisons between the real-time H5LC-UEM and the offline DEM show that the FPGA-based H5LC-UEM produces results that are nearly identical to the offline DEM. Fig. 11 (b) shows that the phase-a currents of the UEM and DEM are indistinguishable. Figs. 11 (c) and (d) demonstrate that the individual FBSM capacitor voltages maintain the same shape. It is noted that the 15 FBSM capacitors from the offline and real-time simulation are randomly selected, and the VBA can effectively regulate differences between the individual capacitor voltages and their ripples. Fig. 12 presents zoomed-in plots over four cycles. Figs. 12 (a) and (b) present the phase-a five-level voltage, v 5LC,a , and cascaded FBSM voltage, v FB,a , for the online and offline simulations, wherein the results are indistinguishable. Fig. 12 (c) and (d) respectively present the phase-a upper FC voltage, v FC,u,a , and the upper PC voltage, v PC,u . Due to the sensitivity of the VBA of Fig. 4, the FCs show a minor discrepancy. This is because the offline simulation uses MATLAB's full double precision, i.e., 64-bit resolution, whereas the real-time simulation uses the 20-bit resolution. Hence, although the FC voltages are both initialized to 150 kV, the VBA of Fig. 4 may produce different results, which causes the slight DC offset, as seen in Fig. 12 (c). Since the PCs' voltages are balanced by the DC-side voltage source, no such DC offset occurs in their voltages, as Fig. 12 (d) shows.

B. DC-SIDE FAULT BLOCKING OPERATION
To illustrate that the FPGA-based H5LC-UEM produces accurate results through dynamic operations, the response to the DC-side short-circuit pole-to-pole fault is presented and compared for both the FPGA-based H5LC-UEM and the offline DEM in Figs. 12 and 13. At t = 1 s, a DC-side short-circuit fault lasting 200 ms is applied across the middle of 100 km DC cables, which use the π-section model. After 200 ms, the fault is cleared and the DC-side voltage ramps back up to its set-point value of 300 kV, which occurs approximately 110 ms after the fault is cleared, at t = 1.31 s. Once the PC charging transient settles, the FCs begin their energization process at t = 1.36 s. Thereafter, at t = 1.435 s once the FCs are charged, the real power is ramped back to its set-point of 0.9 GW.
Figs. 13 (a) and (b) present the transient responses of the real power and DC-side current during the fault process, wherein the UEM and DEM produce indistinguishable results. Fig. 13 (c) shows the sum of the 64 phase-a cascaded FBSMs' capacitor voltages, where the shapes of the UEM and DEM are virtually identical throughout the fault. The small discrepancy in Fig. 13 (c) can be explained by the difference in resolution between the offline MATLAB/Simulink DEM and the proposed FPGA model.
Figs. 14 (a) and (b) present the phase-a AC-side line-toground voltage, v a , and the converter current, i a , wherein the results of the UEM and DEM match well. From Fig. 13 (a), the bypassing action of the BTVs causes the swing in real power, which ranges from −2.45 GW to 1.25 GW. The phasea current corresponds to this power swing with a peak value of 8 kA. Since the BTVs and H5LC's DSs' free-wheeling diodes are rated for high currents, this transient is safe for the converter. Figs. 14 (c) and (d) show the phase-a upper FC voltage and the upper DC-side pole capacitor's voltage during the fault process. Throughout the fault process, recharging process, and FC energization process, the FC and PC voltages of the H5LC-UEM are observed to match those of the DEM.

VI. UEM SIMULATION EFFICIENCY AND RESOURCE CONSUMPTION
In this section, we compare the performance of the UEM and DEM for real-time and offline simulations. For realtime simulation, the minimum calculation time-step of the HVDC test system with the H5LC-UEM or H5LC-DEM are presented. For the offline simulation, the H5LC-UEM and H5LC-DEM are each simulated within a single CPU core, such that we present the execution time of a one-second HVDC simulation with varying numbers of FBSMs. Table 2 shows the execution time of the offline simulations and the calculation time required for the real-time simulations, where it is noted that the number of FBSMs for the real-time simulations has no bearing on the computational burden of the CPU since the sorting and calculation of the SM capacitor voltages are performed within the FPGA. Table 2 shows that the H5LC-UEM has significantly higher simulation efficiency than the H5LC-DEM for the offline simulation, with the largest improvement for smaller numbers of FBSMs. Since the entire systems including the controls and FBSMs are calculated on the same CPU core, the overhead increases proportionally to the number of FBSMs. Hence, as the number of FBSMs increases, the execution times of the models converge.
For the CPU cores CPU 1 and CPU 2 of Fig. 7, RT-LAB enables measurement of the execution time per time-step. Table 2 shows the minimum CPU 2 execution time for real-time simulation, where CPU 2 models only the HVDC system, precluding the FPGA-calculated FBSM capacitor voltages. CPU 1 is common to both the H5LC-UEM and H5LC-DEM and has a minimum execution time of 2.40 µs. The results show that CPU 2 calculates the H5LC-UEM 34.5% faster than it does the H5LC-DEM without any loss in simulation accuracy. Hence, for HVDC systems with many H5LCs, or other HCMCs, the H5LC-UEM enables 34.5% fewer CPU cores which has significant implications regarding simulation cost savings.
In Table 3, we show the resource consumption of the Virtex-7 FPGA, which is used to calculate the voltages of the 192 FBSMs, FCs, and PCs and to perform the sorting and switching functions of Figs. 8 to 10. For reference, its resource consumption with 256 FBSMs per phase is also shown. Table 3 shows that despite performing many high resolution 2 −30 V) voltage calculations, only approximately a quarter of the FPGA's look-up tables (LUTs) are used for 64 FBSMs and 60.36% are used for 256 FBSMs. Due to the overhead of the transmission of data between the CPU and FPGA, the values of Table 3 do not scale proportionally with the number of FBSMs.

VII. CONCLUSION
This paper proposed a new universal converter equivalent model (UEM) for the real-time simulation of complex hybrid converters such as the H5LC and other HCMCs. The UEM reduces the computational load of the H5LC on the CPU by using the proposed simplified converter equivalent circuit, composed of controlled voltage sources, diodes, and ideal switches, which are elementary circuit components available by most simulation software. With the reduced CPU load enabled by the UEM, the real-time simulation is achieved for the H5LC by means of the FPGA computing the voltages of all the FBSMs' capacitor voltages, FCs, and PCs. Additionally, the FPGA model implements the various lowerlevel controls, including the FBSM capacitor voltage sorting algorithms, the FC voltage balancing algorithm, and the switching functions. The FPGAs are programmed such that the polarity reversals of the H5LC's (and other HCMCs') cascaded FBSMs occur within a single FPGA calculation cycle, which is a novel functionality that is absent from previously proposed FPGA implementations. OPAL-RT's OP5700 realtime simulator executes all of the aforementioned converter functions within its CPUs and on-board FPGA. The accuracy of the CPU/FPGA co-simulation of the H5LC-UEM is verified using an offline DEM model of the H5LC for both nominal and DC-side fault operations. With the computational savings enabled by the UEM, the H5LC and other HCMCs can be integrated into large-scale real-time HVDC simulation schemes.