Two New Common Ground Extended-Boost Active Quasi Z-Source Inverter With Reduced Passive Components

A high voltage gain inverter is a critical component of any high voltage power system, which feeds from a limited DC source. Numerous inventive solutions proposed to increase the boost factor. However, many of them have a large number of components and no short circuit immunity. While retaining the inherent characteristics of conventional quasi Z-source inverters (qZSI) with fewer components, this paper proposes two new active impedance source inverters based on qZSIs that utilize an additional active switch. In addition to the inherent benefits of qZSIs, the proposed topologies have a higher boost capability. They have an additional degree of freedom that allows the voltage ratio of the capacitors adjusted to any desired value without affecting the gain of the converter. They can also control the dc-link voltage without being fully dependent on the shoot-through time duration, resulting in a higher utilization factor for the dc-link. Additionally, the proposed topologies establish a common-ground connection between the input and output terminals, which is useful for some applications. In order to drive the inverters’ boost factor, the operation and steady-state analysis described. Furthermore, the comparative analysis done to illustrate the features of proposed topologies. Finally, a simulation and experimental analysis carried out to validate that the proposed inverters are feasible.


I. INTRODUCTION
In addition to electromagnetic interference (EMI), the ability to only perform buck operation and the need to provide dead-time to the bridge's legs are two of the most significant drawbacks of systems that use conventional voltage source inverters (VSI). The DC-DC power stage is the conventional method for boosting low-level DC voltage. Since two-stage conversion resulted in low efficiency, Peng [1] was the first to introduce Z-source inverters (ZSI). ZSIs provide EMI immunity and enhance reliability by eliminating deadtime and enabling buck-boost power conversion in a single stage. Nonetheless, this solution hampered by start-up inrush current, a high passive component rating, a discontinuity of input current, and the absence of a common ground between the input and output of the impedance source. The quasi The associate editor coordinating the review of this manuscript and approving it for publication was Yuh-Shyan Hwang . Z-source inverter (qZSI) was introduced in [2] as a means of overcoming these drawbacks without sacrificing the benefits.
It inherits all the advantages of ZSI and none of the aforementioned disadvantages. Several types of high-boost modifications presented in order to increase the boost factor by adding extra capacitors, inductors, and diodes to the traditional ZSI/qZSIs. Reference [3], [4], [5], [6], [7], and [8].
The mains are referred to as diode-assisted [3], capacitorassisted [5], and switched-inductor [8] buck-boost inverters. As shown in Fi. 1, these topologies utilize numerous components, which increases the cost and size.
Using a transformer-based ZSI/qZSI structure [9] is another potential solution; however, these structures degrade the signal quality by generating spikes at the DC-link due to transformer leakage inductance. Thanks to an additional active switch, switched boost inverters (qSBI) can provide the same features with fewer passive components, resulting in a more efficient cost-benefit ratio and a smaller inverter [10]. Among them is the utilization of switched capacitor (SC) technique. The SC technique employs a lesser number of DC sources in accordance with the voltage across the capacitor [11]. Based on how the impedance network formed by combining passive and active elements with the new active switch, [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22] present a series of high-gain switch boost inverters. The topologies presented in [12] and [13] are based on the switched capacitor technique, and despite having a high gain, they employ a large number of components. The same issue that exists in the majority of presented topologies.
This paper presented two new topologies as a potential solution by adding one switch and one diode to the traditional qZSI: continuous current current active quasi Z-source inverter (CC-AqZSI) and discontinues current active quasi Z-source inverter (DC-AqZSI). These topologies have an additional degree of freedom because of the additional switch, allowing the voltage gain and modulation index adjusted independently of the shoot-through time. This feature allows the capacitors' voltage to be set to the desired level, which is useful for establishing an adjustable midpoint.
The structure of the reminder of the paper is as follows: Section II presents the structure of topologies. Section III discusses the steady-state operating principle analysis and the derivation of the boost factor. Section IV contains the parameter design guidelines. Small-signal analysis and comparison of characteristics with other high boost inverters presented in Sections V and VI, respectively. Section VII is where simulation and experimental verification take place. Finally, Section VIII contains the conclusion.

II. CONFIGURATION OF THE PROPOSED TOPOLOGY
The proposed inverter topology depicted in Fig. 2. The boost factor of both topologies is the same, as will be demonstrated later; however, the CC-AqZSI has a continuous input current, whereas the DC-AqZSI has a lower stress voltage on the input capacitor. The structure of these topologies is straightforward and has the same number of components. They made up of a traditional qZS (L 1 , L 2 , C 1 , C 2 and D 1 ), an extra switch (Sd), diode D 2 , a standard three-phase, two-level bridge (Sij, where i= 1 to 2 and j=a, b, c), an output filter (L f , C f ) and a three-phase load resistance R. CC-AqZSI, thanks to the series input inductance, can suppress inrush current during startup, whereas DC-AqZSI has a lower capacitance stress voltage.

III. OPERATION PRINCIPLE OF THE SUGGESTED INVERTER
In this section, the operating principles of these two topologies thoroughly described and discussed. To simplify the analysis, we assume that all AqZSIs components are ideal and that all passive components are linear, time-invariant, and frequency-independent. The dead time intervals are short enough to be ignored, and the impedance network's capacitances are sufficient to keep the capacitor's voltage constant.
There are two distinct operating modes for the inverter: non-ST and ST. The equivalent circuits of these modes for CC-AqZSI and DC-AqZSI depicted in Fig. 3 and 4, respectively. As shown in Fig. 2 and 3, the most significant difference between these topologies and the conventional structure is that in the proposed structure, the inductor L 2 can be in either charging mode (d1-state) or non-charging mode (d2-state) without needing AqZSI to operate in shoot-through mode. The operational principles of the proposed AqZSIs described by the switching states listed in Table 1.  [4], (b) Extended-Boost ZSI [5], (c) Embedded Switched-Inductor qZSI [6], (d) Enhanced-boost qZSI [7].

A. SHOOT-THROUGH OPERATING MODE
The ST-mode for CC-AqZSI is depicted in Fig. 3(c) and 3(d) where type-1 and type-2 indicate wether S d is turned on and off. In this mode, all power switches (S ij ) are turned on and conducted simultaneously from at least a phase leg of the bridge. In ST-mode, the voltage of S d is zero, and whether it is on or off has no effect, as there is no power transfer to the load. Inductor L 1 energized through both input voltage source and capacitor C 2 , while capacitor C 1 discharges energy to inductor L 2 . Also, unlike D 2 , diode D 1 is reverse-biased. The time interval of ST-mode is d ST .T S , where d ST is the ST time duty ratio of the inverter bridge and T S is the switching period.  As shown in Fig. 4(a) and 4(b), the operation principle of DC-AqZSI is similar to that of CC-AqZSI, with the exception that inductor L 2 charged by both C 1 and the input voltage source. The following equations obtained by using KVL and KCL for CC-AqZSI and DC-AqZSI, respectively B. NON-SHOOT-THROUGH OPERATING MODE d1-state: Fig. 3(a) and 4(a) depict the equivalent circuit of d 1 -state for CC-AqZSI and DC-AqZSI, respectively. As illustrated, there is no short-circuit in the bridges for this state, and the switch S d is open. There is no difference between this state and that of traditional qZSIs because the extra diode D 2 is conducting and has no effect on the circuit. The time interval of this operating mode is d 1 ·T S . By applying KVL and KCL for this state, voltage and current relations extracted as (3) and (4) for CC-AqZSI and DC-AqZSI, respectively where i PN is the average DC-link current in non-ST modes [15].

d2-state:
In this mode, there is no short-circuit in the bridges and switch S d is turned on, as Fig. 3(b) and 4(b) show, same as ST-state, inductor L 2 is in charging mode, Diode D 2 is reverse-biased and the rest of circuit is the same as d 1 -state. The time interval of this operating mode is d 2 ·T S , where d 2 is the time during which S d is conducting. During non-shootthrough-d 2 state, it is possible to extract inductor voltages and capacitor currents as (5) and (6) for CC-AqZSI and DC-AqZSI, respectively The voltage gain of CC-AqZSI is deduced by applying voltage balance law across the inductors and taking into account that each periodic time is divided into three parts of d 1 , d 2 , and d st .
Considering (7)- (9), the voltage of the capacitors calculated as follows Using the same method for DC-AqZSI, we have Consequently, for both topologies, the dc-link voltage and boost factor B of the inverter calculated aŝ The inverter's inversion voltage gain G defined as (15) whereV o denotes the peak load voltage, and M is the modulation index. The relationship between M and B is determined by the PWM control strategy used. In this paper, like [14], the simple boost control (SBC) is applied. As a result, the modulation index is constrained by the ST duty ratio, as illustrated bellow By considering the highest modulation index, the maximum peak load voltage can be extracted aŝ whereV PN is the mean voltage of the inverter dc-link.
As it is evidenced from (9) and (11), the most significant contribution of the proposed topology is the addition of one degree of freedom to the impedance network, which increases the gain factor while simultaneously controlling the capacitors voltage level. This contribution makes these topologies useful for some symmetric and asymmetric multilevel inverters, needing a controlled midpoint besides boosting input voltage. In this regard, three-level diode clamped inverter, four-leg, and fault-tolerant inverters are some examples of applications for which the proposed topologies can be helpful.

IV. INDUCTOR AND CAPACITOR DESIGN
Due to the operation principles, inductor currents are influenced by the ST state and rise rapidly. The current ripple of inductors and the associated value of inductors can be calculated using (1-6), (9), and (11) as below for CC-AqZSI and DC-AqZSI respectively.
where n is the number of shoot-through states that happen in one switching period. Operation principle shows unlike conventional qZS networks, the charging times of inductors are different. Same as capacitors voltage, by applying the amp-second balance property of capacitors C 1 and C 2 , the average current across inductors in steady-state is calculated as follows.
where R L is the ac side circuit's simplified equivalent, DC load [23]. By these considerations, the average inductors' VOLUME 11, 2023 current, which is equal to the average current of the input source, derived as follows Further, concerning (1-6), (9) and (11), for both topologies, capacitors' voltage ripple and therefore, the corresponding capacities extracted as follows

V. SMALL-SIGNAL DYNAMIC ANALYSIS AND CONTROL METHODOLOGY
For small-signal analysis, the output load simplified further by modeling it as a simplified equivalent dc-inductive load [23]. In this circumstance, the voltage and current of the load are identical to those of the dc-link. Using the procedure outlined for small-signal analysis in [23], the transfer function of capacitor voltage with respect to d st (s), after the necessary simplifications, is as follows. Fig. 5 depicts the Bode plot of the system described as (20), for two different input voltages, in order to analyze the stability of the proposed. As evidenced, at the crossing frequency, the slope of the graph is -20db/dec and all the poles of the system are located on the left side, proving that the system is stable for different inputs.
For the AqZSI as with other standard qZSIs, the ac-side can be controlled independently of the dc-side; therefore, the method described in [24] has been employed for this purpose. Given that this voltage is not continuous, it is not possible to obtain direct feedback from the dc-link in order to control it. To solve this problem, the voltage of the capacitors is used. The block diagram of the dc-side control method depicted in Fig. 5(b). Due to the non-minimum phase property of the capacitor voltage, the inductor reference current is initially determined by a PI controller and then fed to a second controller, which determines the final value of d st .
In each of these stages, the value of d 1 is constant and predetermined.

VI. PERFORMANCE COMPARISON
Utilizing an inverter with a high voltage gain at higher modulation index, preferably with fewer components, is one of the most important factors for enhancing voltage quality. In this section, several non-transformer-based high voltage gain topologies compared to the proposed inverter's characteristics, and an in-depth comparison analysis presented. Table 2 provides a comprehensive comparison between the proposed topology and other similar topologies. Fig. 1 and 2 demonstrate that, in comparison to other high voltage gain qZSI topologies that do not employ an active switch, the proposed topologies reduce the number of passive elements significantly. They simultaneously increase the boost factor. In contrast, as shown in Table 2, this topology employs fewer or an equal number of components compared to other similar topologies. The only [22] has a smaller capacitor, but it does not share a common ground between input and output terminals and instead employs numerous diodes.

B. COMPARISON OF THE BOOST ABILITY
Since the proposed topologies have one more degree of freedom, it is preferable to demonstrate the boost capability in three-dimensional space. Based on the values of d 1 and d st , the boosting capability of the proposed topologies can vary substantially, as shown in Fig. 6(a). For instance for d 1 =0.2, the boost factor is equal to Although theoretical value can reach infinity, parasitic effects will limit the experimental boost factor. Fig. 6(b) compares the boosting ability of proposed topology for d 1 = 0.25; as shown, the boost factor of the proposed is greater than all others.

C. COMPARISON OF THE CURRENT AND VOLTAGE STRESS
Current and voltage stress of components is one of the most crucial parts of qZS inverters. Fig. 7 depicts a comparison of the current and voltage stresses of all devices utilized in various topologies. Fig. 7(a) shows the current stress of the inductors. Evidently, the majority of topologies contain inductors with unequal currents. Comparing the proposed inductor current to the maximum inductor current of other topologies reveals that, with the exception of [18], the proposed current is identical to that of all other topologies. The voltage stress on capacitors, diodes, and the additional switch depicted in Fig. 7(b), 7(c), and 7(e), respectively. As seen, in the majority of topologies, components within the same category do not have identical values, and one topology cannot be favored over another. Comparing voltage stresses reveals that the proposed topology has acceptable voltage stresses, and in many cases, including diodes and switches, it has less voltage stress. Fig. 7(d), 7(f), and 7(g) depict, respectively, the current stresses of diodes, the additional switch, and the shootthrough state for all topologies.
As with voltage stresses, the proposed topology has excellent performance in this instance. In the meantime, although the shoot-through current of the proposed topology like [22] is greater than that of the others, it has the lowest current stress in the additional switch, which reduces the switch losses and improves efficiency.

D. POWER LOSS AND EFFICIENCY COMPARISON
The system losses made up of the losses of inductors, capacitors, diodes and switches utilized in the system.

1) LOSSES OF INDUCTORS
Inductors account for the majority of the system losses. Using (18) to get the rms value of inductor current, the inductor losses calculated as follows

2) LOSSES OF CAPACITORS
Capacitor current in different working modes is determined as follows After determining the capacitor current's rms value, its power loss estimated as follows

3) LOSSES OF DIODES
The current of the diodes that vary from one another is equal to The average and rms value of the current flowing through the diodes used to calculate the three forms of losses present in diodes: a reverse recovery loss and two types of conduction power loss.
where Q rr represents the reverse recovery charge of the diode and f s refers to the switching frequency.

4) LOSSES OF SWITCHES
Switch losses are divided into two categories: conduction power loss and switching power loss. The following describes the switches current in their distinct operating modes.
The delay durations for turning switches on and off are denoted by t on and t off , respectively, and r s is the drain-tosource resistance of switches. The value of the internal parasitic parameters shown in Table 3. Based on that, Fig. 9(b) shows and compares Loss distribution percentage of the proposed topology. As observed, a significant proportion of losses related to the inductors. Fig. 9(c)-9(e) compare the losses of the proposed topology to those of the other topologies in various ways. As can be seen, the proposed topology has lower losses than the others except [15], indicating the proposed topology's relative superiority over them. Fig. 9(a) compares the efficiency of different topologies. As expected, AqZS has better efficiency than other topologies with the exception of [15].

E. COMPONENT STRESS FACTOR (CSF) CALCULATION AND COMPARISON
One of the most effective methods for analyzing and comparing alternative topologies for a particular application is its Component stress factor (CSF). The method calculates converter stresses and provides a quantitative performance measurement. To do this, the CSF value of capacitors (CCSF), inductors (WCSF), switches (SCSF) and diodes (DCSF) is determined as follows where W i is the given individual weight for component i and k W k is the total of the individual weight factors. Fig. 8(c)-8(f) compares the CSF values of different components of the proposed topology with other topologies. As can be observed, the suggested topology yielded the best results when compared to other topologies, with the exception of CCSF, where [15] and [16] yielded superior results. This means that the proposed topology has an appropriate current stress, reconfirming that it has more favorable qualities than the others.

F. SWITCHING DEVICE POWER (SDP) CALCULATION AND COMPARISON
The highest impressed voltage, as well as the peak and average current, are among the selection criteria for switching devices in inverters. For this regards, the SDP index developed. The SDP of a switching device or cell is the product of the voltage and current stresses and described as follows In AqZS, the current that passes through the inverter is the shoot-through current during the d st time period and the load current at all other periods which, owing to symmetry, is split evenly across the switches.
Using (28) and the shoot-through current value and due to the symmetry, the average current of switches derived as The maximum voltage on the switches formed when the output power is zero and the dc-link voltage is at its maximum value. In this instance, we will have SDP avg = 6 * V s(max) I s(avg) = 6 * V pn I s(avg) In addition, when the line current of phase A is at its peak and the output is short-circuited, the inverter switches'  Repeating this method for diodes and the additional switch yields the SDP value of the system. The average SDP and peak SDP of the proposed topology compared to those of other topologies in Fig. 8(a) and 8(b). As can be observed, the suggested topology has the lowest average SDP value, with the exception of [16]. In addition, its peak SDP value is smaller than [22] and [18]. The obtained results indicate that the proposed topology is a cost-effective and SDP-compliant option.

VII. SIMULATION AND EXPERIMENTAL RESULTS
The performance of the proposed topologies verified with simulation and experimental results. The simulations are done with Simulink MATLAB, while laboratory prototypes carry out the feasibility. The input voltage varies from 30 to 140 volts, and the switching frequency is set to 20 kHz. Table 3 demonstrates the circuit parameters used.
A. SIMULATION RESULTS Fig. 10(a) depicts the simulation results of the proposed CC-AqZSI with d1=0.2, dst=0.08, andV PN = 500V . Since the desired peak output voltage is 155 volts (110 Vrms) for an input voltage of 60 V, as shown in Fig. 10(a), the capacitor C1 and C2 voltages are 99 and 398 volts, respectively, which are slightly lower than the values calculated in (9) due to the parasitic parameters considered in the simulation. The DC-link voltage increased to 498 V, which is consistent with the analytical results. The peak-to-peak of inductor current ripple is 1V and 1.8V for L 1 and L 2 respectively which almost agrees with (15). The same procedure is carried out for the proposed DC-AqZSI, but with an input voltage of 90V, d1=0.6, dst=0.3, andV PN = 500V ; the results are depicted in Fig. 10. (b). As anticipated, the voltages of C 1 and C 2 changed to 150V and 197V, respectively, which is almost agree with (11). The peak-to-peak current ripple of the inductor is 2.2V and 2.45V for L 1 and L 2 respectively, which, as anticipated, is greater than that of CC-AqZSI and roughly coincides with (16). The dc-link voltage is 498 V, which is nearly identical to CC-AqZSI voltages. Fig. 10(c) depicts the voltages and currents of the output phase. The RMS value of voltage is 110V, and there is no voltage or current distortion.

B. EXPERIMENTAL RESULTS
A 1-kVA prototype was constructed and utilized to validate the simulation and analytical results. Table 3 lists the value of prototype component parts. Fig. 11 is a photograph of the hardware configuration. It consists of an impedance network circuit, a DSP controller, a measuring unit, a driver board, an output filter, and a 1-kVA controllable. The inverter bridge performed by an FP40R12KT3 module, ensuring greater compatibility and a more compact circuit. Here, we performed all active components of the impedance network with the same module.
A DSP TMS320F28335 controller generates PWM control signals with a triangle frequency of 20 kHz. The drive circuits utilized the ISO5852 smart and high-performance gate driver IC from Texas Instruments, which has a very high common-mode immunity of 100 kV/us. Fig. 12 shows the practical results for CC-AqZSI with Vin = 60V and d 1 = 0.2. The control system is set to maintain the dc-link voltage at 500V. Fig. 12(d) shows that the capacitor C 1 and C 2 voltages are 98V and 397V, respectively. They differ slightly from the theoretical results since the parasitic found in the experiment. Fig. 12(c) also demonstrates that the dc-link voltage is square and remains maximum unless the bridge's legs shorted. The peak voltage of the dc-link is 494 V, which is close to the set value of 500V. The experimental results prove that the inductor currents have two different charging and discharging patterns. It shows that, L 2 is charged twice per cycle, as opposed to the L 1 , which is charged only in ST-mode. Furthermore, the intensity of its changes is greater than the L 1 inductor, consistent with the theoretical results.   (11), dst increased to 0.28, and d 2 decreased to 0.32. As the ST-mode increases, the peak-to-peak inductor current ripple of L 1 and L 2 increases to 1A and 2.5A, respectively. Furthermore, the voltages of capacitors C 1 and C 2 have been changed to 197V and 295V, which are acceptable despite being slightly lower than the theoretical results. The same procedure followed for the proposed DC-AqZSI. Fig. 14 depicts the practical results for the DC-AqZSI with an input voltage of 90 V and d1 = 0.3. Fig. 14(d) shows that the capacitor voltage for this topology equals 58V and 345V, respectively. These values are lower than the calculated value for CC-AqZSI but agree with (16). Except for the voltage of the capacitors, other waveforms, particularly the dc-link voltage, follow the same rule described previously for CC-AqZSI and do not affected by topological changes. Using this method, it is simple to determine the voltage of the capacitors so that the voltage at the point of connection between two capacitors is equal to half the voltage of the dclink; this point considered the middle point of the inverter. With this method, the impedance network used for three-level  inverters. In general, Fig. (12)- (14) show that the DC-AqZSI topology is only effective when the input voltage and d1 are both high. Under these conditions, the capacitor voltage is minimal and significantly different from CC-AqZSI. In other cases, the CC-AqZSI topology is preferred and recommended due to the continuity of the input current. Fig. 15 depicts the experimental waveform of the output voltages during the transient state when the load power increases from 700 w to 1000 w while the input voltage set to 100 V. In accordance with the applied control policy, the input current increased in response to the increase in output current and power, and the load voltage stabilized at its previous levels. Fig. 16 depicts the dynamic response of the system when the input voltage stepped from 60V to 90V and the load remains constant at 1000 w. As expected, thanks to the controller's proper operation, the input current is gradually decreasing, and the output voltage and current stabilized at their previous levels.

VIII. CONCLUSION
This paper presented two novel Active impedance source inverters based on the quasi Z-source inverter with a high voltage gain and a lower component count. Except for input current continuity and capacitor stress voltage, the gain of both topologies is identical. In addition to the control system's specifics, the analysis of the circuit and guidelines for parameter selection presented. In addition, comparisons between the proposed topologies and other similar topologies reveal that they have an additional degree of freedom, allowing for a wide range of gain and capacitor voltage adjustments. The introduced topology has favorable characteristics, and the current and voltage stresses of the internal components are superior or comparable to those of other topologies. The simulation and prototype results confirm the feasibility of the proposed topologies.