A New Non-Isolated Active Quasi Z-Source Multilevel Inverter With High Gain Boost

This paper proposes a three-level diode clamped active impedance source inverter (AIS-TLI) based on the quasi Z-source inverter (qZSI). Apart from having minimal components and the inherent benefits of three-level qZSIs, such as single-stage buck-boost capability, shoot-through (ST) immunity, and continuity of input current, the proposed topology has a higher boost capability and excellent efficiency. In addition, the inverter bridge has a higher modulation index, which improves the quality of the output waveform and necessitates less inductance. The proposed topology provides common ground between input and output terminals, which effectively eliminates leakage current in PV-powered single-phase systems. This paper describes the different operating modes principle, dynamic analysis, steady-state analysis, and parameter selection instructions for the proposed in-depth. Furthermore, the suggested inverter’s benefits and limitations are compared to the traditional (q)ZSIs and some other AIS-TLIs. Finally, modeling and experimental results are used to confirm the effectiveness of the suggested topology.


I. INTRODUCTION
Three-level diode-clamped inverters offer several advantages versus traditional two-level voltage source inverters (VSIs), including two times lower voltage stress on semiconductors, higher power capacity, and lower switching losses that result in higher switching frequency, better output waveform quality, smaller filter size, reduced dv/dt, improved harmonic performance, and the lack of a transformer required at the level of the distribution voltage [1], [2], [3], [4], [5], [6]. Typically, an additional DC-DC step-up converter employed to enhance the inverter voltage boosting capability. Reference [1] proposes a high step-up DC-DC converter based on the Cockcroft-Walton (CW) voltage multiplier. The proposed converter does not require a step-up transformer and is well suited for DC generation systems with low input levels. Reference [2] discusses a new three-level uninterruptible power supply (UPS), which uses a push-pull boost circuit to interface with the battery bank and the DC bus. Compactness The associate editor coordinating the review of this manuscript and approving it for publication was Javier Moreno-Valenzuela . in its future implementation, another topology based on the Cuk-derived buck-boost method presented in [3].
Although [1], [2], [3] present some beneficial topologies of traditional TL boost inverters, none of them can provide shoot-through (ST) immunity. Hence, employing dead time between the switching control signals is inevitable, but this additional dead time distorts the output AC voltage and degrades the inverter's output waveform quality. To cover this shortcoming, the impedance network solution is one of the creative ideas which can be added to the three-level Neutral point clamped inverter (TL-NPC).
common-mode voltage and leakage current suppression.
Since the traditional space vector modulation (SVM), is unable to address the problem of neutral-point potential (NP) balancing, [6] presents an improved SVM approach based on modifying the time of the classic symmetric SVM.
Although the single LC-TLI has a minimal passive component, it has several disadvantages, including high voltage stress across switches and capacitors, significant inrush current, and restricted boost factor. To mitigate some of these drawbacks, [7] introduces another type of ST immune, single-stage impedance source topology by using a combination of a three-level inverter with two symmetrical Z-source networks (2PIS-TLI). Trying to form another topology with continuous input current characteristic, [8] introduces a different 2PIS-TLI by combining two quasi Z-source inverters.
In [9] and [10], some other 2PIS-TLI have been presented, which can effectively decrease the stress voltage of the Z-source capacitor and prevent starting inrush current, especially in [9], thanks to applying level shifted and SVM method, the neutral-point voltage will also balance. As seen in Fig. 1, 2PIS-TLI utilizes a significant number of passive elements, increasing the inverter's weight, cost, and volume. One way to reduce the number of passive elements in traditional PIS topologies is incorporating some active switches. Compared to PIS-TLIs, active impedance source (AIS) inverters have a smaller inductance and capacitance but implement more switches and diodes. In [11], a new topology based on the inverse Watkins-Johnson topology is introduced for low-power applications, where the topology is called the switched boost inverter (SBI). Inspired by this topology, [12] proposes a new topology for a three-phase NPC inverter. The proposed topology offers all the features of a multilevel quasi-Z-Source inverter with the benefit of fewer passive parts. Since multilevel inverters contain more power semiconductor components, the failure rate increases that results lowering reliability; hence in [13] and [14], two different SBI topologies are applied to a fault-tolerant TLI. The main contribution of these topologies counted as high gain boost and operating safely even if the inverter's power switches are open-circuited. Enhancing voltage gain despite lowering capacitor voltage stress, two new quasi switch boost (qSB) based inverters have been presented in [15] and [16], which their benefits achieved through the application of a modified PWM control approach.
By examining these topologies, it is concluded that the most shortcomings they share are the higher ST duty ratio, lower modulation index availability, and lesser boosting capabilities. Furthermore, the majority of these topologies use two distinct impedance networks, which means deploying single split or two independent DC voltage sources with many other components. To address most of these shortcomings, this paper proposes two new configurations of a single-stage AIS-TLI. The proposed topologies have a single non-split source with lower passive elements, which is based on the qZSI definition, so they called active quasi Z-source neutral point clamped (AqZS-NPC) inverter. Compared to [16], [17], and [12], the proposed topologies save one switch. They have higher voltage gain than traditional PIS-TLI and most of AIS-TLIs, meaning a better DC-link utilization factor. They also have a continuous input current and an adjustable midpoint, which is beneficial for using in asymmetric NPCs. Fig. 2 illustrates the proposed inverter configuration. Both topologies provide the same function. However, the second one saves a diode. Since the topology with separated midpoint is inconvenient for commercially available NPC modules, in this paper, the study is made on the topology depicted in Fig, 2(a).

II. CONFIGURATION OF THE PROPOSED TOPOLOGY
This topology consists of two inductors (L 1 , L 2 ), two capacitors (C 1 , C 2 ), three diodes (D 1 , D 2 , D 3 ), an additional active switch (S d ), twelve switches (S ij , where i= 1 to 4 and j=a, b, c) to form a three-phase three-level diode clamped inverter bridge, and a three-phase filter (L f , C f ). Compared to the traditional qZSI, additional passive and active elements (D 2 , D 3 , S d ), improve the specification of qZSI and make the proposed configuration suitable for TL-NPC inverters. Therefore, as discussed later, the obtained inverter will have a better boost capability, resulting in a higher modulation index with a lower ST duty ratio. Furthermore, unlike traditional PIS-TLIs, the proposed inverter employs lower inductances as well as a single non-split DC source. It shares a common ground between input and output terminals while the qZS-based impedance network, ensures continuity of the DC source current.

III. OPERATION PRINCIPLE OF THE SUGGESTED INVERTER
In this section, the operating principle of these two topologies is thoroughly outlined and discussed. For the sake of analysis simplicity, we assume that all the components of the AqZS-NPCs are ideal and all of the passive components are time-invariant, linear, and frequency-independent. The dead time intervals are short enough to be ignored, and the impedance network's capacitances are large enough to keep the capacitor's voltage constant. The suggested inverter can operate in two distinct states: non-ST and ST. Fig. 3 depicts the suggested scheme's corresponding circuits in these modes. As evidenced in Fig. 3(a) and 3(b), in non-ST mode, capacitor C 1 is in charge or discharge mode depending on the state of switch S d . The switching states indicated in Table 1, describe the operational principles of the suggested AqZS-NPC. Fig. 4 indicates the proposed inverter's steadystate voltage and current waveforms. As shown in Fig. 4, because of d2 implementation, the frequency of capacitors and L 2 increased, which results in more smooth voltage and current waveforms of them respectively.   simultaneously. As evidenced, in ST-mode, the voltage of S d is zero and there is no change in the circuit function, if S d is turned on or off. Under these conditions, power is not transferred to the load, and the input voltage source along with capacitor C 2 energize inductor L 1 , while capacitor C 1 discharges energy to the inductor L 2 . The current flow across diodes (D 1 , D 2 ) reduced to zero, and all of them are reversebiased. The time interval of ST-mode is dst.Ts, where dst is the inverter bridge's ST time duty ratio and Ts is the switching period. When KVL and KCL are applied to Fig. 3(c) or 3(d), the following equations are obtained:

A. SHOOT-TRHOUGH OPERATING MODE
The operation principle of this mode is similar to that of a traditional qZS impedance network. Fig. 3(a) depicts the equivalent circuit for the d1-state. In this mode, there is no short circuit in the bridges, and switch S d is turned off. Diodes D 1 , D 2 , and D 3 conducted, and Capacitor C 1 is fed by Inductor L 1 and the input source. In contrast, Inductor L 2 discharges energy to capacitor C 2 . The time interval of this operating mode is d1·Ts. By applying KVL and KCL, for this VOLUME 11, 2023 state, voltage and current relations can be extracted as In which a simple current source I PN is used to represent the external load.
2) d2-state Fig. 3(b) shows the equivalent circuit of the d2-state. Throughout the active d2-state, switch S d is turned on, and like d1-state, there is no short circuit in the bridges. In this mode, both diodes D 1 and D 2 are conducting while diode D 3 is reversed-biased. Capacitor C 1 continues to charge by inductor L 1 and the input source while simultaneously discharges energy to Inductor L 2 . The time interval of this operating mode is d2·Ts, where d2 is the time which S d is conducting. During non-shoot-through-d2 state, it is possible to extract inductor voltages and capacitor currents as

C. BOOST FACTOR CALCULATION
Since each period is divided into three parts d1, d2, and dst, as it is evidenced from Fig. 4, we have By considering the volt-second balance property of inductors L 1 and L 2 , the average steady-state voltage of the inductors over one switching period Ts is zero. Since each period is divided into three parts d1, d2, and dst, from (1) to (4), we have Considering (4)-(6), we can calculate the voltage of the capacitors as follows As a consequence, in non-ST state, the maximum voltage of the DC-link isV As a result, the suggested inverter's boost factor B can be calculated as The inverter's inversion voltage gain G is defined as (10) whereV o represents the peak load voltage, and M represents the modulation index. Applied PWM control strategy determines the relationship between M and B. In this paper, like [21], we use the simple boost control (SBC), so the modulation index is limited by the ST duty ratio, as shown below By considering the highest modulation index, the maximum peak load voltage can be extracted aŝ whereV PN is the mean voltage of the inverter DC-link. Although in the proposed AqZS, capacitor voltages are different and depend on the values of d 1 and d st , as it can be seen in Fig. 4(a), the voltage of capacitor C 1 should be equal to the half ofV PN to make a suitable midpoint for the NPC inverter. Therefore from (7), (8), and (12), the value of d 1 for a balanced DC-link AqZS-TLI should be as follow By having the above consideration, the voltage of capacitor C 1 is set to half of the peak value of the DC-link, but the boost factor's degree of freedom reduced to one, and the gain factor is modified as According to (14), although the proposed topology is only made up of traditional qZS, a switch and extra one or two diodes, it has a better boost factor than other topologies which use two or more combinations of qZS. Furthermore, as can be deduced from (7) and (14), the proposed AqZS offers an adjustable midpoint voltage. Equation (7) shows, by changing d1, without a necessity of changing dst or any active or passive devices, the midpoint voltage can change easily, which shows the benefit of utilizing this topology for unbalanced NPC as well as fault-tolerant inverters. Fig. 5 depicts the wide boosting ability of the suggested topology with two special cases, where the peak value of the midpoint is 1/3 and 1/2 of the peak value of the DC-link are highlighted.

IV. INDUCTOR AND CAPACITOR DESIGN
Due to the operation principles, inductor currents are influenced by the ST state and rise rapidly. The current ripple of inductors and the associated value of inductors can be calculated using (1-3), (7), and (9) as below.
where n is the number of shoot-through states that happen in one switching period, substituting (13)- (14) into (15), the inductance values of L 1 and L 2 can be designed as follows.
Unlike conventional qZS networks, as it is clear from Fig. 3, in AqZS-NPC, the charging time of inductors are different. Same as capacitors voltage, by applying the ampsecond balance property of capacitors C 1 and C 2 , the average current across inductors in steady-state is calculated as follows. (17) where R L is the ac side circuit's simplified equivalent, DC load [20] and I PN is corresponding the average DC-link current. By these considerations, the average inductors' current which is equal to the average current of the input source, can be derived as follows.
Further, concerning (1-3), (9) and (18), the capacitors' voltage ripple and therefore, the corresponding capacities can be extractad as follows Substituting (13)- (14) into (19), the capacitance values of C 1 and C 2 , are calculated as voltage difference is fed into the new controller, and d is output, but only within certain bounds so as not to conflict with dst. As a result, the corrected value of d 2 is obtained. For ac-side control, the proposed topology is compatible with conventional voltage regulation techniques. Commonly, d-q transformation used to convert fundamental frequency components to dc components. This approach enables the use of fewer and simpler PI compensators. One more possibility is to use a stationary frame and design the appropriate controller for it. Among the advantages of this technique is its applicability in single-phase systems. This paper employs the traditional controller in a stationary frame to achieve the desired outcome of regulating the output voltage. In this context, [24] provides more detail about the controller parameter designing process.

VI. PERFORMANCE COMPARISON
This section compares the proposed topology with traditional non-isolated high boost ZSIs, qZSIs, and qSBs to validate its benefits Table 2, illustrates the number of elements in the impedance network of the proposed topology and other three-level ZSI, qZSI and qSB topologies. As is obvious, compared to the others, the suggested topology has a less or equal number of capacitors. However, although the same is true for inductors, it has one more inductor compared to [22]. Although [22] has a lower passive component, it has one more switch, making it costly and more complex for control. Furthermore, the proposed inverters, employs far fewer diodes than [17] and along with [19] and [22], use a single DC source, while the other inverters use two. Amongst all, only the proposed topology offers the benefit of the common ground.

B. COMPARISON OF THE BOOST ABILITY
Comparing the relationship between the boost factors shows the proposed topology has higher voltage gain through the whole shoot-through duty cycle d st range than the others except [16] and [17], which have better boost ability, but they suffer from discontinuity of input current. The boost ability and gain comparison of the proposed topologies with other TL boost inverters are illustrated in Fig. 6(a) and 6(b) respectively.

C. COMPARISON OF THE DC-LINK UTILIZATION
Compared to the traditional impedance source three-level inverters, AqZS-NPC provided better DC-link utilization. To compare fairly, the inverter topologies' input and output voltages, as well as their power ratings, must be identical.
As shown in Table 2, when the same shoot-through duty cycle is used, the voltage gain of the suggested inverter is higher than the values proposed in [19]. Suppose [19] has a ST duty cycle of d st1 . In that case, for a proper boost factor, the suggested inverter's ST duty cycle should be (4d st1 -1)/2, which is less than d st1 and results in a higher utilization factor for the proposed topology. This feature can be formulated as below.

D. COMPARISON OF THE CAPACITOR AND INDUCTOR VALUES
In order to compare the value of capacitors and inductors, in addition to the proper input voltage, proper DC-link utilization condition should be taken into account. To provide the exact DC-link utilization, if the ST time duration of [12] is d st1 , the equivalent value in the suggested topology would be 3/2 -1/2d st1 , which is lower than d st1 . This causes the proposed inverter's peak-to-peak inductor current to be less than that of [12], implying that the inductor size of the proposed inverter can be reduced. Repeating the same process for [16] with the assumption of d0=0.6, the equivalent value in the suggested topology would be 4/3 -1/3d st1 , which proves that the inductances of the proposed topology is higher than that in [16]. Although the current ripple in [16] is less than that of proposed, Fig. 6(e) shows the inductor current is much higher, making it much more costly. Fig. 6(f) compares the inductor current ripple of all different topologies. As indicated, the current ripple in Aqzs is less than all of them except [16] and portions of [19], but [16] has higher current rate and [19] uses two more inductor which makes them more expensive than the proposed. Continuing this procedure to compare the capacitor values reveals that compared to [12], the proposed topology has smaller capacitors. Moreover, although in [19] the values of capacitors C 1 and C 4 are nearly half the value of Aqzs capacitors, C 2 and C 3 have the same value as the proposed capacitors. Given that [19] uses two more capacitors than Aqzs, a general comparison reveals that the introduced topology uses lower capacitor values overall.

E. COMPARISON OF THE CURRENT AND VOLTAGE STRESS
In general, the capacitors' voltage stress of the proposed topology are not equal to each other but for d1=1/2, both of them have the same voltage. Fig. 6(c) compares the capacitor voltage stress versus gain for the proposed Aqzs-NPC and the other topologies. As Fig. 6(c) shows, the Aqzs-NPC is superior in capacitor voltage stress compared to [16], [17], and [19], but it has lower voltage stress than [4], [12], [22], and [23] which makes the proposed reasonable. Similar to the capacitors, Fig. 6(d) shows the stress voltage comparison results for diodes. Evidently, for the proposed Aqzs-NPC, although diodes d 1 and d 2 have the same stress voltage, the stress voltage of diode d 3 is different. For the same condition, the voltage stress of d 1 and d 2 is higher than [16] and [17] while they are lower than the others. This is even though diode d 3 has a much higher voltage and its voltage is only lower than [23]. Fig. 6(e) compares the current stress of inductors. As indicated, all topologies have the same current stress except for [17] and [16], which have lower and higher current stress respectively. This means although the proposed Aqzs-NPC uses lower values of capacitors and inductors, it still has an acceptable voltage and current stress compared to the other alternating topologies. Fig. 6(g) and 6(h) compares the voltage and current stress of extra switch respectively. As shown, despite the fact that it has a higher voltage stress than [16] and [17], but it has only one extra switch and its current is much lower than them, which makes the total loss of the switches not significantly different.

F. COMPARISON OF THE EFFICIENCY
For efficiency comparison, it assumed that the values of components and variables are identical across all topologies. Additionally, the type and model of diodes and IGBT switches (if utilized) regarded as identical. Each topology's efficiency calculated in relation to the overall voltage gain. As depicted in Fig. 7(a), for the special case of d1=0.5, the suggested Aqzs-NPC is more efficient than the topologies provided in [16], [17], and [19], but it is comparable to [4], [12], and [23] with a minor difference. The topology given in [22] is the most efficient, but includes more diodes and active parts. As previously stated, the presented topology is applicable to numerous applications, including asymmetric NPCs. In such cases, the capacitor voltages do not have to be identical, and d 1 can have a variety of values. Fig. 7(b) shows the comparison of all topologies efficiency for d 1 = 0.3. As illustrated, the proposed topology is the most efficient in this case, especially for larger gains.

VII. SIMULATION AND EXPERIMENTAL RESULTS
In verify the presented theoretical analysis, the performance of the proposed topology is demonstrated with simulation and experimental results. The simulations are done with MATLAB Simulink, and the experimental validation is carried out by building a laboratory prototype. We assume that the conduct resistance of switches is 45 m . S 1j and S 4j (j = a, b, or c) have a 2 V saturation voltage, whereas the drop voltage of diodes D 1 , D 2 , and D 3 is 1.5V. A variable DC supply of 50 ∼ 150 V is also included, and the Aqzs-TLI's switching frequency is set to 20 kHz. Table 3 illustrates the circuit parameters used for simulation.

A. SIMULATION RESULTS
The results of current and voltage waveforms shown in Fig. 8, where a resistance of 15 per phase used at the inverter's output. Moreover, the input voltage is set to 90 volts, and the output peak AC voltage of each phase (Vm) across the load considered 155 Volts (110 Volts r.m.s.).
According to equation (14), the required shoot-through duty ratio (d st ) and modulation index (M) for the above specification can be set to 0.32 and 0.62, respectively,  resulting in a peak DC-link voltage of 500 Volts. As shown in Fig. 8(a), the voltage across capacitors is well balanced. BothV C1 and V C2 are observed to be the same as the theoretical value (i.e., 250 Volts) with a negligible ripple. The currents of both inductors are approximately identical. The average currents of inductors for I L1 and I L2 are 15.7 and 15.5 A, respectively, which is close to the value obtained from the theoretical. The peak midpoint voltage is half of the peak  To verify the performance of the proposed topologies in the dynamic states, the input voltage, and the load increased by step. Fig. 9 shows the operation of the inverter in this mode. As shown in Fig. 9(a), input voltage increases at 0.2 and 0.4 seconds from 60 V to 100 V and then 140 V, respectively. In addition, the load increases from 1000 w to 1400 w at 0.3 seconds and decreases to 1000 again at 0.5. Fig. 9 shows that the inverter is stable despite changes in input voltage and output load, and the output waveform agrees with the theoretical results.

B. EXPERIMENTAL RESULTS
To validate the simulation results of the proposed topology, a laboratory prototype is developed and evaluated by connecting a resistive load. Fig. 10 depicts a photo of the hardware setup, including the inverter circuit, DSP controller, Measuring unit, driver board, output filter, and a controllable 1.4-kVA load. For more compatibility and coordination, three   PWM control signals are generated using a DSP TMS320F28335 controller, which has a triangle frequency of 20kHz. The drive circuit uses the Texas Instrument's ISO5852 smart and high-performance gate driver IC with a  Fig. 11(e), the voltage of C 1 is half of theV PN , but there are a small differences with the simulation, which are related to parasitic found in the experiment. The current and voltage pattern of all components agree with simulation results. However, spikes are seen in the voltage and currents of AqZS components, which should be lowered by designing an appropriate snubber circuit. Fig. 12 depicts the experimental waveform of the output voltages before and after the LC filter, the input and output current, and the voltages of two capacitors during the transient state when the load power increases from 1000 w to 1400 w while the input voltage and dc-link voltage are set to 140 V and 500 V, respectively. In accordance with the applied control policy, the voltage of the capacitors remains constant. Since the input voltage and dc-link have not changed, there is no need for a significant change in dst; however, the load current increases as a result of the increasing load. Fig. 13 depicts the dynamic response of the system when the input voltage stepped from 100 V to 140 V and the load remains constant at 1000 w. As expected, since the dc-link voltage is set to 500 V, the values of d st and d 2 decreased and increased, respectively, when the input voltage stepped up.  The voltage of the capacitors stays the same, so the voltage of the neutral point remains constant and the experimental results are found to be consistent with the computational results. Fig. 14 shows the measured efficiency of AqZS-NPC in terms of output power. Due to the lack of optimal components employed in the construction of the prototype, the measured efficiency is slightly different from the theoretical results.

VIII. CONCLUSION
This paper introduced a new active quasi Z-source three-level NPC inverter with a lower component count. The suggested inverter presented in two alternative configurations, all of which offer the same results. Besides having outstanding features such as power conversion in single-stage, ST immunity, continuous input current, and improved modulation index, the main contributions of proposed inverters are lower component count, enhanced voltage gain, and require smaller inductances. The simulation and experimental prototype developed to confirm the feasibility and reliability of the proposed topology. The hardware results corroborated the simulation and analytical results. Engineer in the field of oil and gas with Advanced Technology. Since 2009, he has been participated in different power system and power electronic projects in the field of renewable energy, metro system, and railways electrification. Since 2007, he has also been a Consultant of many famous industry companies for various industrial concerns. His research interests include power converters, renewable energy systems, control techniques, electric vehicles, and SIC modules. He received several awards and honors, including the Outstanding Students Award from Ferdowsi University.
HASAN RASTEGAR was born in Gorgan, in 1962. He received the B.Sc., M.Sc., and Ph.D. degrees in electrical engineering from the Amirkabir University of Technology, Tehran, Iran, in 1987, 1989, and 1998, respectively. He is currently a Professor with the Amirkabir University of Technology. He has published many papers in journals and conferences. His research interests include power system control, application of computational intelligence in power systems, simulation and analysis of power systems, and renewable energy. VOLUME 11, 2023