Design and Implementation of a Single Switch High Gain Boost Topology: Structure, Ripple Control and ZCS

The need for high gain DC-DC converters has lately increased in tandem with the utilization of renewable energy supplies. Particularly appealing are high gain converters that do not require the inclusion of extra power switches and/or other passive elements to the system. As a result, this study proposes a non-isolated single switch converter with ultra-high voltage gain (UHG) that is appropriate for most renewable energy conversion systems, like solar installations. With only a single MOSFET working within a suitable duty cycle region, the proposed converter provides significant voltage gain and around 95% efficiency. Moreover, the MOSFET in this UHG converter is turned on in zero current switching (ZCS) mode, resolving the diode recovery issue. The recommended UHG converter’s working modes, steady-state parametric study, circuit variables like voltage stress on switching devices, and converter gain are all thoroughly explained. Comparisons have been done with comparable topologies presented in the literature, and lastly, experimental results depending on 200W (20V input, 320V output voltage) are given to validate the operation of the proposed UHG design.


I. INTRODUCTION
In past years, there has been a significant growth in energy demand and usage. This expansion is projected to continue over the next many years (at least). Conventional fossil-fueled sources of energy are linked to two fundamental issues: finite resources and greenhouse gas emissions. As a result of these worries, companies have invested in environmentally acceptable energy resources such as photovoltaic (PV) devices [1], [2], hydrogen-based fuel cells [3], [4], and wind energy technologies.
In the majority of these novel energy methods, the produced power is either direct current (DC) or there is an intermediary DC connection in the energy conversion system [5].
The associate editor coordinating the review of this manuscript and approving it for publication was Kan Liu . Solar panels, as a standard strategy for PV systems, can be arranged in parallel or in series with one another and operate as the input for DC-DC topologies, the primary tasks of those are to control and step up the DC voltage on the DC-link for DC-AC conversion. In order to control the current rating of the switching devices and utilize the suitable modulation coefficients, the DC-link voltage of a DC-AC inverter must not be less than a particular specified value. In past research, several designs were created to increase the voltage level of PV panels to an acceptable amount for the DC-link voltage.
Combining coupled inductor (CI) and passive and active clamped approaches, high boosting capability can be accomplished [6], [18]. Despite these, the cost and dimensions of this converter, due to its two output DC-link capacitors and CI's enormous core size, do not appear to be appropriate for the entire power rating.
Further approaches for achieving high voltage gain in switching mode converters include the use of a switched capacitor or a switched inductor [7], [15]. However, due to the intrinsic characteristic of these designs [7], [14], a high duty cycle value is required for active switch(s) to accomplish high voltage gain in several high gain step-up converters, that might raise switching losses. The active switchedinductor with a passive switched-capacitor based converter described in [24] increased voltage gain via a cascaded passive switched-capacitor network. But, the inductance in the high-side LC filter, that is utilized to minimize the discharge current spikes of capacitors, will result in a bulkier circuit based on the calculated inductance. The voltage gain of an active switched inductor converter is improved in [25] by using an extensive active-passive inductor unit. By expanding the amount of active-passive inductance cells, voltage stress on switches is diminished and critical inductance is lowered, but the semiconductor device drive circuit becomes more complicated due to the extra switches. Reference [8] introduces a unique resonant design with a double voltage arrangement and two sets of secondary windings to produce soft switching operation. The disadvantage of this converter is that it has a high number of active switching devices as compared to single-switch designs.
Another typical approach for improving voltage gain in DC-DC converters is to change the turn-ratio of specific magnetic elements, such as a transformer or CI [9], [12], [13], [14], [15]. In particular applications when isolation is not required, the CI is used by varying the turns ratio, that can yield significant voltage gain. Compared with an isolation transformer, the coupled inductor has a simple and efficient structure, but its use is restricted to applications that do not require electrical isolation [28], [29]. Considering its adaptability, the high voltage gain method has significant drawbacks, the majority of which are related to CI leakage [10], [11]. Using multiplier cells in a boost converter is another way to enhance voltage gain [16], [18], [20], [24]. The turns ratio of the CI is the most critical factor in increasing voltage gain and reducing voltage stress over the switches. The DC-DC design in [15] operates well in terms of voltage gain and voltage stress. But at the other hand, the current ripple is significantly larger on the input-voltage side. As a result, the power source's lifetime may be diminished, as well as its overall efficiency.
In [17], the researchers suggested a novel DC-DC converter design depending on 3 CI with high voltage gain. While the use of inexpensive elements with CI is a benefit of this design, the voltage gain is too low to be employed for a DC-DC-AC solar systems with a specific solar panel. Another three-winding CI-based converter has been suggested in [13], but it suffers from reverse-recovery issues due to their diodes. Reference [22] proposes a new configuration for a step-up DC-DC converter with a high voltage transfer gain and an appropriate duty cycle. However, due to the use of resistance in the power input path, the ripple of input current is higher than that of other step-up topologies, such as those described in [19], [20], and [21], and the efficiency can be reduced. In addition, the diode voltage stress in the multiplier cell of this converter is equal to the output diode voltage, which can increase the overall price of the converter.
A non-isolated ultra-high gain (UHG) DC-DC configuration with three winding CI and a single power MOSFET switch is presented in this work. The main features of the proposed converter are: • Very low Input current ripple. • Low voltage Stress on semiconductors. • High and appropriate voltage gain of the converter. • Soft switching operation for main switch and diodes. • Appropriate total efficiency of converter. Fig. 1 shows an example application of proposed converter in a grid integration of energy resource. It should be noted that in grounded PV systems, the step-up converter should provide a shared ground between the PV ground and the grid neutral line to prevent common mode current. That's why there is a common input to output ground in the proposed topology.
The proposed converter can be used in PV applications under normal or partial shading conditions as well as other applications such as Fuel cells, DC microgrid and HID lamp ballast. For example, when partial shading occurs on a solar system, the maximum power point of that system may be formed at low voltage levels. Therefore, it is necessary to use a high gain step-up converter.
This work extends the proposed UHG converter topology which was previously presented at a conference [24], where more detail analysis has been done on device operation, evaluation of the current stress on semiconductor devices have been done, comparative study is extended, the component design procedure of the proposed converter has been explained and followed by numerical representation in the experimental setup development. Moreover, more detail efficiency analysis and losses evaluation have been performed to compare the proposed converter efficiency with most recent similar topologies available in the literature.
It is important to note that adding voltage gain using a large number of inductors will not happen easily, and significant challenges such as voltage stress on the switch(es) or diodes, Soft/Hard switching operation, losses of windings should be considered.
The remaining of this paper is organized as follows: Section II discusses circuit designing and operational analysis in the context of continuous conduction mode (CCM). Section III obtains some critical topology characteristics (including voltage gain and voltage stress over the switching devices). There is the component design and efficiency analysis in Section IV. Section V includes a comparison between comparable high gain designs available in the literature. Lastly, Section VI discusses the paper's overall accomplishments depending on the experimental setup. While the closed-loop control can be achieved for different purposes (e.g. output voltage regulation using a conventional PI), this research concentrates on the design of the high gain boost converter along with the soft switching circuit assignment as well as low-ripple input current regulation.

II. SUGGESTED TOPOLOGY AND OPERATION PRINCIPLES
The suggested design comprises a voltage multiplier cell (VMC) and a CI to improve converter boosting capabilities. Figure 2 depicts the suggested UHG DC-DC converter associated power circuit. A passive clamping circuit consists of capacitor C1 and diode D1 is employed to relieve the voltage spike caused by the leakage inductor on the main MOSFET and recycle the leakage inductance energy. To improve the converter voltage gain, at the tertiary side of the CI, capacitors C3 and C4, and diodes D3 and D4 work as a VMC. The LC low-pass filter at the input makes the input current continuous with low ripple, which makes the proposed converter suitable for use in renewable sources such as solar cells.
The condition of switching devices in one entire switching period for the proposed UHG DC-DC converter is depicted in Fig. 3, wherein a switching period is split into six subintervals (mode 1 -mode 6). Figure 4 depicts the primary waveforms of currents and voltages during a single switching period. The following concepts are taken into account when performing the steady-state analysis: • The switch and other semiconductors are ideal.
• The grayed-out components are disabled.
• D denotes duty cycle of the switch and D' is equal to 1-D.
The following are the suggested design operating principles: Mode 1: At the commencement of the first state, the MOSFET starts to conduct, diodes D 1 − D 4 are blocked, and only D O is conducting. As the leakage inductance current, L lk , slowly rises during this small time, the currents on the different sides of the CI (L N 2 and L N 3 ) reduce gradually. According to Fig. 3(a), the existence of Lin and a leaky inductor causes MOSFET current to progressively rise and turning on in a ZCS condition. Whenever the leakage current reaches the magnetizing current, diode D O switches off and diode D 2 turns on.
Mode 2: In Fig. 3(b), the MOSFET remains operating in the second mode, and diodes D 3 , D 4 , and D O are blocked, whereas diode D 2 is turned on with a ZCS condition. The input, leakage, and magnetizing inductors are charged by the DC input voltage source, increasing their current (I Lin , I Lm , and I Lk ). The diode D 2 discharges the capacitor C 1 and charges the capacitor C 2 .
These formulae can be determined by applying Kirchhoff's Voltage Law (KVL) to the design in this mode: Lin are voltage of magnetizing, leakage and input inductances while MOSFET is on respectively. V Cr .V C2 .V C1 are voltage of capacitors C r , C 2 and C 1 respectively, while MOSFET is turned on. This interval ends when the diodes D 3 and D 4 turn on and amplitude of I LN3 increases.
Mode 3: In this state, the MOSFET stays switched on, and diodes D 2 , D 3 and D 4 conduct while diodes D 1 and D O are turned off. Through the diode D 2 , the capacitor C 1 is discharged, while the capacitors C 3 , C 4 , and C 2 are charged. Furthermore, because of the inverted voltage on windings N 3 and N 2 , the currents on windings N 2 and N 3 (I N 2 and I N 3 ) are gradually decreasing. Moreover, the voltages of capacitors C 3 and C 4 are determined in this situation using (6): where V D N3 is the voltage of tertiary windings whenever the MOSFET is on.
Mode 4: This short interval transition starts whenever currents of windings N 2 and N 3 is near zero and all diodes are blocked. As it can be found from Fig. 4, while the switch is completely off, this time interval ends.
Mode 5: In this situation, the power switch is switched off, and the input voltage charges the windings of N2 and N3. The energy from the leaking inductor is recycled to the capacitor C1, which is supplied through the diode D1. For where V D Lm .V D L lk .V D Lin are voltage of magnetizing, leakage and input inductances while the MOSFET is off respectively.

Mode 6:
The power switch is continuously blocked in this situation, and this state starts whenever the voltage of C 1 approaches its ultimate amount and D 1 goes off. As in the preceding state, capacitors C 2 , C 3 and C 4 are discharged through the output diode in this mode (D O ). Whenever the MOSFET is switched on, Mode 6 comes to an end, and the next cycle begins.

III. STEADY-STATE ANALYSIS OF THE SUGGESTED DESIGN A. VOLTAGE GAIN (M CCM ) CALCULATION
By utilizing the volt-second equilibrium axiom for both input inductor and magnetizing inductance, using (3) and (7), V c1 can be related to input voltage by: According to (12) and by utilizing the volt-second equilibrium axiom for magnetizing inductance, using (1) and (8), V Cr is obtained by: By substituting (12) and (13) into (5) the V C2 is obtained: By substituting (12) and (13) into (8) the V D Lm relation to input voltage can be obtained by: By substituting (6), (9), (10), (12), (13), (14), and (15) into (11) the nominal M CCM of proposed UHG topology is obtained: If the leakage inductance of the CI is not considered, the coupling factor k is 1, and the ideal M CCM of the proposed topology is as follows:  Figure 5(a) shows the voltage gain of the converter in the different secondary and tertiary turns ratio when duty cycle is 0.5. As it is clear in this picture, in addition to the high turns ratio, in the lower turns ratio, using the suggested converter, a suitable voltage gain can be obtained. The suggested topology theoretical voltage gain in CCM, M CCM , versus MOSFET duty cycle, D, for different CI, n 2 and n 3 turn ratios is illustrated in Fig. 5. (b). It can be shown that the CI turns ratios, N 2 and N 3 , can be determined and changed to provide very high voltage gain without ever using and operating at an extremely high duty cycle.
Due to the significant increase in power switch conduction losses and the need for a larger heatsink at higher duty cycles, the appropriate duty cycle value of the MOSFET for this topology is less than 0.75, below the knee point of the curves shown in Fig. 5(b)

B. EVALUATION OF VOLTAGE STRESS ON SEMICONDUCTOR DEVICES
The voltage stress of switch and other semiconductors based on the topology operation are calculated as follows: where, V s is voltage stress on MOSFET and V D1 , V D2 , V D3 and V DO are voltage stress of Diodes D 1 , D 2 , D 3 and D O respectively.

C. EVALUATION OF CURRENT STRESS ON SEMICONDUCTOR DEVICES
By using ampere-second balance law on all capacitors, C 1 , C 1 -C 4 and C O , the average currents of all diodes are equal to the output current, I O . Following the same procedure presented in [22], the peak current of the switch and diodes are calculated as follows: Voltage and current stresses are important information for semiconductor devices selection. Figures 6(a-c) show the normalized voltage stress on the diodes D 2 , D 3 and D O respectively when duty cycle is 0.5. Furthermore, the normalized current stress through the Diode D 1 is depicted in Fig. 6(d). By using these figures, the optimal values of turns ratio can be selected.

D. VOLTAGE AND CURRENT STRESS OF PASSIVE COMPONENTS
The voltage stress of passive components can be obtained using equations (6-10), (12)(13)(14), (17) as follows: Furthermore, the current stress of passive components can be obtained using operation modes and by assuming efficiency around to %100 for nominal output power. Besides that, the RMS current of C r is very low.

IV. COMPONENT DESIGN A. INPUT FILTER DESIGN (LIN)
By assuming the acceptable ripple on input inductance ( I in ), and knowing the switching frequency of the active switch (f s ), using (33), the size of input inductor can be obtained from the following equation:

B. CAPACITORS DESIGN
The following equation is used to calculate the size of capacitors except resonance capacitor.
By assuming acceptable current ripple on coupled inductor magnetizing inductance ( I Lm ), the amount of the magnetic inductance can be obtained from the following equation:  The average current of magnetic inductance (L m ) is determined as follow:

1) DESIGN OF RESONANCE COMPONENTS
To calculate the amount of C r (resonance capacitor) and coupled inductor leakage inductance (L lk ), according to [22], these components are designed to operate in boundaryresonance or blow-resonance mode to reduce output diode switching losses and improve its reverse recovery problems. Also the amount of L lk depends on how coupled inductor winding is wrapped and thus the following equation can be used for design purpose:

V. COMPARATIVE STUDY WITH SIMILAR TOPOLOGIES
This section provides an extensive comparison between the suggested converter with available similar topologies in the literature. It is meant to identify the merits and demerits of the proposed topology, comparing with other available alternatives and help the engineers to select proper topology among many available varieties. Table 1 shows the essential properties of the offered converter and comparable CI-based converters with an active switch that have recently been discussed in [12], [13], [14], [15], [16], [17], [18], [19], [20], and [21]. It includes voltage gain, normalized voltage stress (NVS) of the switch and diode, grounding approach, and component count. As shown in Table 1, the proposed topology achieves a considerably greater voltage gain and has less voltage stress on the power MOSFET than previous converters. Also, the smaller number of switches in the proposed converter than the converters provided in [14], [15], [19], and [20] makes the suggested converter easier to control. As a corollary, with appropriate design, the suggested topology can be able to use switch part with lower voltage ratings to obtain better efficiency. Another point that can be obtained from Table 1 is the fluctuation of the input current in the proposed converter versus the compared converters. Unlike the converters described in [13], [15], [17], [19], [20], and [21], the suggested converter has a small input current ripple for wide load conditions. Comparison of voltage gain from multiple high gain topology is shown in Fig. 8. In order to make a fair comparison between these converters, the number of secondary turns (N 2 ) for two windings CI based converters was considered equal to 5 (equals the sum of the secondary and tertiary turn ratios in triple-winding converters). It can be found that with n 2 = 2.5 and n 3 = 2.5, the suggested topology has a higher voltage conversion than the converters provided in [12], [13], [14], [15], [16], [17], [18], [19], [20], and [21] for all duty cycle values.
As shown in Fig. 9(a), the NVS of active MOSFET in the recommended topology is less than that of the topologies described in [12], [13], [14], [15], [16], [17], [18], [19], [20], and [21] for all duty cycle numbers. This feature causes the power MOSFET to be selected at a lower cost, which affects the overall cost of the converter.
Furthermore, Fig. 9(b) depicts the NVS of the output diode of the proposed topology and high step-up converters described in [12], [13], [14], [15], [16], [17], [18], [19], [20], and [21]. As it can be found from this Fig. 9(b), the NVS  on output diode for suggested topology stays lower than output voltage for whole range of duty cycle. Furthermore, converters with lower voltage stress on their output diode  than the suggested UHG topology often have weaker voltage boosting ability.
According to the comparative results, the suggested design has a much larger voltage gain than previous high step-up converters owing to the integration of three-winding CI, voltage lift capacitor (C 2 ), and voltage multiplier unit. Furthermore, using a three-winding CI in the proposed scheme allows for easier voltage gain control and optimization of MOSFET and other semiconductor active component construction.

VI. EXPERIMENTAL RESULTS
To evaluate the effectiveness and confirm the theoretical study of the suggested UHG converter, the outcomes of a 200 W built power circuit of the suggested converter are reported.
The peak to peak ripple of the output capacitor (and other capacitors in the converter circuit) is suggested to be kept under 5% [27]. In our work we have tried to design the converter by compromising the performance and cost factors. By substituting voltage ripple of Table 2 into (37) and assumed capacitors average current equal to I_O, the minimum size of capacitors are listed in the Table 2. (The ESR of the capacitors are ignored due to their small sizes): The peak to peak ripple lower than 50% of the maximum inductor current gives a good compromise between the size of the inductor, that's proportional to weight and cost, and the RMS currents [27]. Similar to the calculation of capacitors, the inductors' size are obtained by assuming the acceptable current ripples as they are reported in Table 3: The experimental model of the specified converter is seen in Fig. 10, and the characteristics for every element are listed in Table 4.
The outcomes of the topology working in CCM are shown in Fig. 11. Blue lines show voltage waveform and red lines represent current waveform in all of the figures. Figure 11(a) depicts the voltage and current of diode D 1 . This diode, as shown in the image, has a ZCS circumstance,  and its voltage waveform verifies the study provided in (18). As it can be found from Figure 11(a) after the current of diode D 1 reaches a maximum, its current decreases slowly. So soft switching occurs when the current reaches zero (According to Mode 5 and Mode 6 in section II).
The voltage and current waveforms of diode D 2 are depicted in Fig.11(b). Because the current of this diode varies with a tiny slope (Not suddenly with a steep slope) when it is turned on and off, it has a ZCS characteristic both when it is turned on and when it is turned off.
The waveforms of diode D 3 are shown in Fig.11(c). This diode, like diode D 2 , has a ZCS behavior in both turning on and off. This diode's voltage waveform confirms the theoretical computations given in (20). As can be found from this figure After the voltage applied to the diode is zero, the current starts to increase with a low slope. Therefore, the overlap between voltage and current will be very low when the state of diode is changed (According to Mode 3 in section II). Fig.11(d) is related to the output diode D o . As it can be found, this diode is turned off in ZCS situation which will reduce the reverse recovery losses significantly. It can decrease the total cost of the system since its voltage stress is smaller than the output voltage.
The voltage and current of input inductor L in are shown in Fig. 11(e). The continuation of the input current is a crucial aspect in several uses, particularly the utilization of solar panels. The average input current in Fig. 11(e) is 10 A, with a ripple of 150 mA. The voltages and currents in the CI primary and secondary windings are shown in Figs. 11(f) and 11(g), accordingly. The maximum voltage and current of L N 1 are 35V,12A respectively. The maximum voltage and current of L N 2 are 100 V and 3A respectively.
The drain-to-source voltage and drain current of the MOSFET are shown in Fig.11(h). The zoomed-in picture shows that this switch has a smooth switching action and that the switching losses are so low that they can be disregarded (According to explanations of Mode 1 in section II). If the rated current of the desired switch is less than that of the converter, or in order to increase the power of the proposed converter, several MOSFETs can be paralleled and increase the power of the converter.
The nominal and experimental prototype output voltages are shown in Fig. 12 to examine the correctness of the derived ideal voltage gain and compare it to actual voltage gain. Since one of the main advantages of this converter is to achieve high voltage gain in low duty cycle values, in this figure, the duty cycle is not considered higher than 0.6. Also, when duty cycle is high, the efficiency drops form our desired level and the conductive losses of the switch increase.
The output voltage, input current and their ripples are shown in Figure 13. As it can be found from this figure, the input current and output voltage ripple of suggested converter is very low. Furthermore, these figures meet the requirements set in Tables 2, 3. This converter is suitable for applications that require a low current ripple on the input side such as fuel cell and PV applications.
The waveform of the output voltage of the proposed converter with transient step load change is shown in Figure 14.
As it can be seen, the proposed converter has an appropriate transient response when load is changed from %100 to %50 of its nominal power. In this figure the voltage overshoot is about 30V and the response time is around 250 ms. Due to the presence of only one active switch in the proposed converter, the closed loop state can be implemented with analog or digital circuits.

A. EFFICIENCY ANALYSIS
According to Table 4, in order to accurately evaluate the performance of the converter, it's better to analyze the converter losses by calculating the converter efficiency at 200 Watts. In general, the converter losses can be divided into 4 groups:

1) SWITCH LOSSES
Switch losses are divided into two categories: switching losses and conduction losses. Because of the soft switching of the topology at the moment when the switch is turned on, its switching losses only include losses during turning off. To calculate conduction losses and switching losses the following equation is needed:  Converter response when output load changes from %100 to %50 (blue curve: output voltage, red curve: output current).

2) DIODE LOSSES
In the case of diodes, the ohmic losses of the diodes and the reverse recovery loss of the diodes in this topology are ignorable and the main losses of the diodes are related to the voltage drop of the diodes in its average currents (conduction losses). For this reason, the following equation can be considered:

3) CAPACITOR OHMIC LOSS
In order to calculate the internal resistance loss of capacitors, the following equation can be considered:

4) MAGNETIC LOSSES
According to T131-52 iron powder core datasheet the core loss of input inductor is considered 125 mW/cm 3 and the volume of each inductor is 13.68 cm 3 . The same as input inductors, according to ETD49/25/16 datasheet the core loss of CI is considered 139 mW/cm 3 and the volume of each inductor is 24.3 mW/cm 3 . The ohmic loss is equal and due to the large number of primary wire (they are wrapped in litz wire) the ohmic loss is negligible. Therefore, to calculate the core loss we can consider: P loss(core) = 3.38 + 1.7 = 5.08 W According to the equation of losses in previous sections, the efficiency of topology can be calculated as follows: The total losses shown by (41)-(47) is illusterated as a pie chart in Fig. 15 for the implemented converter, where V in is 18V and the output load is 200 W. This pie plots show that switch losses is low due to its low voltage ripple. Fig. 16 depicts an efficiency comparison between the suggested topology and the converters based on CIs described in  [13], [15], [16], [17], [18], [19], and [20] for different loads levels. The main reason for improving the efficiency is the ability to use the MOSFET with a small R ds due to lower voltage stress on the switch and the ZCS operation of the main switch in the on state. Also, alleviating the reverse diode recovery issue and ZCS operation of diodes in this topology help to improve the overall efficiency of the converter.

VII. CONCLUSION
This work presents an ultra-high voltage gain (UHG) DC-DC structure depending on three windings coupled inductor (CI) and voltage multiplier cell (VMC). The crucial benefits of the proposed configuration are: • ultra-high gain in a significant low turn ratio of CI and suitable zone of duty cycles, recycled energy of inductor. Comparison with similar topologies showed this superiority.
• Efficiency improvements due to soft switching process for main switch and other diodes. Comparison with similar converters showed appropriate converter efficiency.
• Low normalized voltage stress (NVS) on MOSFETs and other electronic components. The investigation of voltage stresses on components and experimental results confirmed this superiority.
• Low input current ripple, which causes less stress on the input source than the high current ripple converters. The experimental results verified this capability.
The principle of operation of the converter and its steadystate assessment under CCM situations have been comprehensively described.
Furthermore, the proposed UHG converter has two intrinsic characteristics that make it suited for use as a solar panel side DC-DC converter in Photovoltaic system. First, the input current is continuous and has a very small ripple. The second characteristic is its common ground, that can avoid common mode leakage current. Input current continuous simplifies the installation of maximum power point tracking (MPPT) controls, and the common ground characteristic can reduce the requirement for complicated leakage current control in PV system applications [25], [26].
Some other practical applications of the suggested converter are as follows: -DC microgrid application.
-Robotics. The closed loop analysis and transient response of the suggested converter in different conditions can be studied in more detail in the future works.