Design of Approximate Bilateral Filters for Image Denoising on FPGAs

This paper presents the hardware design of fast and low-cost denoising filters suitable to be exploited in the enabling technologies for Industry 5.0. A novel approximate computing strategy is introduced to reduce the computational complexity of the image denoising operation and to comply with real-time requirements. Firstly, it is demonstrated that the novel approximate approach can be helpfully exploited in the design of reconfigurable denoising filters able to reach image qualities as close as possible to the precise software counterparts. The reconfigurability leads to hardware architectures run-time adaptable to different levels of noise, whereas the adopted approximation strategy limits hardware resources and energy requirements. Quality tests, performed at various image and kernel sizes, and noise standard deviations, demonstrate that the approximate denoising approach presented here reaches PSNR and SSIM comparable with the precise denoise filtering. In comparison with state-of-the-art FPGA-based competitors, the novel filters reduce the resources requirements by up to 70%, achieve frame rates up to 35 times higher, and dissipate more than 45% lower power. When implemented within the XC7Z7020 FPGA device, a <inline-formula> <tex-math notation="LaTeX">$5\times 5$ </tex-math></inline-formula> filter designed as proposed here denoises <inline-formula> <tex-math notation="LaTeX">$512\times 512$ </tex-math></inline-formula> grayscale images using only 1689 LUTs, 2635 Flip-Flops and 32 DSPs. Moreover, it processes up to 926.8 frames per second, consumes just 63mW @ 244MHz and, with a noise standard deviation equal to 10, it achieves an average PSNR of <inline-formula> <tex-math notation="LaTeX">$\sim 33$ </tex-math></inline-formula>dB with an average SSIM of ~0.86.


I. INTRODUCTION
The next incoming industrial evolution, Industry 5.0, has the main objective of guaranteeing sustainable and efficient manufacturing solutions by leveraging the collaboration between human experts and intelligent machines [1]. As deeply discussed in [1] and [2], in order to achieve this result, proper enabling technologies are required, such as Artificial Intelligence (AI), Edge Computing (EC), Virtual Reality (VR), Internet of Everything (IoE), Collaborative Robots (Cobots), and many others. These technologies can certainly benefit from fast and reliable computer vision and The associate editor coordinating the review of this manuscript and approving it for publication was Christian Pilato . digital image processing techniques [2], which are suitable to favor the human-machine interaction; to increase the manufacturing efficiency; to monitor the manufacturing processes constantly; and finally, to make accurate decisions in realtime.
Unfortunately, as it is well known, image sensors and acquisition electronics circuits make digital images inherently noisy [3] introducing a noise level often not known a priori. In these cases, noise statistic can be estimated from either a single image or multiple acquired images [4], [5], [6]. Therefore, conceiving methods able to remove or at least reduce the noise effects from acquired images and, at the same time, suitable to adapt this capability to different noise levels is crucial for computer vision and image processing techniques in order to obtain the most reliable elaboration results.
Considering that the noise must be removed/reduced without compromising the information captured from the observed scene, total variational regularization (TVR) [7], [8] and bilateral filtering [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19] are among the most popular denoising approaches. The TVR methods have the ability of removing noise with edges preservation, but also with the introduction of artifacts (e.g. blocky, staircasing, etc.). The adaptive models presented in [7] and [8] improve such a behavior by exploiting either eigenanalysis of the structure tensor [7] or a balancing parameter to prioritize noise removal or artifacts elimination [8]. Conversely, bilateral filtering owes the ability of reducing noise while preserving the fundamental information to its significantly complex nonlinear weighted averaging operations performed in both spatial and intensity domains. These operations demand high computational resources, lead to quite low speed performances and cause significant power dissipation. Most of the above-mentioned technologies (e.g. EC and IoE) are being exploited within energy-and resources-constrained environments, in which also achieving high computational speeds is mandatory [1], [2]. Taking these considerations into account, several approximation strategies have been recently proposed [15], [16], [17], [18], [19] to reduce the computational complexity of bilateral filtering. Although these approaches allow achieving interesting trade-offs in terms of image quality and hardware characteristics, most of them [15], [16], [17], [19] are not suitable to adapt themselves at runtime to different noise levels.
This paper presents an innovative approximation strategy for the hardware implementation of fast low-cost denoising filters suitable to be adopted in the enabling technologies for Industry 5.0. The novel approach denoises a digital image by processing each pixel through approximate spatial domain and intensity range kernels, whose coefficients are approximated to unsigned integer values. While the spatial coefficients are approximated depending on the kernel size, the range coefficients are computed by means of a new simple piecewise approximation function, purposely introduced to simplify the nonlinear weighted averaging operations conventionally performed on the pixel intensity. The denoising capability of the proposed approach is analyzed in terms of Peak Signal to Noise Ratio (PSNR) and Structural Similarity (SSIM) [20], [21] referring to image sizes ranging from 256× 256 to 1024×1024, kernel sizes varying from 3×3 to 21×21, and zero-mean Gaussian noise with standard deviations ranging between 5 and 60. The proposed approach clearly exhibits its graceful behavior limiting the relative error of PSNR and SSIM, introduced in comparison with the MATLAB software bilateral filtering, to −4% and −14%, respectively, which are up to 12% and 24% better than [15] and [16], while remaining comparable with [17] and [19].
For purposes of comparison with state-of-the-art competitors [15], [16], [17], [18], [19] also in terms of implementa-tion results, several FPGA-based denoising filters designed as proposed here were characterized in terms of utilized Look-Up-Tables (LUTs), Flip-Flops (FFs), Block of RAMs (BRAMs), and Digital Signal Processors (DSPs), speed performances and power consumption, using both the Xilinx Virtex-5 and Zynq-7000 devices families. At a parity of used technology, image and kernel sizes, the proposed designs exhibit speed performances ×4.36, ×35.9, and ×4.05 times higher than [15], [16], and [17], respectively. Moreover, a power dissipation ×1.85 lower than [19] is achieved at comparable speed performances and resources requirements. As a further advantage, in comparison with [15], [16], and [17], the designs employing the novel approximation strategy save up to ∼70% of utilized LUTs, thus better complying with the requirements of the referred applications.
In comparison with previously published papers, the main contributions of this work are: 1. it presents an innovative approach that reduces the computational complexity of denoising filters by approximating spatial domain and intensity range coefficients to unsigned integers; 2. hardware architectures based on the proposed approach adapt themselves to different noise levels varying at run-time; 3. the novel approximation strategy is extensively characterized in terms of denoising capability and hardware performances, at different operating conditions kernel/image sizes and noise standard deviations: accuracy metrics are evaluated on the entire Miscellaneous USC-SIPI dataset [22] and FPGA-based designs, implemented using the Virtex-5 and the Zynq-7000 devices families, are characterized in terms of resources requirements, speed performances and power consumption.
The rest of the paper is organized as follows. Section II provides a brief background and overviews the state-ofthe art. The novel approximation strategy is introduced in Section III. Hardware implementations are detailed in Section IV, whereas accuracy and comparison results are presented in Section V. Finally, conclusions are drawn in Section VI.

II. BACKGROUND AND RELATED WORKS
Bilateral filtering is an efficient local method widely used to process digital images on the basis of both geometric and intensity distances between neighboring pixels [9]. Due to the usage of spatial domain and intensity range kernels, such filters have the ability of reducing noise from an n×m digital image Im while preserving fundamental information, in a way that is tuned to human perception [9]. With Im(x,y) being the generic pixel at the coordinate (x,y) within the image to be processed, a bilateral filter averages nearby pixels as shown in (1), where: Om(x,y) is the output pixel; is the k×k filter window centered in Im(x,y); (i,j) is the coordinate of the neighboring pixels in ; and, finally, Ws(i,j) and Wr(i,j) are VOLUME 11, 2023 the spatial domain and the intensity range coefficients defined in (2).
The above definitions clearly show the computational complexity of bilateral filtering and motivate the recent attempts of introducing efficient approximation strategies [15], [16], [17], [18], [19] to make fast low-cost hardware implementations approachable. The method proposed in [15] considers that, with the spatial domain kernel Ws being symmetric and separable, the pixels within can be sorted into groups to be processed by the range filter in parallel, thus allowing high speed performances to be achieved. However, such a solution leads to resources requirements and computational delays building up rapidly with the kernel size. As shown in [16], this effect can be mitigated by approximating the range coefficients through the Taylor expansion. Conversely, the technique presented in [17] conjugates an innovative positionoriented grouping logic with a resource sharing strategy that allows processing the sorted groups of pixels in parallel with a limited resources utilization.
A completely different solution is presented in [18] that replaces the conventional range kernel with a model able to adjust the range coefficients accordingly to the noise estimated at the pixels within . In order to reduce both the computational complexity and the resources requirement as much as possible, the noise-aware kernel obtained in this way is approximated to a binary filter. As an alternative, the efficient piecewise approximation function recently proposed in [19] pre-calculates the exponential functions shown in (2) and selects several approximate fitting points as the kernel coefficients.
For all the above-described approximation strategies, efficient hardware designs are available [15], [16], [17], [18], [19]. They avoid the time expensive computations of the exponential functions, by exploiting LUTs that locally store the approximated values of pre-calculated coefficients. Obviously, the way the latter are approximated leads to a different denoising capability.

III. THE PROPOSED APPROXIMATION TECHNIQUE
The novel method here presented approximates both the spatial domain and the intensity range kernels coefficients to unsigned integers. In the following, the 7-bit word-length is referred to. However, higher bit-widths can be easily introduced if a better quality of filtered images is desired.

A. APPROXIMATING THE SPATIAL DOMAIN KERNEL
In order to compute the possible values of the coefficient Ws(i,j) as given in (2a) for several kernel sizes k×k, the parameter σ s is set to satisfy the condition ED (i, j) ≤ 3 × σ s [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19]. Table 1 summarizes the minimum values of σ s satisfying the above condition and those adopted here for kernel sizes ranging between 3 × 3 and 21 × 21. The exact values of the spatial kernel coefficients related to these kernel sizes have been scaled by 64. This scaling factor has been chosen to approximate each coefficient Ws(i,j) to a 7-bit unsigned integer, thus limiting the loss of information introduced by the approximation and significantly reducing the computational complexity. From Figure 1, that illustrates samples of approximate kernels, it can be seen that the spatial coefficients are approximated only by integer values ranging between 0 and 64 and having at most three asserted bits in their binary representation.
Plots depicted in Figure 2 graphically show how well the adopted approximation fits the real exponential scaled  functions at all the referred kernel sizes. To improve the readability of Figure 2, the x-axis range is limited to ED 2 = 50.

B. APPROXIMATING THE INTENSITY RANGE KERNEL
Intensity kernel coefficients Wr(i,j) depend on the intensity difference I(i,j), that, in the case of 8-bit pixels, ranges between 0 and 255, and the parameter σ r, set on the basis of the noise standard deviation σ noise [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19]. Again, the exponential function (2b) is scaled by 64 and the 7-bit unsigned integer representation is adopted. Figure 3 reports the simple new rules adopted to approximate Wr(i,j) to its 7-bit version AWr(i,j). In this case, only values having at most four asserted bits in their binary representation are used.
The behavior of the proposed approximation strategy has been analyzed over a relatively wide σ noise range (i.e. 5-75). Figure 4 collects few samples obtained through this investigation. From such experiments, it has been observed that the chosen rules guarantee both a good accuracy and a limited computational complexity in all the examined cases. Moreover, Figure 4 shows the effects of the proposed approximation in comparison with the exact exponential functions at various values of σ r = 3 × σ noise . It can be seen that the intensity difference leading to a certain approximate range coefficient AWr(i,j) varies with σ r. As an example, when σ r  = 180, AWr(i,j) is set to 64 for I(i,j) ranging between 0 and 45. Conversely, with σ r = 60, the same approximate range coefficient is associated to intensity differences varying from 0 to 15. Figure 5 reports some of the piecewise functions here adopted for different values of σ r. It can be seen that, in contrast to existing approximation strategies [15], [17], [19], which find at design time a predefined number of optimal fitting points of the range kernel coefficients at a fixed σ r, in the proposed approach also the number of exploited fit- ting values changes with σ r. It is worth pointing out that this behavior is functional to realize a hardware architecture able to run-time adapt the filtering operations to different noise levels. In order to explain how this is possible, let's suppose that the optimal fitting points complying with the approximation rules of Figure 3 have been found for the predefined σ rfix. By introducing the scale factor sc σ , such that σ r = σ rfix sc σ , equation (2b) can be rewritten as (3), with sc I (i, j) = sc σ × I (i, j) being the scaled intensity distance.
It is then clear that the approximate AWr(i,j) related to σ r can be computed using the optimal fitting points precomputed for σ rfix by simply scaling the intensity difference I (i, j) by sc σ . As an example, let's assume that σ rfix = 60 and σ r = 180, that is sc σ = 1/3. In this case, an intensity value I (i, j) = 48 would be scaled to sc I (i, j) = 16 that, through the piecewise function of Figure 5(b), leads to AWr (i, j) = 60, which is the same approximate range kernel coefficient provided in Figure 5(d) for I (i, j) = 48. Analogously, with σ rfix = 60, σ r = 15 and sc σ = 4, I (i, j) = 48 would be scaled to sc I (i, j) = 192 that, as ruled in Figure 5(b), leads to AWr (i, j) = 0, which is the same approximate coefficient provided in Figure 5(a) for I (i, j) = 48. It is worth noting that, in order to guarantee a fair use of the scaled intensity distance, σ rfix must be chosen so that the corresponding piecewise function employs all the fitting points between 0 and 64. As an example, this means that choosing σ rfix = 180, as shown in Figure 5(d), would lead to an inefficient solution. Figure 6 depicts the top-level schematic of the basic hardware architecture purposely designed to exploit the above described approximation strategy at a predefined σ r. It uses three main modules: i) the BUFFER receives the n×m input image in the raster scan order and exploits k−1 FIFOs, each m-k deep, and k×k registers to properly arrange the filter window centered at the pixel Im(x,y); ii) the COMPUTATION module processes through k×k−1 Processing Elements (PEs) that implement the approximation rules described in the previous Section to furnish the range kernel AWr; iii) the MACs& Divider block receives , AWr, the pre-computed approximate spatial domain kernel AWs and performs the Multiply Accumulations (MACs) and division operations required to implement (1). As depicted in the inset of Figure 6, the generic PE computes the absolute difference between the neighboring pixel Im(i,j) in and its central pixel Im(x,y). The I (i, j) obtained in this way is then used as the address of the LUT-based memory that stores the possible 7-bit pre-computed values of AWr(i,j). The k×k−1 approximate range kernel coefficients, computed in parallel by as many PEs, are then inputted to the MACs& Divider module. Figure 7 shows that the latter uses k×k−1 Multiplication Blocks (MBs), each computing the products Pr(i,j) and coeff(i,j). It is worth pointing out that, with k = 5, AWs(i,j) is a power of two constant precomputed at design time. Therefore, the coeff(i,j) can be simply computed by left shifts. Furthermore, it must be noted that, since both AWs(x,y) and AWr(x,y) are always equal to 64, coeff(x,y) is constant and Pr(x,y) is computed by simply left shifting Im(x,y) by 12 bit positions. The k×k products Pr and coeff are then accumulated through appropriate Adder Trees that furnish the numerator N and denominator D of (1). Finally, by implementing the non-restoring division algorithm [23], the Divider computes the filtered pixel Om(x,y).

IV. THE NOVEL HARDWARE ARCHITECTURE
In order to introduce the ability of adapting the denoising filter operations to run-time varying values of σ r, the reconfigurable structure illustrated in Figure 8 has been purposely designed for the PEs utilized to approximate the intensity range kernel. First of all, the scale factor sc σ , such that σ r = σ rfix sc σ , was introduced. Just as an example, it is assumed that it can vary from 0.25 to 3.75 (i.e. σ r can range between 4 × σ rfix and 4 15 × σ rfix). To keep the hardware complexity limited, as a proof of concept, sc σ has been quantized to 4-bit fixed-point values, which, as summarized in Figure 9, can be processed as 4-bit unsigned integers. Consequently, equation (3) has been rewritten as (4) to introduce the integer scale factor sc σ i .
It is easy to understand that, with Im(i,j) and Im(x,y) being 8-bit pixels, the absolute difference Im(x,y) 4 − Im(i,j) 4 is a 6-bit unsigned number and, consequently, the product Prod = sc σ i × Im(x,y) 4 − Im(i,j) 4 is a 10-bit unsigned number. However, since it represents the intensity difference I (i, j) related to a certain σ r, values greater than 255 are saturated. As illustrated in Figure 8, this condition is simply managed by OR-ing the two most significant bits of Prod. The subsequent multiplexer then selects either the saturation value 255 or the 8-bit sub-word Prod(7:0) as the address of the LUT-based memory that stores the possible 7-bit pre-computed values of AWr(i,j) related to the predefined σ rfix.

A. QUALITY RESULTS
Quality tests on the proposed architecture have been performed using the Miscellaneous USC-SIPI dataset [22] that collects benchmark images with sizes ranging from 256 × 256 to 1024 × 1024. As in related works, the original images were corrupted with additive zero-mean Gaussian noise with standard deviations σ noise ranging between 5 and 60. Then, denoising filters, with kernel sizes varying from 3 × 3 to 21 × 21, have been applied. For the novel approach, the variable noise levels have been managed referring to σ rfix = 60. Observing the behavior at different kernel sizes is interesting, since establishing which is the best one to adopt is not trivial for any denoising technique, including the accurate software denoising filters provided by MATLAB and here referenced as the touchstone. Table 2 summarizes some of the average PSNR and SSIM reached with respect to the original noiseless images by applying the novel approach and the accurate software denoising filters provided by MATLAB. To highlight the denoising capability of the proposed filters, the average quality metrics of the noisy images are also reported. From Table 2, it can be seen that, when σ noise =5 (i.e. σ r=15) and the kernel size is 5 × 5 (i.e. σ s=1), the proposed approach improves the PSNR of noisy images by 2.88dB. With σ noise equal to 20 and 30, when the 7 × 7 kernel size (i.e. σ s=2) is adopted, such an improvement increases to 7.19dB and 8.29dB, respectively. Table 2 clearly shows that the denoising effects of the new filters are very close to, and sometime better than, those given by the MATLAB counterparts. Figure 10 provides a compact overview in terms of relative errors introduced with respect to the accurate software MAT-LAB filters, as a function of σ noise and k. The negative relative errors for the PSNR and the SSIM bounded to −4% and −14%, respectively, clearly demonstrate the graceful behavior of the proposed approach. It is also worth noting that, in several cases, the new filters introduce positive relative errors, which means that they perform even better than the accurate counterpart.
The above results also show that, as expected, the most convenient kernel size has to be chosen in relation to the specific application, that is to the expected σ noise range. As an example, if the latter is between 5 and 30, the 11 × 11 kernel size seems to be the best choice, since it performs even better than its accurate counterpart. Conversely, the 3 × 3 kernel appears as the most favorable size when σ noise ≥ 40 is expected. However, in practical scenarios, the optimal kernel size choice must also consider available resources and power  budget. This aspect will be discussed more in detail in the next sub-Section.
For purposes of comparison with existing approaches designed to work at fixed σ r, quality tests have been done also on the reduced data set used in [15] and [17], including the ten test images Barbara, Boat, Bridge, Couple, Goldhill, Lake, Lena, Lighthouse, Peppers and Plane. Results plotted in Figure 11 demonstrate that the new σ r-adaptive approximation strategy does not introduce any quality penalty with respect to [17] and systematically overcomes [15].
Finally, Figure 12 reports sample images corrupted with several additive noise levels and allows comparing the images   σ r. Then, the run-time reconfigurable design has been carried out using σ rfix = 60. In the following, such designs are named New Fix and New Rec , respectively.
All the circuits have been implemented using the Xilinx Zynq-7000 device family and the Vivado 2019.2 Software Development Tool. Just for purpose of comparison with previous designs [15], [16], [17], [19], the proposed architecture has also been synthesized on the obsolete Virtex-5 hardware platform by using the ISE 14.7 Design Suite on a Virtual Machine Oracle VM. Table 3 summarizes implementation results achieved in terms of: quality performances, hardware resources utilization, as the amount of occupied LUTs, FFs, BRAMs, and DSPs; speed performances, evaluated in terms of maximum running frequency, number of filtered pixels outputted per clock cycle (ppcc), number of frame and Mega pixels processed per second (fps and Mps); power consumption, analyzed using the interchange format files (SAIF) extracted from post-implementation simulations performed on test images. It can be seen that, at a parity of σ r, images and kernels sizes, the New Fix designs occupy up to 70% and 12% less LUTs and FFs than their direct competitors. It is also worth observing that those new implementations with an increased amount of occupied LUTs and/or FFs significantly reduces the utilized BRAMs, and vice versa.
In terms of speed performances, the New Fix implementations reach frame rates significantly better than their counterparts and exhibit pixels rates ×4.4, ×35 and ×4.1 times higher than [15], [16], and [17], respectively. In comparison with [19], the new design is ∼12.6% slower, but, on the other hand, it saves more than 45% of the consumed power. Such an advantage is obtained without significantly affecting the PSNR/SSIM metrics that are less than 0.3% lower. Table 3 confirms the nice behavior of the New Fix designs in terms of quality performances also in comparison with [15], [16], and [17].
As expected, due to the more complex architecture of the employed PEs, the New Rec designs utilize more hardware  resources than the New Fix implementations and achieve somewhat slower computational speeds. This is the more than reasonable price to pay for obtaining the capability of run-time adapting the denoising filtering to variable noise levels. It is worth underlining that most of the referred competitors does not have this property. This means that, in the presence of variable noise levels such designs cannot guarantee the same quality performances reported in Table 3. As an alternative, the used device could be reconfigured to upload the properly customized design complying with a different value of σ r. However, the not negligible reconfiguration time [24] makes this solution unsuitable to fast adapt the filtering capability to run-time varying noise levels. Conversely, the new approach makes the proposed designs able to run-time adapt them-selves to various noise levels without compromising either the quality performances or the overall computational speeds.
As concluding remarks, it is worth noting that the amount of hardware resources occupied by the above analyzed design, based on the 5 × 5 kernel, is 1.76× and 4.16× lower than those required by the implementations adopting 7 × 7 and 11 × 11 kernels, respectively. Moreover, it guarantees an average PSNR higher than 30dB on the entire reference dataset [22], with σ noise ranging between 5 and 30. For these reasons, such configuration could represent the best tradeoff for a wide range of practical applications.

VI. CONCLUSION
This paper presented an innovative approximation strategy for the hardware implementation of fast low-cost denoising filters based on a new simple piecewise function. In comparison with the accurate software filters, the accuracy loss introduced by the novel approach in terms of PSNR and SSIM is bounded to just 4% and 14%, respectively. In addition to many positive aspects, the proposed system also inherits the limitations of the bilateral filter approach, such as the tendency to remove most of the texture and fine details, or the creation of flat intensity regions and new contours.
Hardware architectures designed as proposed here are able to support different noise levels varying at run-time and overcome state-of-the-art counterparts in terms of both accuracy metrics and hardware characteristics. At a parity of the target FPGA devices, images and kernel sizes, as well as noise levels, the new filters exhibited pixels rates up to ×35 times higher than competitors with power saving up to more than 45%. where he is currently an Associate Professor. He has authored more than 60 papers in the field of VLSI design. His research interests include ultra low power and high-performance design, VLSI circuits, design techniques for emerging technologies, reconfigurable architectures, and embedded systems. He was a member of the Technical Program Committee of several conferences. He is also a member of the Editorial Board of Microelectronics Journal.
STEFANIA PERRI (Senior Member, IEEE) was born in Cosenza, Italy, in April 1971. She received the master's degree in computer science engineering from the University of Calabria, Italy, in 1996, and the Ph.D. degree in electronics engineering from the Mediterranea University of Reggio Calabria, Italy, in 2000. In 1996, she joined the Department of Electronics, Computer Sciences and Systems, University of Calabria, as a Researcher Associate. In 2002, she was appointed as an Assistant Professor of electronics at the Department of Electronics, Computer Science and Systems, University of Calabria. In Summer 2004, she was a Visiting Researcher at the Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA, where she was appointed as an Adjunct Assistant Professor for four years, in 2005. In 2010, she was appointed as an Associate Professor of electronics at the Department of Electronics, Computer Sciences and Systems, University of Calabria. In 2017, she joined the Department of Mechanical, Energy and Management Engineering, University of Calabria. Her current research interests include QCA-based circuits, high-performance embedded systems, low-power design, VLSI circuits for image processing and multimedia, reconfigurable computing, and VLSI design. She is the coauthor of more than 140 technical papers and holds two patents in these fields. She serves on technical committees for several VLSI conferences and as a peer reviewer for several VLSI journals. She is currently an Associate Editor of the Journal of Low Power Electronics and Applications and Sensors.
Open Access funding provided by 'Università della Calabria' within the CRUI CARE Agreement