Investigation of Junctionless Fin-FET Characterization in Deep Cryogenic Temperature: DC and RF analysis

This work presents the SOI Junctionless Fin-FET characterization in Deep Cryogenic behavior (DC-JLFET). Results show that the JLT device is well-suited for various operations, such as computation, sensing, and communication in the quantum field. The cryogenic transfer characteristics, including bias, and interface trap density, are analyzed over a broad temperature range (300 Kelvin down to 4.2 Kelvin). Cryogenic DC and RF analyses were done on the conventional double-gate JL-FET structure, operating at 300 K and below 4.2 K for different geometries. The suggested study illustrates that cryogenic status in the new technology CMOS can be correctly anticipated by calibrating data using an experimental device.


I. INTRODUCTION
The scaling down of the channel lengths in standard metaloxide-semiconductor (MOS) Field-Effect transistors (FET) poses several critical challenges, such as reducing SCEs, increasing on-current, and lower power consumption must be addressed [1], [2], [3]. SOI transistors have been broadly used as a good alternative for further downscaling for the low-power FET operations asked by ITRS. SOI wafers have low variability, improved electrostatic control, and lesser short-channel effects (SCEs) [4], [5], [6], [7], [8], [9]. Also, SOI's lower parasitic capacitances and resistances provide good RF and analog Figures of Merits (FoMs). The junctionless FETs (JLFETs) have been suggested as a further effort to solve the SCEs and stringent requirements of an ultra-steep doping characteristic at the metallurgical interfaces as well as complicated heat budgets in standard transistors [10], [11], [12], [13], [14], [15], [16], [17], [18]. The other way to reduce the SCEs is by using the multiple-gate transistors in the scaled MOSFETs [19], [20], [21]. To improve electrostatic integrity, three modes are combined in this work: SOI, multiple gate FET, and junctionless technology. In silicon structures, The associate editor coordinating the review of this manuscript and approving it for publication was Wei Huang .
creating CMOS-compatible qubits [22], [23] helped us focus on low temperatures of CMOS semiconductor technology for computer operations. MOS transistor structures have been studied at extremely low temperatures since the 1970s to be used in applications and systems, including limitednoise, space devices, energy conversion devices, and so on [24], [25]. Although, despite the various advantages of high-efficiency and low-power information technology [26], cryogenic cooling did not remain in use for computer technology, reversing the pattern established by the ETA-10 liquid-nitrogen-cooled quantum computer [27]. Quantum computers get the theoretical potential, supported by experimental data, to operate in an enormous problem situation and thus can solve several more computer processing issues that traditional computers cannot. Quantum bit (Qubit) manipulation and readout are vital for achieving quantum computers. Another strategy would be to use low-temperature electronics, which perform at/or close to the temperatures at which qubits exist [28], [29], [30], [31], [32], [33], [34]. Aside from quantum computing, the original function for low-temperature devices is dispersed and huge. In the specific situation of Quantum Computers, FinFETs, as the most common logic circuit structure, are the first of many contemporary devices to be investigated for quantum control circuits. In this work, we demonstrate that the electrical specifications of junctionless FETs are highly affected by the physical properties of the structures. As a result, the main goal of this study focuses on the effect of temperature decrement on the working of JLFETs down to 4 K in the DC and RF characteristics. The I/V curve, transconductance (G m ), subthreshold slope (SS), radio frequency (RF), and interface traps have all been investigated. Also, the influence of different geometries (W/L) on the device characteristics has been analyzed. The goal for comparing 40 and 28 nodes is to investigate the channel length effect on the device features.

II. DEVICE CHARACTERISTICS
A 3-D schematic of the DC-JLFET is depicted in Fig. 1. First, we have calibrated the simulation data for validation by regenerating the experimental data of a junctionless FET [35], which is demonstrated in Fig. 2. This work is based on an N-type JLFETT structure on <100> orientation SOI wafers with a 100 nm thick buried oxide layer (BOX) and an active silicon layer with 5 nm thickness. Uniformly doping of active regions of the device is considered at one × 10 19 cm −3 . The gate comprises a 5.0 eV work function with an oxide thickness of 1 nm. The gate mask length ranged from 28 nm to 40 nm, and the gate mask width ranged from 1 µm to 2 µm. Surface roughness, coulomb, and phonon scattering have been considered to investigate the impact of scattering effect on mobility.

III. RESULTS AND DISCUSSIONS A. IMPACT OF CRYOGENIC TEMPERATURE ON THE DC CHARACTERISTICS
This paper investigates the cryogenic temperature effects on the RF and DC modes and also analyzes these effects on the subthreshold slope, threshold voltage, and transconductance. Transfer characteristics of the JLFET structure for short channel sizes (L = 28 nm and L = 40 nm) have been analyzed at various temperatures in the wide range from 4.2-300 Kelvin, as shown in Fig. 3. The widely known point of crossing, which is known as the zero-temperature coefficient (ZTC) [17], [36], [37], has not to rely on the temperature owing to the heat recompense impacts of carrier mobility and threshold voltage (V th ) [35]. The ZTC phenomenon is defined by the fact that for large gate sizes, V th and electron mobility have both been enhanced at lower temperatures [35], whereas those differed in reduction of temperature for short gate length and increment of mobility is not high.
The subthreshold slope SS, described as kT/q (ln10) (mV/dec), decreases the thermal voltage at 77 and 4.2 Kelvin for all structures. As demonstrated in Fig. 4, the SS reduces to 4.5 mV/dec in 4.2 K for L = 40 nm; however, this reduction is smaller than the predicted amount, which is 0.8 mV/dec at extremely low temperatures; this is due to insufficient dopant ionization. Also, the SS is 4.8 mV/dec when the gate size is L = 28 nm.
The I on increases slightly at 4.2 Kelvin for the small-length structures but rises for the extensive-length designs, as shown in Fig. 5. It could be defined by the expression of the electron current [30]: The current density is proportional to the temperatures at low drain voltages, and field-assisted ionization is poor, but at high drain voltages, the current density rises with lowering the temperature due to carrier mobility, and field-assisted ionization is significant in this channel size. The G m improves at 4.2 Kelvin (∼ × 2, W/L = 2 µm/ 28 nm), as illustrated in Fig. 6.
For JLFET structures, the G m curve was plotted in Fig. 6, with different W/L geometries at V ds = 10 mV, while the G m show high degradation in large V gs < V fb in regards to increasing the series resistance R Se . The oscillations observed in G m curves credit this impact to the quantum transport in such Structures [38]. When the V gs of an n-type transistor is raised, electrons may fill the possible sub-band step by step, causing the current to behave step-like. In particular, at extremely small V ds , the quantization of energy states in the conduction band is seen [39] because the total energy at larger voltages is substantially more than the band gap among two quantized energy states.
In a short channel DGJLFET, the V th can be described as [15] (2), as shown at the bottom of the next page, where; where the λ is the natural length and V fb is the flat band voltage. We must note that the β and γ are zero in long channel lengths. Eq. (3) shows that the only temperaturedependent parameter is the V fb . Besides, the V th shifts to higher gate voltages at 4.2 Kelvin versus 300 Kelvin because of incomplete ionization. Indeed, larger drain voltages are necessary to absorb enough electrons to the top to form the inversion area. The V th variation with different temperatures is shown in Fig. 7 with various W/L geometries. It is worth noting that the maximum V th change has been illustrated in W/L = 1 µm / 28 nm ( V th = 0.15 V). Fig. 8 shows that until reaching 77 Kelvin, the remains close to the value at 300 Kelvin. From 77 Kelvin down to 4.2 Kelvin, the slope factor increases sharply.

B. INFLUENCE OF INTERFACE CHARGE DENSITY ON THE JLFET I-V CURVE IN THE DEEP CRYOGENIC TEMPERATURE
The charge density for every unit area measured in interface states Q f is [40]: In this equation, N f denotes the overall distribution of interface traps across the energy. In cryogenic conditions, the concentration of dangling bonds at the junction does not increase considerably. The clear temperature-dependent rise of the rate of N f value (for example, in charge-pump calculations [40]) is because, at very low temperatures, the Fermi level covers a large section of the energy bandgap. This logarithmic rise in trap intensity at the band edge was also required to account for the bend of the I-V curve and the SS degradation caused by conduction-band or valence-band tails [41]. Depending on the type (acceptor/donor) and the placement of the Fermi level in the bandgap, Interface density Nf can be either charged or uncharged. Their charge contribution varies with the surface potential, ψ s . Fig. 9 depicts the transfer characteristics of JLFET in the deep cryogenic temperature and RT with and without interface charge density. The interface traps play an essential role in determining the V th , the µ ch, and the G m of FETs, and their effect is especially evident in the SS of the transfer characteristics. Fig. 10 demonstrates the influence of the various N f on the SS & V th in the deep cryogenic temperature. Fig. 11 shows the JLFET G m curve in deep cryogenic temperatures with various N f . To analyze the effect of the N f on the SS can be expressed [7]: where C f = qN f is the capacitances of the N f at the gate oxide, C ox is the gate oxide capacitance, C Si is the active regions capacitance, and N f represents the interface trap density at the gate oxide. The n is the body factor, defined by n = (C ox +C f +C Si )/C ox for an SOI structure. The impacts of traps related to the BOX layer have been neglected. Fig. 12 illustrates the influence of V ds on the I-V curve of JLFET in the deep cryogenic temperature. As demonstrated in Fig. 12, at higher drain voltages, current density rises with reducing the temperature through mobility, and fieldassisted ionization is critical in the channel. We understand that N f increases with lowering the temperature, achieving 10 13 cm −2 at deep cryogenic temperatures. Fig. 13 shows the impact of the Transconductance Generation Factor (TGF) versus V gs in various cryogenic temperatures. TGF has been described as G m /drain-current relation and represents the power losses of the structure in digital operations. The higher TGF leads to smaller power losses. Plotting TGF, which gives a detailed perspective of the analyzed device, from low-frequency (depletion/partial depletion) application where high gain is obtained to highfrequency (flat band/accumulation) application where higher drive current is needed, seems to be a constructive analysis solution that enables for a first world admiration of the device under research for analog analysis. In the green regime (depletion/partial depletion), TGF is inversely proportional to the SS. On the purple side (flat band/accumulation), It would be proportionally to µ n .C ox /n (where µ n is electron mobility, C ox is gate oxide capacitance, and n is body factor). On the other hand, A device's analog/RF efficiency is mainly restricted by intrinsic terminal capacitances. The effect of temperature on parasitic capacitances versus V gs can be seen in Fig. 14.

C. RF ANALYSIS
The transit frequency (f T ) of FETs is achieved as follows() [42]:  and is calculated from the current gain (H 21 ) and shown in Fig. 15 as one of the main RF FoMs. Due to the lower parasitic capacitances and higher G m , the f T improves, and the maximum f T is achieved, about 563 GHz. Because of the lower variation of capacitances in cryogenic temperatures, the transit frequency f T follows the increment in the G m, as demonstrated in Fig. 7. This rise may be offset by decreased power usage, which is also advantageous for thermal losses from the management system to the quantum bits. This increment becomes particularly significant in shorter channel lengths.
We analyzed the influence of the various temperatures on the unilateral-power-gain (UPG), (f max ) is the frequency where UPG becomes unity, or zero dB, and the transit time (τ ) of JLFET. These ratios have been achieved from the  equations [43], [44]:     The obtained results above equations are illustrated in Fig. 16. The gate resistance (R g ) decreases because of the reduced  resistivity of gate metal contact at the cryogenic temperature, and due to the higher f T at 4.2 Kelvin, f max increases. It can be inferred that the 4.2 Kelvin temperature leads to better performance and reduces transit time. Improvement in G m and f T enables a reduction in transit time. Charge carriers have a very low transit time in the ON-condition. The NF of FETs can be obtained as follows: Fig. 17 shows the impact of various temperatures on the Noise Figure (NF). By reducing parasitic capacitance and due to higher G m , the value of NF reduces at lower temperatures.

IV. CONCLUSION
The effect of cryogenic temperature on an (L = 28 nm and L = 40 nm) Junctionless SOI Fin-FET innovation for quantum information management systems is presented in this paper. Starting with a deep study of the physical structures at extremely low temperatures, actually promoting changes in the essential analog design specifications are achieved, even though increment in the slope factor at very low temperatures decreases the predicted current savings; however, this increase is not significant. The suggested study illustrates that cryogenic status in the new technology CMOS may be correctly anticipated by calibrating data using an experimental device. This is an attractive idea for future small cryogenic models for silicon-based quantum information structures.