Investigation of Input-Output Waveform Engineered High-Efficiency Broadband Class B/J Power Amplifier

This work introduces a new broadband Class B/J power amplifier (PA) design methodology by considering the input-output waveform shaping due to nonlinear CGS-VGS profile in gallium nitride (GaN) radio frequency (RF) devices. A comprehensive time domain modeling of drain voltage and drain current as a function of input nonlinearity is presented to predict continuous Class B/J PA performance. The proposed theory shows that continuous-mode operation can no longer maintain constant PA performance with varying fundamental and second harmonic impedances as predicted by the ideal class-J theory. This paper demonstrates that continuous-mode class B/J operation with input-output waveform shaping yields a new design space with two distinct regions: one advantageous region with capacitive second harmonic load terminations in which PA performance can be enhanced significantly; and another within an inductive second harmonic load area where the performance is degraded compared to that of a classical class B/J PA. For practical validation, source pull measurements and load pull analyses are presented and a broadband Class B/J PA is designed with the proposed second harmonic load and source termination. Source/Load-pull measurements/simulations confirm the theoretical predictions in terms of performance variation across the design space. A high efficiency design space is then identified for broadband PA design. The PA protype demonstrates drain efficiency of (60-73) % with output power above 40 dBm and corrected adjacent channel power ratio (ACPR) better than −55 dBc with digital predistortion (DPD) using 10 MHz LTE signal across (2.2-3.4) GHz.


I. INTRODUCTION
The demand of highly efficient, broadband and linear power amplifiers (PAs) urged the designers more than ever in the quest of enabling key 5G features. As such, the established techniques of PA design methodologies are being revisited to meet the higher demands of 5G infrastructure.
To meet such demands, the harmonic tuned load PAs (Class F/F −1 ) had been extensively utilized for efficiency The associate editor coordinating the review of this manuscript and approving it for publication was Pedro Miguel Cabral . enhancement over tuned load PAs (Class B) [1], [2], [3], [4], [5], [6]. To improve the bandwidth performance, continuous mode of operation were introduced which extended the design space of the Class B/F/F −1 PAs and proposed to maintain the output power and efficiency performance over the band of operation [7], [8], [9], [10], [11], [12], [13], [14], [15]. In [3], a Class X PA is proposed where it has been proposed that the different output harmonic termination could have an optimum fundamental termination which are theoretically predicted and proposed load design space high efficiency PA performance. However, all these works were proposed either by ignoring the input nonlinearity or by avoiding it considering a source second harmonic short circuit at the gate node. But input nonlinearity is inevitable in broadband designs since it is impossible to maintain a harmonic short for a broad frequency range. As such, PA performance analysis with the impact of input nonlinearity is crucial.
Input nonlinearity is introduced by the gate to source capacitance (C GS ) nonlinearity. Traditionally, input nonlinearity had been reported detrimental to the PA performance and typically avoided by presenting a harmonic short circuit at the input or by a counter-acting nonlinearity [16], [17], [18]. Recently, comprehensive studies on input nonlinearity and its impact on PA performance have been investigated [19], [20], [21], [22], [23], [24], [25], [26]. In [23], the input nonlinearity as a function of second harmonic source terminations is mathematically modeled and utilized to design efficiency enhanced broadband Class F/F −1 PA design [24], [25]. Also, input nonlinearity is considered in continuous mode Class B/J PA design in [26] but lacks the physical correlation to the input nonlinearity generation and source harmonic terminations. Thus, a proper explanation on continuous Class B/J PA behavior with input-output nonlinearity is still missing and proper design methodologies are yet to be explored. Figure 1 (Case I) shows theoretically predicted ideal Class B/J performance across a second harmonic load (Z 2L ) design space around the short circuit termination, widely adopted to realize broadband PAs. However, in practice, performance variation is observed for the continuous mode Class B/J PAs. Many previous works [27], [28], [29], [30], [31], and load pull studies have shown that capacitive regions on smith chart show higher efficiency than inductive region with second harmonic loading. However, the theoretical explanation behind the phenomenon is still unknown and demands a comprehensive study.
This paper investigates the impact of input-output waveform shaping for broadband Class B/J PAs with new time domain drain current and drain voltage modeling. This new model captures the actual behavior of continuous class B/J PA implementations. To the best of authors' knowledge, this work is the first to point out to device input nonlinearity as the reason behind performance variation of continuous Class B/J PAs, as graphically illustrated in Fig.1. It is confirmed through theory and measurements that the Z 2L termination in the capacitive region provides better efficiency than the inductive region for non-short second harmonic source (Z 2S ) termination, for broadband Class B/J PAs under input nonlinearities. Fig. 1 gives an overview of the paper through three cases with different waveforms, design spaces, and large signal performance metrics. It is methodologically shown that the proposed Z 2S termination (case III) provides better performance compared to conventional continuous Class J (case I) and ensures input design space is kept outside the sub optimal region (case II).
The rest of the manuscript is organized as section II covering the input nonlinearity effects on continuous Class B/J PAs. Section III provides the practical validation of the theory presented through load pull. The PA measurement results are presented in section IV followed by conclusions in Section V.

II. INPUT HARMONIC CONTROLLED CLASS B/J THEORY
Power Amplifier (PA) performance parameters, like output power and efficiency, are functions of voltage and current waveforms. These voltage and current waveforms can be shaped as per specific requirements with a good understanding and careful control over input-output nonlinearities of the device being used to achieve different PA modes of operation. This section will discuss the impact of input-output nonlinearities on Class B/J PAs.

A. CONVENTIONAL CLASS B/J PA
The time domain gate voltage waveform without any input nonlinearity can be expressed as [1] v GS where, V GS0 is the gate bias voltage and V GS1 is the fundamental voltage magnitude. Assuming constant transconductance, the time domain current waveform can be represented as [1] i DS (θ) = I m cos θ if |θ| < π/2 0 elsewhere (2) where, I m is the maximum drain current. Similarly, the drain voltage of the conventional continuous Class B/J PA is expressed as [1] v where, V DD is the drain voltage, V k is the knee voltage, and σ is the design continuum factor which varies between -1 to +1. From (2) and (3), the optimum impedance for Class B/J PAs can be calculated as  where, R opt,B = 2(V DD -V K )/I m . The output power and efficiency can be estimated as The waveforms, design space, and drain efficiency (η) are illustrated in Fig.1, (Case I) conventional continuous Class B/J PAs. Theoretically, we can see a constant efficiency across the Class B/J design space.

B. IMPACT OF INPUT NONLINEARITY ON CLASS B/J PAs
Due to the presence of parasitic capacitances of the device being used for any PA design, the performance variation occurs both at small signal as well as large signal in a significant manner. It should be noted that the reference plane of this mathematical analysis is at the C GS reference plane at the input and at the intrinsic current generator plane at the output For the FET model, we have considered a constant transconductance characteristics to simplify the analyses. If a sinusoidal input voltage (V in ) is applied to the extrinsic gate terminal of a power FET device, due to its nonlinear C GS vs v GS profile, the intrinsic gate voltage (v GS ) waveform is reshaped accordingly. This modified v GS consequently reshapes the drain current waveforms and impacts PA performance. Nonlinearity effects can be taken into account by considering higher orders of harmonics being generated due to parasitic capacitances. The gate voltage (v GS ) time domain expression, considering up to second order effects of input nonlinearity, can be redefined as The gate voltage expression can be normalized, v GS,norm (θ, γ , (11) where, γ = V GS2 /V GS1 , the ratio of second harmonic input voltage (V GS2 ) to fundamental (V GS1 ), and ϕ 2 , the phase difference between second and fundamental voltage component, are defined as the input nonlinearity parameters. The gate voltage waveforms are shaped due to input nonlinearity and shapes the drain current and drain voltage waveforms which consequently impacts the PA performance.

1) DRAIN CURRET MODELING
In the presence of input nonlinearity, the device conduction angle changes depending on the set of (γ , ϕ 2 ) parameters [19]. Considering the modified conduction angle be β, the normalized drain current can be expressed as where, ε (γ , ϕ 2 ) is defined as a limiting function which keeps the drain current within safe operating limits of the device for all sets of (γ , ϕ 2 ). For a given value of (γ , ϕ 2 ), at θ = θ m the drain current amplitude becomes maximum. To keep maximum amplitudes of the normalized drain equal to unity for all sets of (γ , ϕ 2 ), the limiting factor can be expressed as Substituting θ = ±β 2 in (11) gives us On solving (14) for β, we can get the conduction angle variation as function of (γ , ϕ 2 ). Fig. 2(a) shows contours of β which indicates that for different values of γ and ϕ 2 , the device conducts more and for others it conducts less.
To understand the impact of input nonlinearity, we consider three cases as defined in Table 1 where Case I represents nominal state of drain current under no input nonlinearity i.e., second harmonic source impedance (Z 2S ) as short, giving β = 180 • (Class B). Case II and Case III takes impact of input nonlinearity into consideration through two sets of γ and ϕ 2 , which can be practically realized, with former one giving maximum modified conduction angle (∼ 220 • from nominal 180 • ) and the later one giving minimum modified conduction angle (∼ 155 • from nominal 180 • ).
The blue curve in Fig. 2(a) indicates the values of (γ , ϕ 2 ) taken by simulating a nonlinear model of GaN transistor for VOLUME 10, 2022  second harmonic source reflection coefficient at the intrinsic gate of magnitude (| 2S |) fixed at 0.9 at 2.6 GHz to have a good correlation with practical implemented PAs. For a given device periphery, the 2S can be evaluated as function of γ , ϕ 2 using nonlinear polynomial fitting of gate to source capacitance as given in [23]. Figure 2(b) illustrates the (γ , ϕ 2 ) values realizable with respect to 2S while keeping the | 2S | = 0.9. Case I, Case II and Case III data points are taken from the blue curve with first case showing β = 180 • for which γ ≈ 0, second case showing maximum and third case minimum conduction angle. For these three cases, Fig. 2(c) and 2(d) shows gate voltage and drain current waveform under the presence of input nonlinearity as per Table 1.
The Fourier expansion of the normalized drain current from (12) gives the dc component as Figure 3 shows contours of the normalized dc current for possible sets of (γ , ϕ 2 ). It shows that dc current increases for (90 • < ϕ 2 < 270 • ) and reaches maximum value for ϕ 2 as 180 • . The rest of the Fourier coefficients for the normalised drain current from (12) are: where, I 1r , I 1q , I 2r , I 2q , I 3r and I 3q are the fundamental real, fundamental reactive, second harmonic real, second harmonic reactive, third harmonic real, and third harmonic reactive components of the normalized drain current respectively. Fig. 4(a)-4(f) shows contours of drain current components for different combinations of (γ , ϕ 2 ). We observe that for Case I, the current components are as per ideal Class B, while moving from Case I to Case II and then to Case III, the values of both real and reactive current components shift because of which we observe changes in shape of current waveform. This helps in understanding contribution of drain current components to waveform shaping controlled by (γ , ϕ 2 ) which is a function of second harmonic source termination (Z 2S ).

2) CONVENTIONAL CONTINUOUS CLASS B/J VOLTAGE MODELING
Conventionally, the Class B/J drain current and voltage waveforms are expressed as in (2) and (3). In this work, the drain current waveform has been remodeled with input nonlinearity and defined as in (12). It is important to note that with the addition of input nonlinearity, the drain current waveform changes with respect to Z 2S , affecting performance of continuous Class B/J significantly. Accordingly, the impedances can be calculated for fundamental and second harmonic as where, Z iL is the i th harmonic impedance for respective harmonic real (V ir ,, I ir ) and reactive (V iq , I iq ) drain voltage and current components respectively. The impedance design space for the three different cases are shown in Fig. 5 (3) results in lossy harmonic impedances as well as unrealizable impedance terminations as it goes out of the Smith chart. Although, lossy resistive harmonic terminations are realizable, they cause harmonic power dissipation and degrade efficiency and output power performance. In this regard, a new drain voltage model is necessary for continuous Class B/J PA taking into consideration the impact of input nonlinearity.

3) CLASS B/J VOLTAGE MODELING WITH INPUT NONLINEARITY
We have seen in the previous section that how conventional time domain drain voltage modeling results in unrealistic second harmonic load (Z 2L ) design space under the presence of input nonlinearity. Whereas a designer is free to choose Z 2L as desired. For optimum efficiency performance reducing power consumption at harmonics, typically, reactive harmonic terminations are recommended. In this section, we present a generic drain voltage modeling as a function of second harmonic load design space which is more practical and design oriented. To do so, the load impedances can be defined as where, Z 1L , Z 2L , and Z 3L are the fundamental, second, and third harmonic load impedance, respectively. Considering a broadband Class B/J PA where third harmonic is terminated as short, a generic drain voltage waveform can be represented as where, V 1r , V 1q , V 2r , V 2q are the fundamental real, fundamental reactive, second harmonic real and reactive voltage components, respectively. The drain voltage components, V 1r , V 1q , V 2r , and V 2q in (19) can be calculated following the below steps: 1) V DD is the supply voltage chosen by the application and design requirement. 2) From (17) and (18), on solving for drain voltage (V ir − jV iq ) and equating the real and imaginary coefficients, different voltage components are calculated as 3) For a defined range of X 2L as [−X 2,lim , +X 2,lim ], V 2r and V 2q are calculated for a given value of X 2L from (20c) and (20d) knowing I 2r and I 2q from (16c) and (16d). 4) Now, (V 1r , V 1q ) need to be estimated such that the drain voltage remains non-negative for the defined second harmonic load design space. From a generic harmonic tuned (HT) drain voltage expression represented as [1] v DS,HT (θ) = − cos θ − k 2 cos (2θ) − k 3 cos (3θ) where, k 2 and k 3 are second and third harmonic real voltage components normalized by fundamental HT drain voltage, a voltage gain function defined for each combination of k 2 and k 3 is expressed as [1] ( As shown in Fig. 6, we can observe (k 2 , k 3 = 0) as function of k 2 to keep the generic voltage in (19) as non-zero considering third harmonic load impedance as zero. The voltage gain as a function of k 2 can be defined as [1] ( For traditional Class B, voltage gain function becomes unity as k 2 and k 3 both remains zero, giving a pure VOLUME 10, 2022 sinusoidal waveform. The generalized drain voltage expression can be rewritten using (22)(23) as The drain voltage from (24) presents a family of drain voltage waveforms depending on the value sets of (k 2 , k 3 ). 5) Calculate k 2 as V 2r /(V DD -V k ). 6) Based on the value of k 2 , (k 2 ) can be determined from (23) and calculate V 1r as (k 2 ) (V DD − V k ). 7) Now, the remaining drain voltage component V 1q in (24) is estimated satisfying the condition min(v DS,iB/J (θ)) = 0 which finds the solution for drain voltage to an arbitrary Z 2L termination chosen by the designer. The drain voltage modeling procedure is summarized in the flowchart shown in Fig. 8. The drain voltage waveforms along with the drain currents for three different cases are shown in Fig. 7 for three different Z 2L terminations modeled by the above steps 1-7. From waveforms we observe that for case II and III, the output voltage swing in capacitive region, is higher as compared to short and inductive terminations. The drain current and voltage waveforms have relatively less overlap in case III for both capacitive and inductive regions as compared to case II and case I, thus ensuring higher efficiency.
This analysis ensures a non-negative drain voltage waveform and provides the fundamental design space as a function of second harmonic reactance X 2L . This analysis allows the designer to choose second harmonic load termination as desired under the presence of input nonlinearity. For, X 2L = 0 or any value of X 2L , the drain voltage calculation is modeled with steps 1-7 described in this section previously.
At this stage, it should be noted that selecting X 2L away from short increases drain voltage maximum which is typical Class B/J PA behavior. However, it is important to select appropriate limits of X 2L such that the device operates reliably in the safe drain voltage region. Thus, it is important to know the maximum limit of X 2L .
It has been observed that the maximum drain voltage varies linearly across X 2L . For instance, considering the limit as 3V DD ≥ v DS,iB/J (max) ≥ 2V DD , an approximate relationship for Case I can be expressed as In a similar manner, for a given set of (γ , ϕ 2 ), [−X 2,lim , + X 2,lim ] can be calculated which allows maximum drain voltage swing.

C. DESIGN SPACE OF CLASS B/J PAs WITH INPUT NONLINEARITY
With the voltage and current waveforms obtained as a function of input nonlinearity, fundamental drain impedance  can be estimated for all possible combinations of (γ , ϕ 2 ), using (17). Using the cases defined in Table 1, fundamental impedance is plotted as a function of second harmonic load impedance. As seen in Fig. 9, Case I is conventional continuous Class B/J design space, however, the optimum fundamental impedance changes for Case II and Case III. Due to the contribution of input nonlinearity, the optimum design space for Case II and Case III is asymmetrical across real axis as compared to Case I. This helps us in understanding that fundamental loading varies as a function of second harmonic source and design needs a thoughtful matching control to achieve optimum performance from the device.

D. THEORETICAL ASYMMETRIC CLASS B/J PERFORMANCE
The dc power for the new drain voltage (v DS,iB/J (θ)) and drain current along with the output power and drain efficiency can be estimated as (27) η drain (β, γ , ϕ 2 ) = P out P DC × 100 (28) Figure 10 shows calculated normalized power and efficiency contour plots for three extreme limits of X 2L terminations which are (-j3π 8.R opt,B , j0, j3π 8.R opt,B ). Though capacitive and inductive X 2L gives us mirror image contours, the realizable/simulated set of (γ , ϕ 2 ) are as shown by the blue curve, with circled dots as data points, in all contours. We observe significant variation in efficiency and power across load terminations, unlike ideal Class B/J (Case I). The efficiency values for fixed load terminations are as shown in Table 2. We had previously observed that current waveforms for all load terminations are same for a given set of (γ , ϕ 2 ). The swing and shape of drain voltage waveforms vary across the loads causing variations in power and efficiency of Class B/J PA under input nonlinearity. Due to which there exists asymmetry in performance across symmetric Z 2L load terminations. Thus, the continuous Class B/J PA with constant power and efficiency does not exist in reality since the input nonlinearity effects on input waveform is inevitable in broadband design.
Considering three cases as per Table 1 for the predefined X 2L range, efficiency is plotted across the load as shown in Fig. 11. As can be seen from Fig. 11, moving from extreme inductive Z 2L termination towards short and upto extreme capacitive Z 2L , efficiency performance enhances significantly for both case II and case III. This also gives us an insight that drain efficiency for capacitive X 2L is relatively VOLUME 10, 2022 less sensitive to variations in β than inductive and short X 2L terminations.
This theoretical analysis give us an insight that for boradband design, Z 2S transiting between the three cases (I-III-II), capacitive X 2L termination offers less variation in efficiency compared to other two terminations, with peak efficiency being higher than that of the inductive X 2L . Hence, this gives designer the freedom of having less variation in perfromance across the band in addition to having optimal efficiency. As such, capacitive X 2L design space is proposed for broadband Class B/J PAs in this work.

III. LOAD/SOURCE PULL RESULTS
To validate the realistic Class B/J PA performance across X 2L terminations under the presence of input nonlinearity, harmonic source and load pull experiments were conducted with a 2-mm GaN device at 2.6 GHz. For Class B loading conditions, source pull measurement data was collected at intrinsic reference plane with maximum efficiency (MXE) fundamental load termination and harmonics short at drain node. Fig. 12 shows power added efficiency (PAE) and output power contours for intrinsic Z 2S swept across the whole smith chart. It can be seen from Fig. 12(a)    performance in Case III is improved by 5% points compared to Case I. On the other hand, the Case II efficiency performance tanks significantly as predicted by theoretical analyses. This proves the necessity of considering input nonlinearity in broadband Class B/J PA design.
For efficiency and output power performance, the source harmonic design space is identified for broadband Class B/J PA design. Once Z 2S termination is fixed, load pull simulations are carried out with Fig. 13 (a)-(c) showing drain voltage and current waveforms for three fixed Z 2S terminations for three fixed X 2L terminations. The waveform validates the theoretical Class B/J waveforms. The simulation was carried out at maximum power (MXP) with 3 dB gain compression.
The simulated performance variation across X 2L is shown in Fig. 14. To understand the shift in MXP and MXE points across X 2L terminations, contours are plotted in Fig. 15 for Case I, Case II and Case III. It is observed that for capacitive X 2L termination, Case III offers relatively higher MXE than Case II. Also, for short and inductive X 2L terminations, Case III MXE values drops less as compared to Case II. These plots prove and confirm the theoretical prediction of performance shifts.
In Fig. 14, output power and efficiency has been plotted across X 2L both at MXP and MXE. We observe that the power remains almost constant around 40 dBm with efficiency being relatively higher for capacitive X 2L termination region. The theoretical time domain analysis typically predicts and falls more in line with MXE than MXP load pull simulations. Comparing Fig. 14(b) with Fig. 11, the variation in efficiency is less in all three cases for load pull simulation for nonshort X 2L as the time domain modelling presented in this paper rather simplifies the impact of input nonlinearity for the extraction of design space. But even with differences, load pull results follow the trends as per theoretical predictions. This confirms with the theoretically estimated performance variation plot from Fig. 11.
The results in Fig. 14 are significant in that it explains the asymmetry of efficiency performance in Class B/J PAs in practice due to input nonlinearity and also validates that the capacitive Z 2L load terminations, in fact, improves the efficiency performance. Thus, it is desirable to realize capacitive Z 2L termination when aiming for high efficiency Class B/J PAs in broadband operation.

IV. MEASUREMENT RESULTS
For practical validation of the proposed theory, GaN CG2H40010F device was used to design a broadband Class B/J power amplifier (PA) in a Rogers RO4003C board with a thickness of 32 mils. The quiescent current of the device was set at 25 mA with drain bias voltage of 28 V. The PA was stabilized using an input RC network with R = 147 , and C = 2.4 pF. Fig. 16 shows the extracted parasitic network which was used to access the intrinsic gate and drain terminal of the device. Using this terminal, intrinsic impedances were controlled across the desired band to realize Class B/J operation. Fig. 17(a) shows the schematic of the proposed PA with realized input matching network (IMN) and output matching network (OMN). Fig. 17(b) shows the picture of the implemented PA prototype.
The measurement of the designed PA was conducted using a test setup consisting of a signal generator EXG and signal analyzer EXA from Keysight as N5172b and N9010b, respectively. A pre-amplifier from Mini-Circuits, a 20W 30 dB attenuator, an isolator, and a power sensor was utilized to make a power drive-up test bench as shown in Fig. 17(c). The realized output matching network (OMN) trajectory of the PA is designed using the large signal model.
To exploit the maximum performance advantage of Class B/J operation, input second harmonic is designed in the region to be non-short, to shape input waveform using region determined by γ , ϕ 2 . The IMN is designed such that intrinsic Z 2S trajectory follows the region on smith chart equivalent to Fig. 12 as shown in Fig. 18(c) at intrinsic node. The OMN is designed, with reference to intrinsic node, for optimal fundamental impedance with Z 2L preferred to be in the capacitive region and Z 3L to be near short in the smith chart as shown in Fig. 18(b). The extrinsic terminal impedance trajectory was accordingly observed and are as shown in Fig. 18(a). The PA prototype with input and output fundamental and harmonic   matching circuitry is as shown in Fig. 17(b) implementing Class B/J mode operating in capacitive region for load second harmonic in order to ensure best possible efficiency for the intended frequency band.
As reported in Fig. 18(d), the measured drain efficiency (DE) across 2.2-3.4 GHz frequency band is between 60% and 72.8%, giving a fractional bandwidth of 42%. The PA provides saturated output power and gain above 40 dBm and 10 dB, respectively. The power drive-up for (2.2-3.4) GHz is shown in Fig 18(e) up to 3 dB gain compression. To confirm the PA class of operation, the simulated drain voltage and current waveforms are reported at 2.4, 2.6 and 2.8 GHz, respectively in Fig. 18(f). As observed, the half sinusoidal voltage has ∼2.5xVdd voltage swing while current is also half sine confirming the Class B/J mode of operation for the targeted performance over broadband range of frequencies.
Furthermore, the obtained results are benchmarked against the existing works in high-efficiency HT PA design. The purpose of this work is to analyze and find appropriate design space for broadband Class B/J PAs considering only reactive or nearly lossless harmonic terminations unlike bandwidth enhanced extended Class B/J PAs utilizing resistive harmonic loadings. The comparison is reported in Table 3 where the performance of the PA stands out in the literature so far. The saturated power variation is less than 0.8 dB as compared to previous work without compromising efficiency and linearity across the band of the designed PA.
For assessment of linearity of the fabricated PA, a 10 MHz LTE modulated signal with peak to average power ratio (PAPR) of 10 dB is used at 33 dBm average power. The average efficiency of the PA is measured between 30% to 36% with uncorrected adjacent channel power ratio (ACPR) −28.5 dBc to −32 dBc as shown in Fig. 20.
The output of the PA is modelled and linearized by memory polynomial DPD model with memory depth of 5 and polynomial order of 7. Fig 19 shows the output spectrum for signal before DPD and after DPD model application. The corrected ACPR is below −55 dBc across the bandwidth as shown in Fig. 20.

V. CONCLUSION
For broadband PA design, input nonlinearity is inevitable since a harmonic short termination cannot be maintained in practice over broadband operation. This paper investigates waveform engineered broadband Class B/J PAs under the presence of input nonlinearity. The performance of broadband Class B/J PAs are mathematically modeled and explains VOLUME 10, 2022 the performance variation in broadband Class B/J PAs in practice. It has been shown that it is indeed the input nonlinearity which causes efficiency performance variation in Class B/J PAs across the Z 2L design space. As such, this works identifies and proposes capacitive Z 2L design space for broadband Class B/J PAs for optimum efficiency performance. Theoretical findings are validated with extensive load pull results. A proof-of-concept PA prototype implementing the proposed input-output harmonic design space was demonstrated showing efficiency 60-73% over the bandwidth 2.2-3.4 GHz. The PA shows excellent linearizability with corrected ACPR below −55 dBc. From July 2016 to December 2017, he was an Assistant Professor at the SSGI Faculty of Engineering and technology, Bhilai, Chhattisgarh, India. He is also an Intern with Renesas Electronics Corporation, Bengaluru, India. His research interests include broadband high-efficiency power amplifiers, continuous mode harmonic controlled power amplifiers at S-band, and waveform engineering.
SAGAR DHAR (Member, IEEE) received the Ph.D. degree in electrical and computer engineering from the iRadio Laboratory, University of Calgary, Calgary, AB, Canada, in 2020.
He is currently a Staff RF Design Engineer developing power amplifiers for 5G infrastructures with Renesas Electronics America Inc., San Diego, CA, USA. His current research interests include high-efficiency radio frequency (RF) power amplifiers, Doherty power amplifiers, monolithic microwave integrated circuit (MMIC), large-signal device modeling, digital signal processing, and load-pull techniques.
Dr. Dhar was a recipient of the Izaak Walton Killam Pre-Doctoral Scholarship, the AITF Doctoral Scholarship, the Open Doctoral Scholarship, the Transformative Talent Internship Award, the Academic Excellence Award, and the Research Productivity Award.
TUSHAR SHARMA (Member, IEEE) received the Ph.D. degree in electrical engineering from the University of Calgary, Calgary, AB, Canada, in 2018.
He was a Postdoctoral Researcher at the Integrated Micro-systems Research Laboratory, Princeton University, Princeton, NJ, USA. He is currently a Staff RF Engineer with Renesas Electronics Corporation, San Diego, CA, USA, and a Visiting Professor with IIT Bombay, Mumbai, India. He has more than 45 publications in international journals and conferences along with four granted patents. His research interests include high-frequency novel reconfigurable techniques in radio frequency (RF) and millimeter-wave (mm-Wave) transmitters, broadband high-power gallium nitride (GaN) power amplifiers, large-signal device modeling, technology characterization, digital signal processing, mm-Wave amplifiers, and waveform engineering.