Capacitor-Current-Feedback With Improved Delay Compensation for LCL-Type Grid-Connected Inverter to Achieve High Robustness in Weak Grid

To attenuate the resonance of the LCL filter, capacitor-current-feedback (CCF) active damping has been extensively adopted in LCL-Type grid-connected inverters. Owing to the appearance of a negative damping region caused by the digital control delay, however, the damping performance has significantly deteriorated, thus the system is susceptible to being unstable under weak grid operation. To address this issue, this paper proposes an improved delay compensation method, which can effectively extend the boundary frequency of the positive equivalent resistance region from <inline-formula> <tex-math notation="LaTeX">$f_{s}/6$ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$f_{s}/4$ </tex-math></inline-formula>. Furthermore, the resonance frequency forbidden region of the LCL filter can be eliminated. In doing so, strong robustness against the grid impedance variation and high noise immunity can be achieved. To guarantee the system stability and obtain good control performance after compensation, a detailed parameters design procedure for the current regulator and the CCF coefficient is further presented. At last, experimental results are provided to confirm the theoretical analysis and verify the effectiveness of the proposed delay compensation method.


I. INTRODUCTION
NOWADAYS, driven by the increasing concern about energy shortage and environmental pollution problems, distributed power generation systems (DPGSs) are attracting growing attention. As the power conversion interfaces between the DPGSs and the public grid, in which, inverter plays a key role in injecting stable and high-quality current into the grid [1], [2].
To reduce the switching harmonics content in the output current, an L or LCL filter has been widely used, while the total volume required for the LCL filter is smaller for the same harmonic attenuation performance [3]. However, an inherent resonance problem is introduced by LCL filter, which might lead to system instability. To address this issue, damping methods must be adopted to suppress the resonance The associate editor coordinating the review of this manuscript and approving it for publication was N. Prabaharan . peak [4], [5], [6], [7], [8], [9], [10]. Passive damping is a direct way to dampen the LCL resonance by inserting a passive resistor in series or parallel with the filter network [4], [5]. This is a simple and effective way while it also introduces into considerable power loss, which is not cost-effective. Compared with passive damping, active damping features high efficiency and flexibility, and it can be implemented in two ways. One is based on digital filters, which are cascading with the current regulator [6]. The other way is based on filter state variables feedback [7], [8], [9], [10]. This article adopts the capacitor-current-feedback (CCF) active damping method, which is extensively used in industry due to its simplicity and effectiveness [10].
For obtaining high flexibility, the grid-connected inverter is most digitally controlled. Considering the influence of digital control delay [11], however, the CCF active damping performance is weakened [12], [13], [14], [15], [16]. As revealed in [12], it is no longer equivalent to a pure resistance but an impedance that varies with the frequency of the system. In [13], one-sixth of the sampling frequency f s /6 is regarded as the critical frequency, signed as f cri , which is the boundary frequency of the positive equivalent resistance region. When the actual resonance frequency is higher than the critical frequency, the open-loop unstable poles would be introduced into the control loop, leading to nonminimum-frequency behavior. Note that, if the resonance frequency is too close to the critical frequency, the system is apt to be unstable due to the inadequate gain margin. So, f cri and its vicinity can be defined as the resonance frequency forbidden region [14]. In particular, when the resonance frequency is equal to f s /6, the system stability cannot be maintained [16]. Therefore, the digitally controlled gridconnected inverter with CCF active damping is susceptible to instability under weak grid conditions.
To mitigate the adverse effect of digital control delay on the CCF active damping, numerous solutions are proposed [12], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], which can be classified into two types. One is to directly reduce the digital control delay. In [12] and [17], the computation delay is reduced by shortening the time interval between the signal sampling instant and the PWM reference update instant. However, signal aliasing and switching noises might be introduced. To overcome this drawback, the real-time computation scheme is proposed in [18] by immediately updating the computed PWM reference. Nevertheless, it is highly dependent on DSP computation performance. In [19], the multiple sampling scheme is proposed, which is equivalented to reducing the computation delay by increasing the sampling frequency. Nevertheless, it is also susceptible to aliasing and switching noise.
Another method is to use the model-based predictive control [20], [21], [22] or the model-free phase-lead compensator [23], [24], [25], [26], [27], [28], [29], [30], [31] to compensate the digital control delay. In [20], the smith predictor is proposed to alleviate the delay effect, which is effective and more readily implemented. However, it is sensitive to the variation of system parameters and operating conditions. State observer can also be used to calculate the next beat of system state variables for compensating the computation delay [21], [22]. However, it also needs modeling error mitigation, which imposes extra computation burdens. In [23] and [24], the RC damping and the RLC damping are respectively proposed by feeding back capacitor current with a first-order high-pass filter (HPF) and a secondorder one, which can extend the boundary frequency of the equivalent resistance region from f s /6 to f s /3. Nevertheless, it is subject to noise amplification, which is introduced by the HPF. Based on the graphical evaluation, Lu et al. [25] investigate several phase-lead compensators, e.g., linear predictor [26], first-order phase-lead compensator [27], [28], second-order generalized integrator [29] and propose a novel phase-lead compensator. Those above-mentioned compensators are revealed that can compensate a maximum time delay of half-sampling period. The characteristic of them are that the higher phase compensation, the higher gain in high frequency region. To compensate more phaselag resulting by the digital control delay, a second-order phase-lead compensator is respectively inserted into the CCF path and the feedforward path [30], [31], which has significant phase-lead performance and higher magnitude response near the Nyquist frequency. However, those delay compensation methods put more attention on the phaselead performance of the compensator while neglecting the high magnitude response in high frequency region, which introduces significant noise amplification and increases the difficulty of control parameters design.
In this paper, an improved delay compensation method with better noise immunity performance is proposed. After compensation, the positive equivalent resistance can cover the range of (0, f s /4), and the resonance frequency forbidden region is eliminated. Thus, the system robustness against the grid impedance variation is enhanced and noise amplification can be relieved.
The rest of this paper is organized as follows. In Section II, the configuration of the system is described and the mathematical model in discrete-domain is presented. In Section III, the effect resulting by digital control delay on the damping performance is investigated. In Section IV, an improved delay compensation method with better noise immunity performance is proposed and the stability analysis of the system after compensation is further analyzed detailedly. For obtaining good control performance, the detailed parameters design procedure is also presented. In Section V, the experimental results are shown to verify the validity of the proposed delay compensation method. Finally, Section VI concludes this paper. Fig. 1 shows the configuration of a digital controlled singlephase LCL-Type grid-connected inverter, in which V in is the DC voltage, and v g denotes the grid voltage. L 1 is the inverterside inductor, C is the capacitor filter, and L 2 is the grid-side inductor, which constitutes the LCL filter. H i1 and H i2 are the sense coefficient of the capacitor current i c and the grid-side current i g , respectively. The main purpose is to regulate i g to be sinusoidal and synchronized with the voltage at the point of common coupling (PCC). So, the demanded amplitude I * , which is generated by the outer voltage loop, and the phase θ extracted by the Phase-locked loop (PLL) from v PCC constitute the current reference i ref . The grid impedance at PCC composes of resistance and inductance. Since grid resistance can contribute to damping to some degree, thus grid resistance is ignored to emulate the worst situation. A proportional-resonant (PR) current controller G R is applied to achieve zero steady-state error tracking.

II. MODELING THE DIGITAL CONTROLLED LCL-TYPE GRID-CONNECTED INVERTER
According to Fig. 1, the continuous-domain control block diagram of the digitally controlled LCL-Type grid-connected inverters is given in Fig. 2(a), where 1/T s is represented the sample [32]. K PWM is equivalent to the inverter bridge gain, which can be approximated as v inv /v tri . v inv and v tri are respectively the inverter bridge output voltage and the amplitude of the triangular carrier. The digital control delay contains computation delay and PWM delay [33]. In order to avoid multiple intersections between the modulation signal and the carrier signal, there is one sampling period delay between the current loading instant and the current sampling instant, which is the computation delay. In s-domain, the computation delay can be expressed as The modulation signal should remain unchanged and compare to the triangular carrier, this process can be modeled by ZOH, which is written as follows According to (2), a half sampling period delay 0.5T s is introduced by the PWM process. Therefore, the total delay in the control loop will be 1.5T s , which consists of computation delay (one sampling period delay) and PWM delay (0.5T s ). G R (s) is the PR current controller, expressed as where K p is the proportional gain and K r is the resonant gain, ω o = 2πf o is the fundamental angular frequency. ω i is the resonant cutoff frequency, due to the typical ±1% fluctuation of the grid fundamental frequency f o , ω i is set as π.
The transfer function from the grid-side current and the capacitor current to the inverter bridge output voltage can be respectively obtained as where ω r is the inherent resonance angular frequency, expressed as shows the control block diagram of the digitally controlled LCL-Type inverter with the CCF active damping in z-domain. G ig (z) and G ic (z) can be respectively derived by Z-transform to (7) and (8) with ZOH as According to Fig. 2(b), the discrete-domain open-loop gain can be derived as (9), shown at the bottom of next page, and the discrete expression of G R (z) can be obtained as

III. IMPACTS OF THE CONTROL DELAY ON THE CAPACITOR-CURRENT-FEEDBACK ACTIVE DAMPING PERFORMANCE
In order to analysis the effect of control delay on the CCF active damping, control block diagram in continuousdomain and its equivalent transformation is shown in Fig. 3. Replacing the feedback variable i c (s) with u c (s), and moving the feedback node from the output of G R (s) to the input of 1/sC. By means of the equivalent transformation, the CCF active damping can be equivalent to a virtual impedance Z eq paralleled with the filter capacitor [34], expressed as Substituting s = jω into (11), yields According to (12), Z eq can be represent as a parallel connected between a resistor R eq and a reactor X eq , expressed as According to (13) and (14), the frequency characteristics of R eq and X eq can be drawn in Fig. 4. As seen, R eq > 0 when f r ∈(0, f s /6), R eq < 0 when f r ∈(f s /6, f s /2), and R eq = 0 when f r = f s /6. Obviously, f s /6 is the boundary frequency of the positive equivalent resistance region, which can be defined as the critical frequency f cri . With respect to X eq , X eq > 0 when   f r ∈(0, f s /3), which is inductive. X eq < 0 when f r ∈(f s /3, f s /2), which is capacitive. Note that, when X eq > 0, f r increases with the increase of H i1 . Thus, a higher actual resonance frequency is yielded, signed as f r . When X eq < 0, f r is lower than f r . According to (9), the Bode diagrams of the loop gain T D (z) with G R (z) = 1 for different f r are shown in Fig. 5. According to Fig. 5 and the research in [12], the stability criterion for digitally controlled grid-connected inverter with the CCF active damping can be summarized in Table 1, where the subscript (+) and (-) represent −180 • crossing in the direction of phase raising and phase falling, respectively. P is the number of the open-loop unstable poles, PM is the phase margin, GM 1 and GM 2 are respectively the gain margin at f r and f s /6, and H ilc is the boundary of H i1 when f r ∈ (0, f s /6).
According to the aforementioned analysis, it is recommended to obtain a relatively low resonance frequency, which is lower than one-sixth of the sampling frequency. However, it needs a larger volume capacitor or inductor which is not cost-effective and would cause the slow dynamic performance of the inverter owing to the influence of the weak grid. Moreover, it is noticed that the gain margin requirement for case 2 conflicts with case 4. Since f r decreases as the L g increases, the actual resonant frequency f r might be close to the critical frequency, which leads to system instability due to the inadequate gain margin. Besides, when f r = f s /6, the inverter will never be stable. Hence, the critical frequency and its vicinity can be defined as the resonance frequency forbidden region. Due to this characteristic, the robustness against grid impedance variation of the system is weakened. So, it is desirable to obtain a wider positive region of R eq and eliminate the resonance frequency forbidden region.

IV. CAPACITOR-CURRENT-FEEDBACK DAMPING WITH IMPROVED DELAY COMPENSATION METHOD A. THE IMPROVED DELAY COMPENSATION METHOD
In order to relieve the influence of the digital control delay, the phase-lead compensator G c (z) is added into the capacitor current feedback path. The expression of G c (z) is VOLUME 10, 2022  The Bode plots of G c (z) can be presented in Fig. 6. As shown, the desired 90 • can be obtained at Nyquist frequency. However, the magnitude response increases with frequency to infinite at Nyquist frequency, which may cause system instability. For explaining this, (16) can be expanded as According to (17), the phase of G c (z) can be calculated as When ω = ω s /2, the phase of 90 • can be obtained, and the magnitude response will be infinite due to  cos(0.5ω s T s /2) = 0, which is in agreement with Fig. 6. However, an ideal phase-lead compensator should only raise the phase of the system while retain the amplitude relatively unchanged. Therefore, a first-order zero-phase-shift digital low filter G low (z) = az + b + az −1 is proposed, which b = 1 − 2a should be met [35], [36]. However, G low (z) has a ''z'', which is hard realized in the digital system. Fortunately, the term ''z'' in G low (z) can be eliminated by integrating into the term ''z −1 '' in the denominator of G c (z). Substituting When ω = ω s/2 , the value of it is 1 − 4a. If 20 lg G low e jωT s ω=ω s /2 = − ∞, the digital low filter has maximum attenuation at f s /2, so a = 0.25, b = 0.5 are selected in this paper. The frequency characteristic of G low (z) with different a is shown in Fig. 7. As shown, when a = 0.25, the maximum attenuation at Nyquist frequency with zero-phase-shift is obtained. The improved phase-lead compensator expression can be written as The bode plots of G c (z) and G c (z) is shown in Fig. 6. It can be seen that the high magnitude response of G c (z) is effectively attenuated at the expense of the phase in high frequency region gradually decreased to zero. According to the expression of G c (z) , the block diagram of the improved phase-lead compensator can be presented in Fig. 8. According to (9), the discrete-domain loop gain T D (z) with G c (z) can be obtained as (21), shown at the bottom of the page.
After compensation, the virtual equivalent impedance is changed, expressed as Same as the mentioned discussion, Z eq can also be represented as a parallel connection of a resistor R eq and a reactor X eq , which can be written as where Combining (23) and (24), the frequency characteristic plot of R eq (ω) can be shown in Fig. 9. As seen, the boundary frequency of the positive equivalent resistance region after compensation can be defined as f p , which is extended from f s /6 to f s /4.

B. STABILITY ANALYSIS OF THE SYSTEM AFTER COMPENSATION
After compensation, the system stability might be changed, so it need to be further analyzed. The poles z = 0 and z = 1 in (21) are inside the unit circle and not right half-plane open-loop poles, which can be ignored here. Therefore, the characteristic equation of T D (z) can be expressed as For the simplicity of analysis, (25) can be mapped from z domain to ω domain by z = (1 + ω)/(1 − ω), resulting in T D (z) = H i2 G R (z)K PWM ω r (L 1 + L 2 + L g )z(z − 1) · 4z 2 + (z + 1) 2 ω r T s z 2 − 2 cos(ω r T s )z + 1 − (z − 1) 2 sin(ω r T s ) The Routh table of (27) can be obtained as In order to ensure the controllability of the system, f r should lower than f s /2, then ω r T s < π is obtained [37]. Since H i1 is defined higher than zero, so sin(ω r T s ) > 0 and 1 − cos(ω r T s ) > 0 can be derived. According to Routh criterion, the first row in the Routh table should retain the same sign for ensuring the system stability. So a 1 > 0, b 1 > 0 and b 2 > 0 are required. According to this requirement, H ilc1 , H ilc2 and H ilc3 can be derived, respectively. So H ilc can be defined as the minimum among them, expressed as According to (21), the Bode diagrams of T D (z) with G R (z) = 1 can be shown in Fig. 10. The −180 • crossing frequency in the direction of phase falling and rising can be respectively defined as f 1 and f 2 . As seen in Fig. 10(a), when f r ∈(0, f p ) and H i1 < H ilc , with the increases of H i1 , f 1 keeps on deviating to the left side of f r . If H i1 > H ilc , with the increases of H i1 , f 1 deviates to the left side of f r while f 2 deviates to the right side of f p . As seen in Fig. 10(b), when f r ∈(f p , f s /2), with the increases of H i1 , f 1 deviates to the left side of f p while f 2 deviates to the right side of f r . As the discussed above, f 1 is never equal with f 2 , and satisfies the characteristic, i.e.
Therefore, the improved delay compensation method can extend the boundary frequency of the positive equivalent resistance region to f s /4 and eliminate the forbidden region of the LCL filter resonance frequency. Then, the robustness against the grid impedance varying in a wide region is enhanced.

C. PARAMETER DESIGN
In order to ensure that inverter can operate stably varying with L g , the CCF coefficient and the current regulator parameters need to be reasonably designed.  Fig. 3, the open loop gain after compensation in s-domain can be given in

Derived by
Due to the capacitor filter has less impact on the loop gain at or beyond the crossover frequency f c , so the loop gain at f c can be approximately as Because f c is far great than f o , thus |G R (j2πf c )| ≈ K p can be obtained. Substituting it and T D (j2πf c ) = 1 into (32), yields 127962 VOLUME 10, 2022 T fo is the loop gain at the fundamental frequency f o , which is related to the steady state error. It can be derived as follow Substituting (33) into (34), the resonant gain of PR current controller under the constraint of T fo is presented as Since f c is much higher than f o and f i , substituting s = jωf c into (3) can obtain G R (j2πf c ) ≈ K P + 2K r ω i /j2πf c , then substituting it and s = jωf c into (31) with simplification, PM can be written as According to (36), the resonant gain of PR current controller under the restriction of PM can be derived as (37), shown at the bottom of the page.
Substituting (33) and (35) into (31), the damping coefficient under the constraint of PM can be obtained as (38), shown at the bottom of the page. As the analysis above, the loop gain at f 1 and f 2 should have enough gain margins. So, expressions can be given as According to (39) and (40), (41) and (42) can be respectively derived, i.e., (41) and (42), as shown at the bottom of the next page, where Based on the above analysis, the design procedure is shown in Fig. 11, which can be elaborated as follows 1) Specify the requirements of T fo , PM, GM 1 , GM 2 , and f c for satisfying system steady-state error, phase margin, gain margin and control bandwidth. Then K p and K r_T fo are obtained from (33) and (35), respectively. It is noticed that the selection of K r needs to be slightly larger than K r_T fo for reducing the effect of the reduction of fundamental frequency gain owing to the grid impedance variation. 2) According to (38), (41), and (42), curves of H i1 against the variation of L g can be obtained, and check if there is a selectable region that satisfies the requirements of PM, GM 1 and GM 2 vary with L g over the entire region.
If not, the specification of f c or PM is too strict, and need to be adjusted. 3) Selecting H i1 from the acceptable region and substitute into (37), and check if K r is lower than K r_PM . If it is  satisfied, the design is over. Otherwise, reduce K r and iterate the design procedure.

D. DESIGN EXAMPLE
For better verifying the effectiveness of the above parameters design procedure and the proposed delay compensation method, a design example is illustrated. Table 2 gives the main parameters of a 2kW single-phase LCL-Type gridconnected inverter.
According to the aforementioned design procedure, step 1 is to specify the desired parameter as T fo > 73dB, PM > 45 • , GM 1 > 3dB and GM 2 < 3dB. The LCL filter with resonance frequency f r = 6.5kHz is applied and the initial f c is set as 1300Hz. According to (33) and (35), K p and K r_T fo can be respectively calculated as 0.85 and 147, for reducing the impact of the weak grid on the fundamental frequency gain, K r is taken as 170.
Due to f 1 and f 2 cannot accurately obtain, so two threedimensional graphs of equation (41) can be drawn in Fig. 12.
In the three-dimensional coordinate system with L g as the x-axis, f 1 as the y-axis, and H i1 as the z-axis. Next, the common line of the three-dimensional graphs is projected onto the xoz plane. This projection is the curve of H i1 under the constraint of GM 1 with the variation of L g . In this way, the curve of H i1 under the constraint of GM 2 with the variation of L g can also be obtained. By using (38), (41) and (42), curves of H i1 varying with L g from 0 to 1.93mH constrained by PM, GM 1 and GM 2 can be obtained in Fig. 13. It can be seen that the acceptable range of H i1 ranges from 0.0118 to 0.0135, so H i1 = 0.013 is selected. Substituting H i1 into (37), the K r_PM = 189 can be calculated, and K r < K r_PM is satisfied.
With the parameters given in Table 2, the close-loop pole maps with the grid impedance variation before and after compensation are shown in Fig. 14(a) and Fig. 14(b), respectively. As shown in Fig. 14(a), the close poles will move outside the unit circle when grid impedance varies from 250µH to 1.05mH, which fall into the resonance frequency forbidden region. When the proposed delay compensation is adopted, the resonance frequency forbidden region is eliminated. So the close poles shown in Fig. 14(b) can be trapped within the unit circle, which verifies the feasibility of   the parameters design and the effectiveness of the proposed delay compensation method.
The Bode diagrams of the loop gain against L g = 250µH with and without delay compensation can be shown in Fig. 15. Before compensation, the actual resonance frequency falls into the resonance frequency region and the gain margin are respectively GM 1 = 8.21dB and GM 2 = 0.2dB, which is not stable due to the inadequate stability margin. Then, the openloop unstable poles is removed owing to the extension of the positive equivalent resistance region. So, just one −180 • crossing exists, and corresponding gain margin is GM 1 = 4.76dB. In Fig.15, the f c = 1300Hz and PM = 45 • are clearly  identified. Therefore, the control system has a good control performance after compensation.

V. EXPERIMENTAL RESULTS
To confirm the effectiveness of the proposed method, a 2-kW experimental set up is constructed, which is shown in Fig.16. The main parameters are given in Table 2 and the controller is implemented in a TI TMS320C28346 DSP. Furthermore, the grid impedance L g is emulated by an external inductor.
In order to make a straightforward comparison, the experimental waveform is altered from one method to another one. The experimental waveforms when altering from G c (z) to G c (z) is shown in Fig. 17. As shown, the grid-side current is significantly distorted due to the noise amplification while the current is stable when alternation is occurred, which is agree with Fig. 7. The noise amplification is effectively reduced when the digital low filter is added. Furthermore, Fig. 18 presents the experimental results when altering from the proposed method to the conventional CCF damping method against different grid impedance, in which v PCC presents the PCC voltage and i g presents the grid-side current. As seen, when L g = 0, the inverter remains stable with either the proposed method or the conventional CCF damping method. However, when the damping method altering from the proposed method to the conventional CCF damping method under L g = 250µH or 1.05mH, which f r falls into the resonance frequency forbidden region. The grid-side current and the PCC voltage arise significantly oscillation and further trigger protection. Moreover, when L g = 1.93mH, the actual resonance frequency is away from the resonance frequency forbidden region. So, the inverter is constantly stable. The experimental results are consistent with the analysis given in Section IV. Thus, it is meaning that the proposed delay compensation method can improve the LCL-Type grid-connected inverter robustness against the grid impedance variation and significantly relieve the noise amplification.
For verifying the feasibility of the parameters design procedure given in Section IV. The experimental results with the proposed method when the grid current reference i ref step between half-and full-load against different grid impedance is shown in Fig. 19. To exhibit the worst situation, the step action is occurred at the peak of i g . As seen, the inverter features good dynamic performance and stability with the grid impedance varies from 0 to 1.93mH. The experimental results demonstrate that the parameters design procedure is valid.

VI. CONCLUSION
Owing to the digital control delay effect, the LCL-Type grid-connected inverter with the CCF active damping is apt to be unstable when the grid impedance varies in a wide range. To address this issue, this paper proposes an improved delay compensation method which is inserting a phase-lead compensator with a digital low-pass filter into the CCF path. Accordingly, the boundary frequency of the positive equivalent resistance region is boosted from f s /6 to f s /4 and the resonance frequency forbidden region is completely eliminated, which the inverter robustness against the grid impedance variation is enhanced. Moreover, the improved phase-lead compensator provides both substantial phase compensation and does not introduce excessive amplitude gain in the high frequency domain, which relieves the noise amplification. For obtaining good control performance of the inverter, a parameters design procedure is further presented. Finally, a 2kW prototype is built and the experimental results verify the validity of the theoretical analysis and the proposed method.