Explicit Impedance Modeling and Shaping of Grid-Connected Converters via an Enhanced PLL for Stabilizing the Weak Grid Connection

The voltage source converters (VSCs) are used to interface and control the renewable energy resources that are integrated into the power grids. However, a weak grid connection raises a stability problem for grid synchronization of the grid-feeding current-controlled VSCs (CCVSCs). This paper handles modeling and controller design for stabilizing the weak grid connection of CCVSCs. The impedance modeling/shaping of the VSC has been recognized as an effective tool to analyze and design the dynamics of the VSC. But an explicit and accurate impedance model of the CCVSC is required. Particularly, modeling the impact of the phase-locked loop (PLL) synchronization unit on the impedance model of the CCVSC is complex. Therefore, at first, an efficient impedance model of the CCVSC is developed while the impact of the PLL is rigorously considered through a complex procedure that results in an explicit/accurate impedance model. The developed impedance model is used to conduct passivity/weak grid connection stability analysis to clarify the underlying causes of instability problems. Then, a novel PLL, with an in-loop low-pass filter (LPF) to account for harmonics/asymmetries, is proposed with enhanced characteristics using the state feedback control. The impedance shaping method (with the aid of the impedance model) is utilized to design the state feedback gains. The state feedback loops provide degrees of freedom for bandwidth design of the PLL considering the current/power control loops and stabilize the system under weak grid connection/distorted conditions. Simulation results prove the accuracy and effectiveness of the models.


I. INTRODUCTION
The inverter-interfaced distributed energy resources (DERs) are connected to the power grids through voltage source converters (VSCs). The non-dispatchable DERs, like renewable energy resources, operate in the grid-feeding mode and thus the current-controlled VSCs (CCVSCs) are used to control them in PQ mode [1]. However, the weak grid connection, i.e., the grid with high impedance and low short circuit ratio The associate editor coordinating the review of this manuscript and approving it for publication was Mouloud Denai .
(SCR), e.g., SCR < 3 in Australia [2], may result in voltage instability of the phase-locked loop (PLL) synchronized CCVSCs [3]. To analyze and stabilize the weak grid connection, appropriate modeling and controller design of CCVSCs are required.
From the modeling perspective, among different techniques, impedance modeling and shaping of the VSCs is probably the most popular one [4]. The reason is that, when it comes to modeling an electric system using transfer functions/matrices with respect to its inputs/outputs, the impedance/admittance characteristics describe the system dynamics [5]. In conventional power systems, the impedance of the synchronous machines and power networks are known and dominantly inductive. In the grid with the dominant inductive impedance, active power flow can be controlled by controlling the frequency, which dynamically controls the phase angle, and reactive power can be controlled by controlling the voltage magnitude. This is compatible with the f − P droop characteristics and automatic voltage regulator (AVR) mechanism in the synchronous generators, and this consistency between generation units and transmission networks provides the harmony required for the stable operation of power systems [6]. However, from the VSC's perspective, their arbitrary impedance, affected by the controller and parameters [7], affects their performance in the grid and demands more investigations. Developing the impedance model of the grid-forming (voltage-controlled) VSCs is to evaluate the compatibility of the output impedance with some droop rules [8], [9].
On the other hand, the passivity analysis is a concern in the admittance modeling of the grid-feeding CCVSCs [10], [11]. However, modeling the impact of the PLL on the impedance characteristics of the CCVSC is complex. The PLL detects the phase angle of the grid, and since the sensitivity of the active and reactive power to the phase angle is high (V 2 Z ) [12], the performance of the PLL critically affects the performance of the CCVSC. Harnefors et al. [13] developed a procedure to model the impact of the PLL on the impedance characteristics of the grid-connected converter, which has been used by others [14], [15], [16], [17], after applying minor changes depending on the modifications in the PLL design. However, the main problem is the complexity of the model since the input admittance is developed as transfer matrices with multiple-input multiple-output (MIMO) representation, which makes the design and stability analysis complicated. A symmetrical PLL has been proposed in [18], to eliminate asymmetric dynamics of the PLL and thus convert the MIMO model to a single-input single-output (SISO) model. However, an asymmetric effect may be due to inappropriate modeling of the PLL impact [19], [20].
In the context of the weak grid connection [21], [22] as an indicator of the grid strength and hosting capacity of the grid [23], the PLL self-synchronization loop (provoked by the grid impedance) has been identified as the source of instability [24]. Also, the impedance model of the CCVSC reveals a negative incremental resistance affected by the PLL [25]. In this light, the impedance characteristics of the CCVSC can be designed to preserve the stability of the system [26]. For example, virtual impedance [27], [28] and active damping [29] methods are proposed.
From the PLL perspective, due to the crucial impact of the PLL and the consequence complexity associated with PLL modeling, the literature can be categorized as PLL-free and PLL-based control strategies [30]. The control loop of the converter has been changed in [31] and [32] to eliminate the PLL requirement and to provide voltage support. However, this inversely affects the dynamic performance of the converter for reference tracking. Besides, replacing a dedicated PLL with a synchronization signal (by filtering the node voltage) [33], [34], known as direct power control, leads to real and reactive power coupling and steady-state error, if the impedance of the CCVSC is not well-shaped following the grid impedance [9], [35]. Further, the weak grid instability issue exists in the direct power control method and the PLL-based CCVSC is still the preferred choice [30].
Therefore, the PLL-based stabilizing methods have gained more attention and a robust PLL has been proposed [36]. The PLL-embedded virtual impedance is proposed in [37], which affects the accuracy of the PLL in phase estimation and power delivery. Alternatively, PLL-based active damping has been studied in [38] to stabilize the weak grid connection of VSCs, which reveals the crucial importance/impact of the PLL for impedance shaping and stabilizing the weak grid connection of CCVSCs. The PLL design has been improved in [39] to eliminate the negative influence of the PLL on the current controller. The PLL-based loop shaping has been proposed in [40] by only focusing on the influence of the reactive power control loop and thus robustness of the method is questionable. The compensated PLL based on the grid impedance is proposed in [41], which needs extra effort for measuring the grid impedance. However, manipulating the estimated phase angle by the PLL impacts the effectiveness of the method.
Along with the weak-grid connection issue, the poor performance of the PLL in distorted grid conditions is an extra concern. To address this problem in the relevant literature, sequence extraction and prefiltering loop are adopted before the synchronization unit to account for asymmetries and harmonics. Recently, prefiltered synchronization has been studied in the context of weak grid connection [42], [43], [44], where prefiltering loops are adopted to modify the bandwidth of the PLL. Prefiltering results in more complex PLL synchronization units, see [45] and references therein, where the common feature among them is adding a low-pass filtering effect to the normal PLL dynamics. But this makes the stability analysis complicated, particularly using MIMO impedance models [44], where the low-pass filtering effect is against the stability margin of the system, which is analyzed in this work.
Despite the extensive efforts done in the field, developing an effective PLL that simultaneously 1) ensures the simplicity of the CCVSC controller; 2) provides a sufficient degree of freedom for bandwidth design to stabilize weak grid connection; 3) stabilizes the converter while suppressing harmonics distortions in the estimated phase angle, is felt as the gap. This is an important issue from the practical point of view as industry practitioners always look for simple and effective solutions. Further, developing an explicit impedance model is a prerequisite for developing such a simple and effective PLL. To address the mentioned issues, in this paper, we consider stabilizing a weak grid-connected CCVSC using an impedance shaping method, and an enhanced PLL is proposed to realize the impedance shaping. The contributions of the paper are as follows: 1) An explicit impedance model of the CCVSC is developed. The impact of the PLL synchronization unit on the CCVSC impedance characteristics is mathematically modeled through a rigorous modeling procedure, that although complex by itself, results in an explicit impedance model. We model and superimpose synchronization, disturbance rejection, and reference tracking factors to develop the impedance model. 2) The developed impedance model possesses two key advantages: a) the modeling procedure of the synchronization impact is irrespective of the PLL model and the current controller of the CCVSC. Therefore, the model can be applied to model the impact of PLL on any CCVSC with different types of filters and controllers; b) the developed impedance model explicitly reveals the PLL impact on the impedance characteristics of the CCVSC. Thanks to the proposed modeling procedure, the MIMO model of the CCVSC is converted to a SISO model without costing the accuracy of the model. It significantly helps to simplify the stability analysis and design of the controllers.
3) The developed impedance model is used for three purposes a) to conduct the passivity analysis, by which the stable bandwidth of the PLL with an in-loop lowpass filter (LPF) (to deal with distorted/asymmetric conditions) is determined; b) to carry out the weak grid connection stability analysis; c) to derive the open-loop transfer function of the weak grid-connected VSC to be used in the synthesis of impedance shaping using the Nyquist stability criterion. 4) A novel enhanced PLL model is proposed for improving system dynamics and stabilizing the weak grid connection. The enhanced PLL is designed based on state feedback control and feedback gain adjustment provides sufficient degrees of freedom for impedance shaping (i.e., bandwidth design) to stabilize the system. The enhanced PLL is robust to a system under harmonic distortions, weak grid connection, and increments of the negative damping in the CCVSC.
The rest of this paper is organized as follows: Section II develops an impedance model of the CCVSC. Section III studies the PLL impact on impedance characteristics of the CCVSC by superimposing the PLL performance. Passivity and weak-grid stability issues are investigated in Section VI and Section V, followed by an enhanced PLL, which is proposed in Section VI. In Section VII numerical and simulation results prove the effectiveness and accuracy of the models, while Section VIII concludes the paper.

II. IMPEDANCE MODELING OF CCVSC
A block diagram of the CCVSC is shown in Fig. 1, where the control loop, in the d − q frame, consists of the PLL and a proportional-plus-integrator (PI)-based current controller to regulate the output current (i od and i oq ). The reference values of the output current, i.e., i odref and i oqref , are determined by the energy management system, which determines P ref and Q ref , and it is given from: where v d is the d-term of the grid voltage at the point of common coupling (PCC), which is extracted by the PLL. The mathematical models governing the electrical circuit and control loop of the CCVSC (in the s-domain) are given as follows. On the control side, i fdref and i fqref are the dq-references for the inductor current of the LC filter and are given after incorporating the LC filter capacitor current into i odref and i oqref (through the first/left block in Fig. 1).
where v d and v q denote the voltage at the PCC, ω 0 is the nominal angular frequency, C f represents the capacitance of the LC filter, and s is the Laplace variable. The PI-based current controller is modeled as: where k Pc and k Ic are the proportional and integrator gains, respectively, i fd and i fq imply LC filter inductor current, v id and v iq are the input voltage to the power converter and L f represents the inductance of the LC filter inductor. On the electrical side, the LC filter current i f is given by Kirchhoff's current law (KCL) as Applying Kirchhoff's voltage law (KVL) to the LC filter yields where R f is the equivalent resistance of the LC filter inductor. By plugging (2)-(4) into (5) and reordering the equation to derive i o as function of i oref and v yields where The CCVSC parameters are designed, given in Table 1, to achieve fast current regulation. Fig. 3 shows the frequency response of (6) by representing the current regulation transfer  Table. 1: G (s) = 1 0 at low frequencies, function G (s) = 1 0 and the transfer matrix entries Y s = jωC f ( Y s = 90 • ) and Y m ≈ 0 characterizing the CCVSC admittance. Noting that we aim to make the coupling term (complex term) be zero (Y m ≈ 0), thus in the natural frame (6) VOLUME 10, 2022 it is given as:

III. THE PLL MODEL AND IMPACT
In the synchronous reference frame (SRF)-PLL, the phase angle is obtained by which the q-term of the input signal is zero. In this regard, the phase detector unit extracts the q-term of the voltage (v q ). Since v q gives information about the phase estimation error, we normalize it by dividing it by the nominal voltage magnitude |V | to improve the PLL performance. Also, for improving the PLL robustness in polluted grids and distorted conditions, we use an in-loop LPF [45]. Further passivity analysis and weak grid stability analysis are used to enhance the PLL performance to stabilize the system and achieve the desired dynamic stability/performance. To this end, the CCVSC impedance model including the PLL is needed.
To analyze the PLL impact on the impedance characteristics of the CCVSC, the PLL performance in the control system of CCVSC can be considered in three different tasks: 1) synchronization by estimating the voltage magnitude and phase angle of the grid voltage, 2) extracting the dq−terms of the output current for disturbance rejection, and 3) converting the dq−error (between reference values of current and output current) back to the natural reference frame for reference tracking. Then the impedance characteristics of the CCVSC can be obtained by superimposing the models of the three parts.

A. SYNCHRONIZATION
The SRF-PLL extracts the voltage magnitude (v d ), frequency and phase angle by forcing the q-term of the voltage (v q ) to zero through the loop filter, i.e., a PI controller, see Fig. 2(a). To this end, the q-term is achieved by the phase detection unit through the process given as follows: where v abc = V cos (ϕ) cos ϕ − 2π 3 cos ϕ + 2π 3 ; ϕ = ω 0 t + θ, is the 3-phase voltage with the nominal voltage magnitude V , argument ϕ, nominal angular frequency ω 0 , and phase angle θ. T αβ = 1 is the Clark transformation matrix that converts the abc natural reference frame to the αβ stationary coordinates. In the quasilocked condition, where the estimated frequencyω = ω 0 , we have [45]: where T dq = cos φ sin φ − sin φ cos φ , andφ andθ are the extracted argument and phase angle by the PLL. By mathematically expanding the trigonometry terms in (9) and henceforth assuming cos θ ≈ 1 and sin θ ≈ θ, since the phase angle is very small, v dq can be estimated as The small-signal model of the SRF-PLL can be drawn as shown in Fig. 2 where G PLL (s) is the transfer function of the PLL given from Fig. 2(b). Based on (9) and (11), in the quasi-locked condition (ω = ω 0 ), the effective T dq is: Plugging (11) Given the perturbation of the PCC voltage v abc : then And using (12), the dq-terms are given as: The PLL output does not change immediately but it changes based in its bandwidth (time constant). Therefore, at the onset of perturbations, we have v dq ≈ v dq due to the PLL time constant. So, plugging (13) into (16) yields that gives rise to the following equations Obtaining the V from (18) and replacing it in (19) results in Plugging (20) into (13) And then updating (6) by (21) yields So, we have: where Also, (12) can be updated by (20) as:

B. DISTURBANCE REJECTION
The dynamics of the CCVSC output current (i o,dq ), which follows the reference values i o,dqref , is obtained as (based on (13) and (20)) upon a disturbance perturbs the output current, i.e., where θ is the phase angle variation of current. With the same process given in (14)- (15) for the voltage, we have Then using (20), (24), and (26) the dq−terms of the currents are obtained as: Plugging (25) into (28) results in: VOLUME 10, 2022 Now, to analyze disturbance rejection performance, i.e., system dynamics for establishing i o,dq = i o,dqref , let's rewrite the CCVSC model in (23) noting that G (s) = 10: In the steady state whereθ ≈ θ and i o = I o θ Since i o,dq follows the reference values i o,dqref , we can write: So, plugging (27) and (32) into (30) results in: Now plugging (29) into (33) gives rise to:    From (36) and (23) the input admittance of the CCVSC (as a passive element in the natural reference frame) is updated as Y pass (s): C. REFERENCE TRACKING Assume the system is at a steady state (i o,dq = i o,dqref ) upon there is a change in the reference values of current as i odqref , then the impedance characteristics of the CCVSC in (23) can be rewritten as: Since i o,dq = i o,dqref and G (s) = 10, (38) is updated as: The i odqref is converted from dq to αβ frame using T −1 dq : So, we have: The CCVSC current i o = I o θ = I o jI o is updated as: Then returning to the dq−frame for the current control loop: which means the error is removed, and the reference tracking loop does not impact the impedance model unless it changes the voltage, which is modeled by the synchronization task. Hence from (37) the output impedance of the CCVSC can be characterized as: where The impacts of the outer (AC/DC) voltage and power control loops on the impedance model can be incorporated into the developed model by modifying the i odref i oqref T based on the dynamics of the DC/AC link/bus and the associated (PI) controllers. However, we neglect their impact here since if the bandwidths of the outer PI controllers are appropriately modeled (to be lower than those of PLL and the current controller) their effect is negligible in the bandwidth of interest for weak grid instability analysis. Notice, here we seek to develop an explicit/accurate model of the PLL impact on the CCVSC impedance and to identify the underlying cause of weak grid instability to propose an effective solution.
It is shown in this paper that the CCVSC model, with appropriate modeling of the PLL impact and without modeling outer control loops, can identify the weak grid instability, which is due to the interaction of the current control loop and the PLL. Also, the bandwidth of the current regulation loop (i.e., the PI controller of the current loop) should be relatively higher than that of the PLL to decouple their operation, as we considered in (38)-(39) by taking G (s) = 1 0 at low frequencies for reference tracking. Otherwise, they may interfere, which impacts the performance of the CCVSC.

IV. PASSIVITY ANALYSIS
The passivity-based stability analysis reveals that the system is stable for the non-negative real part of the input inductance (conductance) at all frequencies [10]. To investigate this issue let us develop real and imaginary parts of the Y pass (jω) in (37).
Realizing the real and imaginary (conductance and susceptance) terms of Y pass (jω) results in: To preserve the stability of the CCVSC, Y pass Real should always be positive which, means X PLL must be negative, i.e., X PLL < 0. Let us develop the real and imaginary terms of the basic PLL in Fig. 2(b) without including the LPF: (51) X PLL is negative regardless of the PI gains, which means CCVSC is stable when a basic PLL is adopted as the synchronization unit. However, the voltage waveform is distorted by the existence of harmonics that affects the PLL performance. Hence, an LPF is adopted for noise rejection to improve the PLL performance. Besides, some advanced PLLs with pre-filtering techniques to extract fundamental VOLUME 10, 2022 frequency (at harmonics and unbalanced conditions) such as multiple reference frame PLL (MRF-PLL) and notch filter, can be modeled as an LPF and have exogenous disturbances [45]. Although studies have obtained a satisfactory compromise between disturbance rejection and quality in designing the cut-off frequency of LPF, the impact of the LPF on the PLL dynamics and stability of CCVSC has been overlooked. To this end, let us develop the real and imaginary parts of the PLL with an in-loop LPF in Fig. 2(b).
Since X PLL < 0, then to secure the stability of the CCVSC.

V. WEAK GRID CONNECTION
In a weak grid connection where the grid impedance is high, the voltage at the PCC fluctuates due to the performance of the current control loop and the PLL dynamics. The reason is that the CCVSC is designed for (power) reference tracking purposes with fast dynamics response. Therefore, in contrast to the grid-forming VSCs, the CCVSC lacks the capability of voltage regulation. Also, the CCVSCs do not have physical inertia and damping factors and thus there is not sufficient damping to suppress the voltage oscillations.
To investigate the voltage instability issue of the weak grid connection, the impedance model of the CCVSC can be used. The electrical circuit model of the CCVSC connected to a weak-grid (V G ) with high impedance (Z G ) through a feeder, with an impedance Z f as depicted in Fig. 4(a)-(b).
From Fig. 4(a) and utilizing circuit analysis tools, i.e., Kirchhoff's voltage and current laws (KVL and KCL), it follows that: From (57)-(59) the block diagram representing the small-signal model of the system is shown in Fig. 4(c).  After simplifying the block diagram, the impedance characteristic of the CCVSC in (56) is modified as: Notice that G (s) = 1 0 for the open-loop transfer function G ol is achieved as: (61) The G ol provides the Z in Z out impedance ratio which is commonly adopted to investigate the stability of the system through the Nyquist stability criterion. The grid-connected admittance is obtained as: (62)

VI. PROPOSED ENHANCED PLL
Impedance shaping is considered a promising solution to address the stability issues of inverter-based power systems [6], [9], [46]. In the case of the weak gridconnected CCVSC system, the impedance characteristics of the CCVSC, i.e., Y (s) , can be adjusted to satisfy the Nyquist criterion in (61). Referring to Y (s) the capacitance of the LC filter and the PLL dynamics are the only elements to be modified for impedance shaping, which gives limited flexibility to be redesigned. Because the PLL, with an in-loop LPF for harmonics rejection, demands a secured bandwidth, which is verified by passivity analysis to be stable. Besides, the bandwidth of the PLL should be high for disturbance rejection while the loop gain must be low for noise rejection. To this end, the enhanced PLL model, as shown in Fig. 5, is proposed, which is developed based on state feedback control. The feedback loops facilitate both impedance shaping and the desired dynamic performance (bandwidth design) to be simultaneously satisfied. To this end, we select the feedback gains based on impedance shaping so that the open-loop transfer function (61) satisfies the Nyquist stability criterion. Also, the grid-connected admittance (62) must satisfy the passivity requirement.

A. DESIGNING THE ADVANCED PLL BASED ON IMPEDANCE SHAPING
The frequency response of the open-loop transfer function G ol is represented in Fig. 6, for the grid parameters given in Table 2. The Nyquist frequency response shows the very weak grid-connected CCVSC (SCR ≈ 1) with normal PLL (K P = 8 and K I = 100) is unstable, see Fig. 6(a). Also, the grid-connected admittance does not satisfy the passivity requirement as shown in Fig. 7. For the enhanced PLL, we select ω f = 100 as per the design-oriented study presented in [45]. We can select a large value for K I = 5000 to yield a high bandwidth (this is against the stability of the weak grid condition), and a small value for K P = 8 for noise rejection (this is against the passivity analysis). Nevertheless, the state feedback loops help to provide sufficient damping to the system and a degree of freedom for impedance shaping. To realize impedance shaping the feedback gains are adjusted as k ψ = 5.3 and k ω = 0.15 so that the open-loop transfer function G ol (s) satisfies the Nyquist stability criterion as depicted in Fig. 6(b). Also, the grid-connected admittance satisfies the passivity requirement as shown in Fig. 7. This shows that (which also will be verified by simulation results)   although choosing a small loop gain, for increasing the noise immunity of the enhanced PLL, is against the passivity analysis, the enhanced PLL is stable thanks to the state feedback loops.

VII. SIMULATION RESULTS
To evaluate the accuracy and effectiveness of the proposed methodology and models, the CCVSC shown in Fig. 1 is simulated in the Matlab/Simulink platform using the Simscape toolbox. A non-linear time-domain Simulink model is developed within which nonlinear characteristics of the grid-connected CCVSC, such as the switching process and electromagnetic transients of the electric parts, are modeled to produce accurate and reliable results. The electrical and control parameters given in Table 1 are used for the Simulink model.  Fig. 1: (a) frequency when k I < ω F K P (stable); (b) frequency when k I > ω F K P (unstable); (c) frequency, k I = ω F K P (resonant); (d) CCVSC's output current which is unstable for k I > ω F K P .

A. PASSIVITY ANALYSIS OF THE CCVSC BY PLL WITH IN-LOOP LPF
An in-loop LPF is adopted to improve the PLL performance in distorted grid conditions. The passivity analysis, using the impedance model of the CCVCS controlled by a PLL with an in-loop LPF was conducted in Section IV to evaluate the impact of the in-loop LPF on the dynamic stability of the system. This issue is illustrated in Figs. 8 and 9, through the frequency responses and simulation results. Notice, in this case, the grid impedance is considered to be low and thus only the impact of the PLL is investigated. The parameters in Table 1 are adopted for the PLL with in-loop LPF while k P is changed to achieve the test requirements. When (55) is satisfied, i.e., X PLL < 0, the real part of Y is positive and the system is stable as depicted in Fig. 8 and Fig. 9(a). However, when X PLL > 0 the system is unstable, see Figs. 8 and 9(b), and k I = ω f k P makes the X PLL = 0 and thus Y Real = 0, which leads to a resonance, see Figs. 8 and 9(c). This verifies the accuracy of the developed impedance model.

B. DISTORTED GRID CONDITION
The performances of the normal PLL, PLL with in-loop LPF, and the proposed enhanced PLL with the state feedback loop are compared for distorted/asymmetric grid conditions, see Fig. 10. The voltage waveform is distorted by an unbalanced load at t = 0 ∼ 1 s, see Fig. 10(a). Fig. 10(b)-(c) shows the extracted q-term of the voltage by different PLLs, which gives information about phase estimation error by PLLs. The fluctuations having twice the fundamental frequency can be seen at t = 0 ∼ 1 s in Fig. 10(b)-(c). The harmonic load (a 3-phase diode rectifier with 1 mH + 25 ||50 µF as DC load) is added at t = 1 s, which makes the voltage waveform highly distorted, see Fig 10(a) and (b)-(c). An inloop LPF helps to filter 2nd (due to unbalanced load) and high-frequency oscillations, but it induces low-frequency oscillations that affect the PLL performance, see Fig. 10(b)-(c). The proposed enhanced PLL significantly suppresses the oscillations without affecting the PLL performance, see Fig. 10(b)-(c). The performance of the PLLs in frequency estimation is illustrated in Fig. 10(d) and the proposed PLL reveals superior performance in the frequency estimation.

C. WEAK GRID CONNECTION
A weak grid can be identified by its low SCR affected by the voltage level (V ), grid impedance (Z G ) and the power rating of the converter (P VSC ): To realize the weak grid condition, the voltage and converter ratings in Table 1, and the feeder and grid impedance in Table 2 are used. Nevertheless, the other factor that may affect the stability of the CCVSC is the X/R ratio of the grid impedance. The weak grid instability issue has arisen in high power rating applications due to the high X/R ratio seen by the converter. In low-power rating applications, which are most likely located in low-voltage grids, the damping factor given by resistive feeders/cables helps to dampen the oscillations. However, the low-voltage grids are more distorted due to non-linear loads. And using PLL with in-loop filtering limits the stability margin of the CCVSC. Therefore, without loss of generality, we consider a low-rating converter connected to a grid with a low X/R ratio.
Simulation results for the weak grid-connected CCVSC are shown in Fig. 11 and Fig. 12. Here a balanced condition is considered to focus on the weak grid connection instability. Fig. 11 indicates the system is unstable, which is consistent with the Nyquist stability criterion represented by Fig. 6(a). This proves the accuracy of the impedance model and the open-loop transfer function of the system. Both normal PLL and PLL with in-loop LPF fail to stabilize the system. The active and reactive power, delivered by the CCVSC, are highly fluctuating, see Fig. 11 This is because there is a fluctuation in the phase error signal, see Fig. 11(c). The reason is that in the weak grid connection, where the inductance of the grid is high, the current controller of the converter increases the phase angle of its end (and dynamically the frequency) to deliver the reference active power (50 kW). Meanwhile, the PLL  estimates the phase angle, which is changing due to the current controller performance. This leads to estimation errors in the PLL. On the other hand, the current regulation loop seeks to remove the current error using the false information, given by the PLL, and thus changes the phase angle. This puts the system into a circulating loop that makes the system unstable as the CCVSC is unable to stabilize its VOLUME 10, 2022  voltage synchronized with the grid. Since the loop filter (i.e., the PI controller) cannot remove the phase estimation error, which is continuously fluctuating, the estimated frequency is continuously rising, see Fig. 11(d).
The simulation results, shown in Fig. 12, confirm the effectiveness of the proposed method for stabilizing the weak grid-connected CCVSC system through the enhanced PLL. It is aligned with the Nyquist stability criterion given in Fig. 6(b), and the passivity of the grid-connected admittance in Fig. 7, thanks to the accuracy of the developed impedance model.

D. DISCUSSION
As per the simulation results, the developed impedance model is accurate to identify the instability and is effective to stabilize the system. It was shown that the interaction of the current control loop of the CCVSC (for adjusting the phase angle) and the PLL (for detecting the phase error and synchronization) leads to instability of the weak grid-connected CCVSC. This makes the system unstable if the reference active power and the grid impedance are relatively high. Assigning a low bandwidth for PLL to decouple its performance with the current control loop, is against the disturbance rejection performance and interferes with outer DC/AC voltage controllers. Besides, it does not guarantee the robustness of the system. The proposed method and the enhanced PLL stabilize the system because 1) the state feedback loops provide sufficient damping to suppress oscillations in the phase estimation process in the PLL; 2) the state feedback loop decouples the bandwidth of the enhanced PLL and the current control loop, while it preserves the disturbance rejection and noise immunity performances.
The bandwidth of the enhanced PLL is affected by the state feedback loops and the PLL response is slowed down after the compensation. Nevertheless, a higher bandwidth can be selected for the loop filter (i.e., the PI controller), which can increase the bandwidth of the enhanced PLL to an acceptable range for a distorted and weak grid condition. The difference is that the feedback loops provide damping to suppress the oscillations. Fig. 13 shows and compares the bandwidth of the enhanced PLL with the basic PLL and the PLL with in-loop LPF.
The proposed impedance shaping method for selecting the feedback gains depends on the assumption that the grid impedance is known. However, the grid impedance may change so the robustness of the proposed enhanced PLL in response to uncertain grid parameters is questionable. To address this issue, a worst-case scenario can be considered for impedance shaping. The alternative solution can be adaptive impedance shaping in response to the variations of the grid impedance. To this end, the grid impedance can be measured through a real-time impedance measurement scheme, based on which the feedback gains are changed to realize adaptive impedance shaping. This demands further investigations for proposing a real-time state feedback gain design that can extend this work.

VIII. CONCLUSION
In this paper, the weak grid stability problem of the PLL-synchronized CCVSCs was investigated and a simple and effective solution was proposed. However, targeting and designing a simple and effective controller is not easy as a rigorous mathematical procedure/modeling is needed to preserve the accuracy and effectiveness of the method.
To have an effective/reliable tool to carry out the dynamic stability analysis and control design, an accurate and explicit impedance model of the CCVSCs was developed considering the PLL impact. The correctness of the impedance model was verified under passivity and weak grid connection analysis where the model was successfully used to identify unstable boundaries. With the aid of the developed impedance model, the open-loop transfer function of the weak grid-connected CCVSC system was derived to investigate the stability margin of the system through the Nyquist stability criterion.
To realize a secured bandwidth for the PLL that satisfies different requirements such as working under a weak grid connection and distorted grid conditions, an enhanced PLL was proposed. The proposed PLL was developed based on the state feedback control and the feedback gains were determined through the impedance shaping methodology and using the developed open-loop transfer function. The feedback loops suppress the oscillations and decouple the operations of the PLL and the current controller to stabilize the weak grid connection while revealing appropriate performance in disturbance rejection and distorted grid conditions. The modeling and stability analysis of the CCVSCs should be modified for large-signal events, such as fault ride-through transients where the system characteristics change. Developing the transient impedance model of the CCVSC and checking the boundedness of system trajectories under fault-ride through transients is left as the authors' future work.