High-Performance Buck-Boost Partial Power Quasi-Z-Source Series Resonance Converter

The converter efficiency defines the overall efficiency of a renewable energy system. In a full power converter, its components process the whole input power, even if it is not mandatory. Partial power processing (PPP) is an exciting concept for improving overall system efficiency and reducing system cost and size. In PPP, the converter processes the amount of power needed to be processed. This work proposes a PPP based on the high-performance Quasi-Z-Source Series Resonance converter (QZSSRC). The proposed partial power converter has a series-input parallel-output (SIPO) architecture. Previous publications in this area mainly consider converters with step-down voltage regulation, like the phase-shifted full-bridge converter. They underperform in this application due to operating at the maximum power when bucking the voltage the most. This paper studies two other types of dc-dc converters, buck-boost and boost, in SIPO partial power converters. Theoretical operation principles are corroborated with full experimental results given and analyzed. A 300 W prototype of the QZSSRC is used to convert the power of up to 2 kW in a PPP system with overall system efficiency over 99%.


I. INTRODUCTION
The significant developments in semiconductor devices, like replacing Si with SiC and GaN, led to considerable advances in power electronics circuits and systems architectures [1], [2], [3], [4]. Power electronic converter efficiency is an essential parameter influencing the suitability of a particular converter to a given application. Nowadays, many power converters have shown very high efficiency. The best-in-class examples reach 99% in some applications [5].
The new concept of partial power processing (PPP) has provided this very high efficiency [6], [7], [8], [9], [10], [11], [12], [13]. This concept is built based on the fact that The associate editor coordinating the review of this manuscript and approving it for publication was Bidyadhar Subudhi . the PPP converter processes a fraction of the system power required for load regulation or other functions based on system requirements [14], [15], [16], [17]. Distinct features of PPP, like high efficiency and reduced power rating of components, make it attractive in many applications such as photovoltaic systems, electric vehicle (EV) charging, electrolyzer cell (EC) and fuel cell (FC) chargers, battery storage systems, LED drivers, and wind power systems [18], [19], [20], [21], [22], [23], [24]. The first appearance of the PPP concept was in aerospace applications, where a PV array was used to charge the space system battery. PPP solutions increase the efficiency and power density of the system, plus adding redundancy [25].
Another application of the PPP concept was reported in [26], where the converter was charging a flying capacitor VOLUME 10, 2022 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ in both polarities. This enables the converter to provide different voltage levels at the input and output flexibly. The fast charging stations are another promising applications for the PPP concept, where the system could be rated at more than 350 kW [27]. PPP would decrease installation and maintenance costs. The difference between the power flow in full power processing (FPP) and PPP converters is illustrated in Figure.1. As can be seen from Figure.1(a), the FPP requires a dc-dc converter to carry the full power of the system. Hence, the converter components are dimensioned to handle 100% of the system power, which causes power loss and high system costs. On the other hand, as seen in Figure.1(b), the PPP configuration required a dc-dc converter that processes only a fraction of the power flowing from the source to the load. This way, the losses generated by the power converter and its size are reduced. Furthermore, by maintaining the same efficiency for the power converter, the global efficiency of the system increases [29]. Equations (1) and (2) describe how the efficiency of a dc-dc converter cell affects the system efficiency differently, depending on whether it is based on FPP or PPP.
where, η FPC , η dc−dc , η PPC , P O , P in , and Kpr are the full power converter efficiency, dc-dc converter efficiency in a partial power converter (PPC), PPC efficiency, output power, input power, and processed power ratio (partiality coefficient), respectively. Different configurations have been reported in the literature for the PPP. However, in general, it can be classified into parallel current regulators (PCRs) and series voltage regulators (SVRs), series connected partial power converters (S-PPCs) [30]. S-PPC is a series regulator that regulates the voltage difference between input and output voltages [31], [32].
S-PPC is defined according to input and output connection into the series input parallel output (SIPO), which is more suitable for voltage step-down applications, and the parallel input series output (PISO), which is more convenient for voltage step-up applications, as shown in Figure.2. Partial power converters based on PISO configuration have been extensively researched in recent years. They show high performance in voltage step-up applications, while SIPO PPCs have not shown comparable performance in voltage step-down applications [33]. One of the root causes of the observed relatively low performance of the SIPO PPCs is the application of inherent voltage backing topologies like phase-shifted full-bridge converters. These topologies are complicated to design for this application, as their transformer should have a high turns ratio to match the minimum requirement for series voltage between the input and output. At the same time, they should handle the highest power (highest K pr ) at the lower dc gain, i.,e., when bucking the input voltage the most.
This work aims to consider alternative implementations of the SIPO PPCs that are expected to provide better performance, namely, using buck-boost and boost dc-dc topologies. The high-performance buck-boost quasi-Z-source series resonant (QZSSR) converter was selected for this study as it can be implemented as buck-boost or as a boost dc-dc converter, depending on the transformer turns ratio while keeping all the other converter components unchanged. The second section presents the basic requirements and operation principles of PPCs. The third section describes the operation principle of the case study converter, while tis design is covered in the fourth section. The experimental results are provided in the fifth section. The conclusions are drawn in the sixth section.

A. REQUIREMENT OF GALVANIC ISOLATION
Isolation is a critical requirement for dc-dc topologies used in partial power converters. PPP comprises numerous nonisolated architectures, requiring galvanic isolation inside to deliver power between parallel and series ports of a dc-dc cell. Figure.3 is an example of using a non-isolated boost converter to implement a PPP, where a potential short-circuit is taking place. Nevertheless, some non-isolated PPP configurations were presented, as shown in Figure.4. Figure.4(a) and (b) are PPP configurations using a flipped buck converter and a regular buck-boost converter, respectively. However, later research showed they are equivalent to a full power boost converter in terms of stress of the main components and thus cannot be considered true PPCs [34]. Hence, dc-dc topology used in a PPC must have some kind of galvanic isolation, either by a transformer or using a flying energy storage component (capacitor or inductor) [33], [35], [36].

B. LIMITATIONS OF VOLTAGE REGULATION CAPABILITIES
The limitation of the transformation ratio is a trade-off in partial power converters. Figure.5 illustrates the relationship between the transformation ratio M = V L /V S , and the converter power rating normalized by the total input power for the voltage step-up conversion (V S < V L ). There is a critical voltage conversion ratio M crit1 = 2 for SIPO partial power converters. If the conversion ratio is higher than M crit1 , the SIPO partial power converter will handle more power than the full power converter and lose its advantages due to the opposite power flow [32]. The voltage gain of the converter decides the percent of power processed by the converter, as can be appreciated from Figure.6.

C. SERIES INPUT PARALLEL OUTPUT PARTIAL POWER CONVERSION
In the case of SIPO PPC configuration, the relation between input and output voltage and currents are as follows: where V L , V Co , V s , I S , I L , I C , M , M C are the load voltage, dcdc converter output voltage, source voltage, source current, load current, dc-dc converter input current, static dc voltage gain of the system, and the static dc voltage gain of the dc-dc converter. The active power processed by the PPP system components is derived by multiplying equation (1) by the load current The total power of the system is denoted as P t , P D is the amount of power transferred to the load without any processing and P P is devoted to the power processed by the switched mode dc-dc converter. And the power processed ratio (PPR) for this configuration is defined as Different topologies based on SIPO configuration have been reported in the literature [6], [9], [32], [37], [38]. In [6], a SIPO PPC is presented based on the flyback converter. The PPP system was designed for PV applications. The system demonstrated an efficiency of around 96% with a partiality ratio of 20%. The presented efficiency is not high compared to the full power converter, and due to the usage of the flyback converter, there is a restriction in the duty cycle range. SIPO VOLUME 10, 2022 PPC presented in [32] is like the system described in [31]. However, due to the high partiality ratio considered, around 50%, the PPP system efficiency is low and less than 93%. In [37], a SIPO PPC based on the dual active bridge topology has been presented. The dc-dc cell is working in bucking mode all the time. The converter operates with soft switching most of the time even with high partiality ratio reaching 50%. The converter demonstrated an efficiency of around 96.4%.
A two-stage step-down SIPO PPC based on the full-bridge isolated dc-dc converter is presented in [9]. This PPP system is designed for string PV integration and demonstrated experimentally. Due to bucking at the extreme limit, the converter efficiency is around 98.7%, even though the partiality ratio is around 10%, as was predicted above.
Though the SIPO configuration is suitable for step-down applications, the topology developed in [38] is based on a boost converter. The dc-dc converter is boosting the fraction of voltage across its terminal. The reported efficiency of around 99% shows that SIPO implementation with other than bucking dc-dc topologies could be beneficial.

III. PARTIAL POWER BUCK-BOOST QUASI Z-SOURCE SERIES RESONANT PARTIAL POWER CONVERTER
The proposed QZSSR partial power converter schematic is illustrated in Figure.7. The schematic is based on SIPO configuration. The Proposed PPP is stepping down; the input voltage is always higher than the output voltage. However, the QZSSR converter itself may operate in boosting or bucking mode based on the voltage applied to its input terminals and the used transformer ratio. The high-performance QZSSR converter studied in this work was originally proposed and validated in [39], [40], and [41]. The converter operates in shot-through mode when the voltage at its input terminals is less than V o /2n, normal mode at V o /2n, and bucking mode when the voltage is higher than The leakage inductance of the isolation transformer L lk could be used as a resonant inductor. During the active states, its current resonates with the voltage of the parallel combination of the voltage doubler (VDR) capacitors C 1 and C 2 . As the switching frequency is close to the resonant frequency, the inverter switches and VDR diodes operate under zero current switching conditions. Idealized waveforms of the QZSSR PPP converter for the bucking and boosting modes are shown in Fig.8.

A. OPERATION IN THE BOOST MODE
In the boost operating region, the converter is controlled by the shoot-through PWM with symmetric overall poof active states (ST-PWM) at the resonant frequency, as shown in Figure 8 (b). The converter operates in the boosting mode if the input voltage is below V o /2n. The DC voltage gain is regulated by the variation of the shoot-through duty cycle: where V o , n, v, and D ST are load voltage, voltage applied to the input of the dc-dc converter (difference between source and load voltage), cumulative duty cycle of the shoot-through states over the switching period T SW (D ST = T ST /T SW ). The shoot-through states are generated by the cross-conduction of all switches of the inverter bridge, which occurs twice per switching period. Equivalent circuits describing the converter operation in the boost mode are illustrated in Figure 9.

B. OPERATION IN THE BUCK MODE
In the buck mode, the converter is controlled by the Phase Shift Modulation (PSM) at the resonant frequency, see Figure 8 (a). The converter operates in the buck mode if the input voltage is above V o /2n. Equivalent circuits describing the converter operation in the buck mode are illustrated in Figure 10. The switch S qZS is always conducting, thus configuring the qZS network as a passive filter at the input of the dcdc converter. The output voltage is controlled by the variation of the phase shift angle ϕ between the leading (S 1 and S 2 ) and lagging (S 3 and S 4 ) legs of the inverter bridge. As the resonant current is discontinuous, the control characteristic of the QZSSR in the buck mode depends strictly on the quality factor Q of the resonant tank: where where R L is the load resistance.

IV. CONVERTER DESIGN GUIDELINES
Converter parameters are designed to cover the worst scenarios of operation. The system design is divided into two parts as follows:

A. MAGNETICALLY INTEGRATED QZS NETWORK
The design of the coupled inductor relies on the current ripple passing through it, and the maximum ripple occurs in the boost mode at minimum input voltage and shoot-through duty cycle at its maximum level. Assuming that the qZS network is symmetrical, see the equivalent circuit of the synchronous magnetically integrated shown in Fig. 11. Hence the leakage inductances are not considered in the design guidelines.
Due to high operation under high switching frequency, the parasitic inductance of interconnection wires between the input source and the converter (L W ) may affect the winding leakage inductance L lk1 , which affects the current ripples of the windings currents I 1 and I 2 .
In order to avoid that difference in ripple, L W has been considered in the design equations as follows [40]: where L lk1 * is the effective leakage inductance of the input winging of the coupled inductor (L lk1 * = L lk1 +L W ), V (min) is the minimum input voltage value of the converter, and D ST (max) is the corresponding maximum shoot-through duty cycle. Magnetizing inductance is much larger than the leakage inductances, even though taking into account the parasitic inductance for the interconnection wires. Therefore, the simplified equation for the magnetizing inductance can be indicated as [40]: The qZS capacitors are designed at the condition where the ripple of the ( V CqZS ) is at its highest value -in the boost VOLUME 10, 2022 mode at the minimum input voltage: where C qZS is the capacitance of the qZS capacitors.

B. INTEGRATED SERIES RESONANT TANK
The integrated series resonant tank of the converter is composed of the parallel combinations of the VDR capacitors (C 1 + C 2 ), and the isolation transformer leakage inductance referred to the secondary winding (L lk ). The inverter switches and VDR are operating at Zero Current Switching (ZCS), due to the discontinuity of the current through the resonant network. Therefore, the critical value of the L lk when the converter still maintains DCM could be given as: Special attention should be given to the design of the leakage inductance L lk , as the smaller values of L lk will lead to higher currents through the isolation transformer, which results in increased current stresses of the semiconductors.
To maintain the resonance, the values of VDR capacitors could be selected by The QZSSRC could operate in both voltage buck and boost modes. However, their utilization directly depends on the transformer turns ratio n. This paper utilizes two ways to design the given converter to provide to compare the performance of boost and buck-boost dc-dc converter topologies in the SIPO PPCs. First, the transformer turns ratio could be selected to ensure that the proposed SIPO PPC operates in the boost mode from the minimum ( v min ) to the maximum ( v max ) series voltage values for a fixed load voltage V L : The other alternative would be to design the given converter to cover one-half of the voltage regulation range with the boost mode and the other half with the buck mode. Assuming v min ≤ v max /10, the turns ratio could be selected as: (19) The unique feature of the selected QZSSRC topology is that the same prototype could be used with two different transformers. This approach would provide a fair comparison between the performance of the boost and buck-boost dc-dc topologies in the SIPO PPCs.

V. EXPERIMENTAL RESULTS AND DISCUSSION
The proposed system has been tested in the laboratory to verify its operation and measured efficiency until 2 kW. A 300 W prototype, which is depicted in Figure 12, has been built based on parameters shown in Table 1.
This prototype was wired between two high voltage ports to form a SIPO configuration discussed in the previous sections. The load side voltage is stabilized at 350 V, while the input voltage of the PPP system varies to cover all the operating points of the converter.
The operating voltage range for the dc-dc converter is set to ensure v max = 60 V. Therefore, two transformers were built on the RM14 core of 3C95 material: with turns ratios of   n = 3 and n = 5.6. Both designs aimed to achieve the same maximum flux density in the transformer core.
For the transformer with n = 5.6, the dc-dc converter operates in the boost mode when the voltage applied to its input terminal varies from v min = 5 V to 31V, normal mode  at 31 V, and buck mode from 31 to 62 V. At each operating voltage the current is varied from 0 to 5 A. The load voltage is fixed at 350V for all operating points. The experimental efficiency was measured using a Yokogawa WT1800 power analyzer. Figure. 13 represents a case study where the input current is fixed to 1A, and the input voltage of the PPP system is swept from 355V to 410 V. In the case of 355V at the input, the converter input terminal voltage is v min = 5 V due to SIPO connection. With a transformer turns ratio of 5.6, the converter operates in the boost mode until the voltage across its terminal is lower than 31 V, and higher than this value the converter is operating in bucking mode. Figure. 13(a) is the overall PPP system efficiency, while Figure. 13(b) represents the dcdc converter efficiency. Despite the relatively low efficiency of the converter, the overall system efficiency is higher than 99%. By having higher voltage across the dc-dc converter input, the converter will process higher power, which is an apparent reason for the reduction of overall system efficiency.
Different case studies with the input current of 2 A, 3 A, 4 A, and 5 A are shown in Figures 14 -17, respectively. By increasing the input current, the overall efficiency is slightly decreased at the same partiality ratio; meanwhile, the dc-dc converter efficiency is improving slightly. For all case studies, the buck mode is used at partiality ratios above 8%, which could explain the relatively low efficiency of the dc-dc converter in the buck mode. In the buck mode, when the input voltage of the PPP system increases up to 410 V, i. e., the series voltage v reaches 60 V. Hence, the converter has to process higher powers at lower efficiency values, which results in the PPC minimum efficiency achieved at the maximum partiality, as could be expected. It varies from 98.1% at the current of 1 A to 97.9% at the current of 5 A, which shows small variations across the load power. The efficiency drop is caused by the relatively low dc-dc converter efficiency dropping from 89% to 86%.
These relatively low dc-dc converter efficiency values could be explained by the very pragmatic design of the dc-dc converter aiming at a low cost and use generic off-theshelf components. As could be expected, the dc-dc converter achieves its maximum efficiency at around 30 V at the input. For all the load currents, the PPC efficiency stays over 99.5% for < 30 V owing to the good performance of the dc-dc converter at light loads in the boost mode as the normalized gain is limited to six by design.
In order to extend the boosting range of the converter, the used transformer has been replaced by another one with a turns ratio of n = 2.9. The primary purpose of this modification in turns ratio is to study the system performance when the dc-dc converter operates solely in the boost mode. As a result, the dc-dc converter operates at the minimum dc gain, i.e., minimum voltage boosting efforts and high efficiency, at higher K pr values when it handles the maximum power. On the other hand, it has to operate at the normalized dc gain of over tenfold at v min = 5 V.
It is worth mentioning that the PPP system based on the buck-boost converter shows almost no variations in the  efficiency at series voltage value below 30 V, i.e., in the boost more of the dc-dc converter. This is caused by the dc-dc    After replacing the transformer, the dc-dc converter is able to operate in the boost mode until 400 V at the input side of  the PPP system. Similar to the buck-boost implementation, PPC with the boost dc-dc converter was studied for the input currents of 1, 2, 3, 4, and 5 A, as shown in Figures 18-22, correspondingly. As could be expected, the boost implementation of the dc-dc converter results in its best performance achieved at the partiality ratios over 7%, i.e., series voltage v > 25 V. As it was predicted, the dc-dc converter performance at lower partialities is poor, resulting in efficiency as low as 57% due to the dc-dc converter operating at a normalized dc gain of over tenfold. However, those low efficiency values are achieved at very low power levels, resulting in the PPP system efficiency of over 99.4%. Compared to the buck-boost implementation of the dc-dc converter, the PPP system efficiency is reduced at v < 30 V. However, it is improved at higher partiality ratios. For example, at v = 50 V, the PPP system efficiency is improved by 0.2% at the maximum current of 5 A.

VI. CONCLUSION
Despite numerous research activities in the field of partial power processing, the series input parallel output partial power converters were underrepresented in literature. This could be associated with the relatively poor performance of the first demonstrated examples. However, this poor performance is mainly caused by the use of voltagebucking galvanically isolated dc-dc topologies. As a result, the design of such a SIPO PPC becomes unpractical as it requires a very high transformer turns ratio to realize the required regulation range. In addition, it features low efficiency due to the very high voltage step-down requirements when operating at the maximum power, i.e., the maximum series voltage between a voltage source and a dc load. This work compares two other possible dc-dc converter implementations -boost and buck-boost. By selecting the quasi-Z-source series resonant converter topology, it was possible to provide a fair comparison between the boost and buck-boost implementations as they differ only in transformer design and use the same other components in the experimental prototype.
The following conclusions could be drawn based on the existing literature and the obtained results. First, SIPO PPCs are beneficial in voltage step-down applications, where they can provide full efficiency of over 99%. Second, galvanically isolated buck dc-dc converter topologies are not recommended for implementation in SIPO PPCs. Third, galvanically isolated buck-boost dc-dc converter topologies provide good performance in SIPO PPCs in applications where a PPC operates mainly at low partiality ratios (below 10%). Fourth, galvanically isolated boost dc-dc converter topologies provide balanced performance in the entire regulations range as their efficiency increases with the power processed by a SIPO PPC. Hence, they could be recommended for implementation in SIPO PPCs in applications where PPC will operate mainly at partiality ratios above 10% or where its operation is equally probable in the entire regulation range.