Active Switched-Capacitor Embedded Quasi-Z-Source Inverter and PWM Methods for High Boost Capability and Switching Loss Reduction

This paper proposes a novel topology, named a single-phase active switched-capacitor embedded quasi-Z-source inverter (ASC-EqZSI), and two pulse-width modulation (PWM) methods, namely, PWM1 and PWM2 methods for the proposed ASC-EqZSI topology to improve the boost capability and reduce switching loss. The boost capability can be improved by using an additional non-shoot-through (NST) state, referred to as the NST2 state, besides conventional shoot-through (ST) and NST states. In the NST2 state, the switch in the impedance network is switched on to boost the dc-link voltage while generating the ac output voltage. A PWM1 method is suggested to control both the NST2 and ST time intervals with one carrier signal for improving the boost capability. A PWM2 method aims to reduce the commutation count of the switches and diodes in the proposed topology while maintaining the enhanced boost capability. The switching loss can be reduced by almost 40%. A comparative analysis between the proposed topology with the PWM2 method and five other topologies with an active switched Z-network is performed. The proposed topology with the PWM2 method has a higher ac voltage gain and efficiency with fewer components. Simulation and experimental results are carried out to validate the performances of the proposed topology and PWM methods.


I. INTRODUCTION
The Z-source inverter/quasi-Z-source inverter (ZSI/qZSI) composed of an impedance network and an inverter provides the buck-boost capability by a shoot-through (ST) state and short-circuit immunity of an inverter leg [1], [2]. However, the voltage gain of the classic ZSI/qZSI is not high, which makes it difficult to apply to industrial applications requiring a high voltage gain. In order to solve the boost limitation of the classic ZSI/qZSI, many modifications and improvements on the ZSI/qZSI-based topology and its modulation techniques have been proposed. Utilizing switched-inductor The associate editor coordinating the review of this manuscript and approving it for publication was N. Prabaharan .
By adding extra passive components into the (q-)Z-source impedance network, the new inverter topologies are referred to as continuous diode-assisted/capacitor-assisted extendedboost qZSIs [9], enhanced-boost ZSI combined with two switched Z-impedance networks [10], enhanced-boost qZSI with two switched-impedance networks (EB-qZSI) for continuous input current configuration [11], embedded switchedinductor qZSIs with two isolated dc sources [12], and high-boost qZSI combined with two quasi-Z-source networks [13]. These topologies offer high voltage gain. However, they have many passive components, which results in VOLUME 10, 2022 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ increasing the cost and volume of the power converter and deteriorating the efficiency. The switched boost inverter (SBI) based on the Inverse Watkins-Johnson topology [14] was introduced in [15]. The SBI has one extra switch to reduce the number of passive components in the impedance network. However, it has a lower boost factor than the ZSI/qZSI, and its source current is discontinuous. In order to build up to the same boost factor as the classic qZSI with a continuous dc source current, a class of quasi-switched boost inverters (qSBIs) was proposed in [16]. Compared with a classic single-phase qZSI, a single-phase qSBI has fewer passive components, one extra switch in the impedance network, and higher efficiency [17].
In order to improve the boost capability of the basic (q)SBI, various topologies with the active switched network, like the (q)SBI topology, have been proposed [18], [19], [20], [21], [22], [23], [24], [25]. By adding one diode and capacitor to the classic qSBI, switched-capacitor quasi-switched boost inverters (SC-qSBIs) [18] can achieve high voltage gain with low voltage stress across capacitors and diodes. The SC-qSBIs can be extended to an n-cell to improve the voltage gain even more. In [19], two high voltage gain quasi-switched boost inverters (HG-qSBIs) and a modulation technique were proposed to perform a high voltage gain with a low source current ripple. In comparison with the EB-qZSI [11], an enhanced-boost qZSI with an active switched Z-network (EB/ASN-qZSI) in [20] can reduce two LC pairs with the same boost factor. Additionally, the high boost non-isolated qZSI (HB-ni-qZSI) in [21] can produce a higher voltage gain with fewer components by combining with a new active switched Z-impedance network. The continuous current active SL-boost-qZSI (cASLB-qZSI) in [22] provides high boost capability with continuous input current by combining an active switched-inductor boost network. The switched ZSI based on the active switched-capacitor with a high voltage conversion ratio, referred to the capacitor assisted switchedcapacitor extended boost-ZSI (CSC-EB-ZSI), was presented in [23]. The continuous input current qZSI (CC-qZSI) can be implemented by applying the concept of switched-boostmodified ZSI into the qZSI [24]. The high voltage gain active switched qZSI (HGAS-qZSI) in [25] offers a higher output voltage with proper number of components in the impedance network.
The (q-)ZSI requires special attention to its modulation strategies, because the modulation strategies for the (q-)ZSI affect the current ripple, switching loss, boost capability, and also reliability [26], [27]. Modulation strategies for the (q-)ZSI can be classified as carrier-based pulse width modulation (CB-PWM) and space vector modulation (SVM). The CB-PWM includes simple boost control [1], maximum boost control [28], and maximum constant boost control methods [29]. Among these three modulation methods, the maximum boost control method realizes the highest boost factor by turning all zero states into ST states. In [30] and [31], the hybrid PWM combined the PWM and the pulse-amplitude modulation (PAM), and the dual switching modulation are proposed, respectively, to reduce power loss of the converter. A sawtooth-carrier-based PWM (SCPWM) method with the zero-voltage switching operation is applied to qZSI to reduce the total harmonic distortion (THD) and inductor current ripple [32]. In [33], the conventional space-vector concept was modified and applied to the (q-)ZSI, due to the high voltage utilization and low current harmonics. Additionally, modified SVM methods for qZSI have been suggested to reduce the inductor current ripple, switching loss, and leakage current [34], [35], [36], [37].
The qSBI has one additional switch in the impedance network to reduce the passive elements. In the qSBI, the switches in the inverter are utilized to generate a sinusoidal output voltage, and the switch in the impedance network is used to boost the dc-link voltage. A simple boost control method has been applied to the qSBI, where the switch is turned on during the constant ST state [15]. Modified modulation strategies for the qSBI have been introduced to improve the performance [19], [38], [39], [40], [41]. A family of PWM control schemes, aiming to improve the modulation index and reduce the inductor current ripples of the qSBI, were proposed in [19], [38], and [39]. The modified PWM strategy for the dc-linked type qSBIs proposed in [40] increases the boost factor and reduces the inductor current ripple. The PWM strategies in [19] and [38], [39], [40] increase the switching loss of the additional switch and require two carrier signals with different frequency and amplitude. An SVM method for a modified qSBI with two switches to suppress the magnitude of the common-mode voltage was introduced in [41].
In this paper, a novel single-phase active switchedcapacitor embedded qZSI (ASC-EqZSI) topology and two new PWM methods, namely, PWM1 and PWM2 methods for achieving high boost capability and reducing switching loss are suggested. The improved boost capability is achieved by using an additional non-shoot-through (NST) state, referred to as NST2, besides conventional shoot-through (ST) and NST states. The PWM1 method for the proposed ASC-EqZSI topology is presented to control both the NST2 and ST time intervals for increasing the boost factor. The proposed PWM2 method can reduce the switching losses of the switches and diodes in the proposed topology, while still maintaining high boost capability. The operation analysis of the proposed ASC-EqZSI topology and impedance parameter design are described. A detailed comparative analysis between the proposed ASC-EqZSI utilizing the new PWM method and five other topologies with an active switched Z-network is also performed. The performances of the proposed topology and PWM methods are verified through simulations and experiments using a prototype built in the laboratory. Fig. 1 shows the structure of the proposed single-phase ASC-EqZSI topology. The impedance network connected to a single-phase inverter of the proposed topology has two inductors (L 1 , L 2 ), two capacitors (C 1 , C 2 ), two diodes (D 1 , D 2 ) and  one switch (S 0 ). The dc source is embedded in series with the inductor L 2 in the impedance network.

A. OPERATION PRINCIPLES OF ASC-EqZSI
The topologies based on the SBI structure generally have two operating states: the shoot-through (ST) state and the non-shoot-through (NST) state. The additional switch S 0 is switched on during the ST state, and is switched off during the NST state. The proposed topology has one more operating state, which we refer to as the NST2 state. In the NST2 state, the switch S 0 is switched on outside of the ST time interval to step up the boost factor, while the inverter operates in the active or zero state like the conventional NST state. The conventional NST state is referred to as the NST1 state. Therefore, the proposed topology has three operating states: ST, NST1, and NST2 states. The equivalent circuits of the proposed topology for the three operating states are shown in Fig. 2. Using equivalent circuits of the proposed topology, the operation principles for the three operating states will be described.

1) SHOOT-THROUGH STATE
During the ST state, the dc-link of the inverter is shorted by conducting two switches of any phase leg and the switch S 0 is switched on, as shown in Fig. 2(a). The diodes D 1 and D 2 are reverse biased during the ST time interval of D · T , where D is the ratio of the ST time to one switching period T . The inductor L 1 is charged from the capacitor C 2 . The inductor L 2 is charged from the dc input voltage V dc and capacitor C 1 . From Fig. 2(a), the inductor voltages and capacitor currents are given by 2) NON-SHOOT-THROUGH 1 STATE In the NST1 state, as shown Fig. 2(b), the proposed inverter operates in the active or zero state. The switch S 0 is switched off and two diodes D 1 and D 2 are forward biased. A singlephase inverter and load are modelled with a constant current source I o , which is the current through the inverter bridge during the NST1 and NTS2 states. The capacitor C 2 is charged from the dc voltage V dc and inductor L 2 . The energy stored in the two inductors L 1 and L 2 is supplied to the load side and two capacitors C 1 and C 2 . From Fig. 2(b), the inductor voltages, capacitor currents, and dc-link voltage are given by

3) NON-SHOOT-THROUGH 2 STATE
In the NST2 state, as shown in Fig. 2(c), the switch S 0 is switched on outside of the ST time interval while the proposed inverter operates in active or zero state like the NST1 state. The time interval in the NST2 state is D a ·T , where D a is the ratio of the NST2 time interval to one switching period T . Thus, the time interval of the NST1 state is represented as (1-D-D a ) · T . The dc-link voltage can be boosted by controlling the duty ratio D a while generating the ac output voltage. The diode D 1 is reverse biased whereas the diode D 2 is forward biased during this state. The capacitor C 2 and inductor L 1 supply the energy to the capacitor C 1 and load side. The inductor L 2 is charged from the dc input voltage V dc . From Fig. 2(c), the inductor voltages, capacitor currents and dc-link voltage are given by It can be noted that the dc-link voltage in the NST2 state is the same as that in the NST1 state.

B. BOOST FACTOR AND INDUCTOR CURRENT STRESS
By applying the volt-second balance principle to both inductors L 1 and L 2 from (1), (3), and (6), two capacitor voltages VOLUME 10, 2022 can be derived as The capacitor voltage V C1 from (5) or (8) is a peak dc-link voltage. From (9), the boost factor B is expressed as where the boost factor B can be controlled by the ratio D a as well as D.
By applying the ampere-second balance principle to both capacitors C 1 and C 2 from (2), (4), and (7), the average of two inductor currents can be derived as

III. PROPOSED PWM METHODS FOR ASC-EQZSI
Two new PWM methods (PWM1, PWM2) based on the simple boost control method suitable for the proposed ASC-EqZSI are proposed to increase the boost factor and reduce the switching losses of the switches and diodes.
A. PWM1 METHOD The PWM signals of the pairs S 1 /S 3 (or S 2 /S 4 ), which are switched complementarily, are generated by comparing a carrier signal V tri with the positive modulation signal V ref _p (or the negative modulation signal V ref _n ). By comparing the ST envelop signal V ST to the carrier signal V tri , the ST signal S ST is generated to adjust the ST time interval, D · T . The ST signal S ST is inserted into the PWM signal S 1 (or S 4 ) when the reference signal is positive (or negative) to generate the ST state. Two signals P P and P n are utilized to detect the polarity of the reference signal. By comparing another control signal V Da to the carrier signal V tri , the signal S Da is generated to adjust the time interval of the NST2 state, D a · T . The switch S 0 control signal can be obtained from adding S ST and S Da . The commutation count of the switch S 0 is increased two-fold due to the NST2 state. Therefore, the switching loss of the switch S 0 is increased.   Fig. 4 shows the proposed PWM2 method to reduce the commutation count of the diodes and the inverter switches as well as the switch S 0 in the proposed topology. The PWM2 method can be implemented by replacing the triangle carrier signal of the PWM1 method with a sawtooth carrier signal. The process used to generate the S ST , S Da , and PWM signals of the PWM2 method is the same as that of the PWM1 method. The logic of the switching signal generation for the proposed PWM method is illustrated in Fig. 5. The proposed PWM methods require only one carrier signal, and the PWM methods can be selected depending on whether the carrier signal is a triangular wave (V tri ) or a sawtooth wave (V saw ).

C. COMPARISON BETWEEN PWM1 AND PWM2 METHODS
The PWM2 method can reduce the commutation count of the three switches (S 1 , S 4 , and S 0 ) in the proposed  topology by half, compared to the PWM1 method. In addition, the commutation count of one diode (D 1 ) in the impedance network can be reduced by half by using the PWM2 method. Therefore, the proposed PWM2 method can reduce the overall commutation count of all switches and diodes in the ASC-EqZSI topology by 40% and 34%, respectively, as compared to the proposed PWM1 method. It can be noted that the switching losses of the switches and diodes in the ASC-EqZSI topology can be considerably decreased by adopting the PWM2 method. Fig. 6 compares the efficiency and power loss of the proposed topology with the PWM1 and PWM2 methods. As shown in Fig. 6(a), the efficiency of the PWM2 method is 2-3% higher than that of the PWM1 method, and the efficiency difference between the two PWM methods increases slightly as the output power is increased. Fig. 6(b) compares the power loss distribution of the proposed topology with the PWM1 and PWM2 methods, when the output power is 1.2 kW. From Fig. 6(b), the switching losses of the switches and diodes of the PWM1 method are about 40% higher than those of the PWM2 method. The other losses of the two PWM methods are nearly the same. Fig. 7 shows the two inductor current ripples in one switching cycle using the PWM1 and PWM2 methods, respectively. The current ripple on the inductor L 1 ( i L1 ) of the PWM2 method is the same as that of the PWM1 method. The PWM2 method has a slightly higher current ripple on the inductor L 2 ( i L2 ), as compared to the PWM1 method. Fig. 8 shows the two capacitor voltage ripples in one switching cycle using the PWM1 and PWM2 methods, respectively. The ripple voltage in V C1 ( V C1 ) of the PWM2 method is the same as that of the PWM1 method. The PWM2 method has a slightly higher voltage ripple on the capacitor C 2 ( V C2 ), as compared to the PWM1 method.

IV. PARAMETER DESIGN OF PASSIVE COMPONENTS
The proposed single-phase ASC-EqZSI topology generates low-frequency (2ω) and high-frequency ripples on the inductors and capacitors in the impedance network, similar to the classic single-phase qZSI. Assuming the 2ω ripple can be eliminated by using control methods [42], the inductors and capacitors are designed based on the high-frequency ripple when the PWM2 method is used for the proposed topology. From Fig. 7(b), the maximum peak-to-peak current ripples of the inductor L 1 during the ST state and the inductor L 2 during the NST1 state can be expressed as Using (10), (11), (12), (13), (16), and the load current I o =V pn /R L where R L is the load resistance, the inductances of L 1 and L 2 are derived as where the maximum permitted current ripple ranges of the two inductors are defined as r L1 % = i L1 /ī L1 and r L2 % = i L2 /ī L2 , respectively. Additionally, f s is the switching frequency.
From Fig. 8(b), the maximum peak-to-peak voltage ripples of the capacitor C 1 during the ST state and the capacitor C 2 during the NST1 state can be expressed as Using (10), (11), (12), (13), (19), and the load current equation, the capacitances of C 1 and C 2 are derived as where the maximum permitted ripple ranges of the two capacitors are defined as r C1 % = V C1 /V C1 and r C2 % = V C2 /V C2 , respectively.

V. COMPARATIVE ANALYSIS
To evaluate the performance of the proposed ASC-EqZSI topology using the PWM2 method, a comparative study is performed with five state-of-the-art topologies with an active switched network: EB/ASN-qZSI [20], HB-ni-qZSI [21], CSC-EB-ZSI [23], CC-qZSI [24], and HGAS-qZSI [25]. The comparisons focus on the number of components used in the impedance network, boost factor, ac voltage gain, capacitor voltage stress, inductor current stress, voltage and current stresses on the diodes and switch, and ST current. Table 1 depicts the number of passive and active components in the impedance network of the proposed ASC-EqZSI topology and five other topologies. Both the proposed ASC-EqZSI and CC-qZSI topologies have the fewest components in the impedance network among the five topologies, and they have  the same number of the inductors, capacitors, diodes, and switch each.

B. BOOST FACTOR AND AC VOLTAGE GAIN COMPARISON
The boost factor or ac voltage gain is a critical factor to evaluate the performance of the proposed ASC-EqZSI with the PWM2 method and the five other topologies with the conventional PWM method in [16]. Fig. 9(a) shows the boost factor versus shoot-through duty ratio D for the six topologies. The proposed topology with the PWM2 method at D a = 0 has the lowest boost factor with CC-qZSI topology. The boost factor can be increased by increasing the duty ratio D a . When the duty ratio D a of the proposed topology increases to 0.5, the proposed ASC-EqZSI topology achieves the highest boost factor in the overall range of D, followed by HGAS-qZSI topology. The ac voltage gain G is expressed as G =V o /(V dc /2) = M ·B, whereV o is a peak output voltage and M is a modulation index. The relationship between M and D is determined by the modulation strategy. As the proposed topology adopts a simple boost control method, the shoot-through duty ratio D is limited to 1 -M and the duty ratio D a is limited to M . Using D = 1 -M , the ac voltage gain G can be written in terms of M . Fig. 9(b) shows the ac voltage gain G versus modulation index M for the six topologies. When the duty ratio D a = 0.5, the proposed topology with the PWM2 method achieves the highest ac voltage gain. When the duty ratio D a increases more, a higher boost factor and ac voltage gain can be obtained.

C. VOLTAGE AND CURRENT STRESSES COMPARISON
In order to compare properly the voltage and current stresses on the capacitors, diodes, and switch in the impedance network of the six topologies, the voltage stress ratio, defined as the ratio of the voltage stress to the ac output voltage, is used for the voltage stress comparison. The current stress ratio, defined as the ratio of the current stress to (B·I o ), is used for the current stress comparison. Table 2 summarizes the voltage stress ratios of the capacitors, diodes, and switch, and the current stress ratios of the inductors, diodes, and switch for the six topologies.
Figs. 10(a), 10(b), and 10(c) show the total voltage stress ratio comparison of the capacitor, diode, and switch, respectively, for the proposed ASC-EqZSI with the PWM2 method and the five other topologies. The proposed ASC-EqZSI topology provides the highest total capacitor voltage stress ratio, and the total diode voltage stress and switch voltage stress ratios are in the comparatively intermediate range. Fig. 10(d) shows the ratio of the total inductor current stress to (B · I o ). The total inductor current stress ratio of the proposed ASC-EqZSI at D a = 0 is the same as that of the three other topologies like EB/ASN-qZSI, HB-ni-qZSI, and CC-qZSI. When D a increases to 0.5, the proposed ASC-EqZSI has the lowest total inductor current stress ratio. Because the total inductor current is the same as the ST current, the lowest total inductor current stress ratio saves the cost of the inductors and inverter switches. Figs. 10(e) and 10(f) show the ratios of the total diode and switch current stress to (B·I o ), respectively. Both the proposed ASC-EqZSI and CC-qZSI can produce the lowest total diode current stress ratio. The HB-ni-qZSI topology provides the lowest switch current stress ratio, followed closely by the proposed ASC-EqZSI, CC-qZSI, and CSC-EB-ZSI topologies.
From Fig. 10, a large duty ratio D at the proposed ASC-EqZSI increases the voltage stresses across the capacitors and diodes, and decreases the current stresses on the inductors, diodes, and extra switch.
To better evaluate the voltage and current stresses of the proposed topology, the switching device power (SDP) is introduced. The SDP of the switching devices is expressed as the product of their voltage and current stresses. The total SDP of the topology is defined as the summation of SDP of all switching devices used at the topology. In this paper, the SDPs for diodes and extra switch used at the impedance network are compared. Based on the definition of the peak and average SDPs in [10], the peak and average SDPs for extra switch of the proposed ASC-EqZSI with the PWM2 method are derived as where P o is the inverter output power. Similarly, the peak and average SDPs for diodes are derived as follows: Fig. 11 shows the comparisons of the average and peak SDPs of diodes and extra switch versus buck-boost factor G between the proposed topology and five other topologies. From Figs. 11(a) and 11(b), the peak and average SDPs for extra switch of the proposed ASC-EqZSI topology are slightly higher than CSC-EB-ZSI, and lower than the other topologies. From Figs. 11(c) and 11(d), the peak SDP for diodes of the proposed ASC-EqZSI topology is slightly higher than the CC-qZSI, and the same as the CSC-EB-ZSI. The proposed ASC-EqZSI topology has the lowest average SDP for diodes.

D. COMPONENT STRESS FACTOR COMPARISON
The component stress factors (CSFs) in each component of the six topologies are compared. Based on the definition in [43], the total inductors' winding CSF (WCSF), capacitors' CSF (CCSF), diodes' CSF (DCSF), and active switch' CSF (SCSF) of the proposed topology when D a = 2D are derived as where W i is the individual weight assigned to component i, and j W j is the sum of the individual weights for all components of the same type in the impedance network. Based (24)- (27), the CSF comparison between the proposed ASC-EqZSI and five other topologies is shown in Fig. 12. As shown in Figs. 12(a) and 12(b), the inductors' WCSF and CCSF of the proposed ASC-EqZSI are slightly higher than the HGAS-qZSI. From Fig. 12(c), the proposed ASC-EqZSI has the lowest DCSF among six topologies. From Fig. 12(d), the extra switch' CSF of the proposed topology is higher than the CSC-EB-ZSI and nearly the same as the CC-qZSI.

E. POWER LOSS AND EFFICIENCY COMPARISON
The power losses of the proposed ASC-EqZSI using the PWM2 method are analyzed. For the proposed topology, the total power loss can be classified as the inductor losses, capacitor losses, conduction and switching losses of IGBT switches, and conduction and reverse recovery losses of diodes.  The power loss in the inductors consists of the winding conduction loss and core loss. The core loss can be negligible compared with the total inductor losses. The winding conduction loss is dependent on the equivalent series resistance (ESR) of the inductor r L and rms value of the inductor current. Using the approximated rms value of the inductor currents from (12) and (13), the total inductor loss can be expressed as By considering the ESRs of the two capacitors r C1 and r C2 , the total power loss in the capacitors is expressed as The diode loss is divided into the conduction power loss and reverse recovery loss. The conduction power loss of diodes is dependent on the forward voltage drop V F and the on-resistance r D . By neglecting the ripples of the inductor currents, the total conduction power loss of the two diodes can be derived as The reverse recovery loss of the two diodes can be derived as where Q rr is the reverse recovery charge of the diode. The power loss of IGBT consists of the conduction power loss and switching power loss. The extra switch S 0 is turned on during the ST and NST2 time intervals. Therefore, the conduction and switching power losses of the extra switch S 0 are expressed as, respectively where V CE(sat) and r CE represent an insulated gate bipolar transistor (IGBT) on-state collector-emitter voltage and collector-emitter on-state resistance, respectively, and t on and t off are the turn-on and turn-off times of IGBT, respectively. The shoot-through current i ST flowing through inverter switches during ST state is Using the shoot-through current i ST , the average and rms values of the inverter switches' current can be expressed as where cos ϕ is the power factor of the ac load side. Using (34) and (35), the conduction power loss and switching power loss of all inverter switches can be derived as follows: The efficiency and power losses of the proposed ASC-EqZSI using the PWM2 method are compared with the five other topologies using the PWM1 method without NST2 state (D a = 0). To compare properly the efficiency and power losses for all of topologies, it is assumed that they all have the same ESRs of the inductors and capacitors. Also, the forward voltage drop and collector-emitter on-state resistance of IGBT switch, and the forward voltage drop and on-resistance of the diodes are the same for all compared topologies. Fig. 13 depicts the efficiency versus output power of the proposed ASC-EqZSI and five other topologies. As shown in Fig. 13, compared with other topologies, the proposed ASC-EqZSI has a higher efficiency in the whole range of output power. Fig. 14 shows the comparison of the power losses of each component for the six topologies when the output power is 1 kW. It can be noted that the proposed ASC-EqZSI provides the lowest power losses of all components. The main reasons for reducing the power losses of the proposed ASC-EqZSI topology can be summarized as follows: • The proposed topology requires fewer number of components in the impedance network.
• An additional NST2 state is included to achieve a higher voltage gain with a lower shoot-through duty cycle.
• The proposed PWM2 method can reduce the commutation counts of all switches and diodes in the proposed topology.

VI. SIMULATION AND EXPERIMENTAL RESULTS
To validate the effectiveness of the proposed topology and PWM methods, both simulations and experiments are performed. The system parameters used at the simulations and experiments are given in Table 3.

A. SIMULATION RESULTS
To verify the theoretical analysis of the proposed topology and PWM methods, simulation is performed using the PSIM program. Fig. 15 shows the simulation results of the proposed ASC-EqZSI topology with the PWM2 method when D = 0.2, M = 0.8, and D a = 0.4. As shown in Fig. 15, the capacitor voltages V C1 and V C2 are boosted to 225 V and 181 V, respectively, and the dc-link voltage can be boosted to 225 V from a dc input voltage of 30 V. The RMS (root means square) values of the ac output voltage and current are 127 V and 1.27 A, respectively. Fig. 16 shows the simulation results of the proposed ASC-EqZSI topology when two PWM methods are used under the same operating conditions as those used in Fig. 15. The dc-link voltage in he NST2 state is the same as that in the NST1 state. The commutation counts of the switch S 0 and diode D 1 under the PWM2 method are half those of the PWM1 method. The PWM2 method has a slightly higher current ripple on the inductor L 2 , as compared to the PWM1 method.

B. EXPERIMENTAL RESULTS
The experiment is performed using a laboratory prototype, as shown in Fig. 17. The laboratory prototype consists of a single-phase inverter, impedance network, LC filter, resistive   load, and control board with a 32-bit DSP 320F28335 and field programmable gate array (FPGA) for generating PWM control signals. Fig. 18 show the experimental results of the ASC-EqZSI with the PWM2 method at the same operation conditions as the simulation results shown in Fig. 15. According Fig. 18, the dc-link voltage can be boosted to 216 V, which is 7.2 times the dc input voltage of 30 V. The capacitor voltage V C1 is equal to a peak dc-link voltage. The ac output voltage and the capacitor voltage V C2 are stepped up to 123 Vrms and 174 V, respectively. Fig. 18(c) show the experimental waveforms of the output voltage and current when the inductive load of 30 mH is appended with a load resistor of 50 for the resistive-inductive load. Fig. 18(d) shows the dynamic responses for the ac output voltage and current, the capacitor voltage V C1 when the load resistor decreases from 100 to 50 with the inductive load of 30 mH. When the load resistor decreases from 100 to 50 , the output current increases. Also, the capacitor voltage V C1 and output voltage are slightly reduced due to increasing the voltage drop of the components in the proposed ASC-EqZSI. Fig. 19 shows the experimental waveform of two inductor currents i L1 and i L2 , dc-link voltage, and gating signal of switch S 0 with the PWM1 and PWM2 methods. The average values of i L1 and i L2 with the PWM1 method are 3.93 A and 9.85 A, respectively. The average values of i L1 and i L2 with the PWM2 method are 4.03 A and 9.65 A, respectively. The current ripple of inductor L 2 with the PWM2 method is slightly higher than that with the PWM1 method. The current of inductor L 2 is the input current, which is continuous. The switch S 0 is switched on during both ST and NST2 states. Fig. 20 shows the PWM signals of switches S 1 , S 2 , S 3 , and S 0 with the PWM1 and PWM2 methods when the reference signal is positive. The ST signal S ST is inserted into the PWM signal S 1 to generate the ST state. The PWM2 method can reduce the commutation count of the two switches S 1 , S 0 by half, as compared to the PWM1 method.    The THD of the ac output voltage filtered by an LC filter, as calculated from Fig. 21(a), is 1.36%. The experimental waveform of the two diode voltages V D1 and V D2 is shown in Fig. 21(b). The reverse voltages across the two diodes D 1 and D 2 during the ST state are (V C1 + V C2 ) and V C1 , respectively.

VII. CONCLUSION
In this paper, a single-phase active switched-capacitor embedded quasi-Z-source inverter (ASC-EqZSI) and two PWM methods for the proposed ASC-EqZSI topology are proposed. The proposed PWM1 method can considerably increase the boost factor with fewer components in the impedance network by using an additional operating state referred to as NST2 state. The boost factor can be increased by increasing the NST2 time interval besides the ST time interval. The proposed PWM2 method can reduce the commutation count of all switches and diodes in the ASC-EqZSI topology by 40% and 34%, respectively. Thus, the efficiency of the ASC-EqZSI with the PWM2 method is 2-3% higher than that with the PWM1 method due to reduction of switching loss. The PWM signals are generated by a simple logic circuit with one carrier signal.
Through the comparative analysis between the proposed topology with the PWM2 method and five state-of-the-art topologies, the proposed topology with the PWM2 method has the highest boost factor and ac voltage gain with the fewest components in the impedance network by increasing the NST2 time interval. It also provides the lowest inductor current stress and ST current, and the voltage stresses across the diodes and switch in the comparatively intermediate range, although it suffers from the highest capacitor voltage stress. Additionally, the proposed ASC-EqZSI leads to the higher efficiency in the whole range of the output power.
As demonstrated by the experiments using a prototype built in the laboratory, the dc-link voltage is stepped up to 216 V, and the inverter produces a line-to-line output voltage of 123 Vrms from a dc input voltage of 30 V when D = 0.2, M = 0.8, and D a = 0.4. The THD of the ac output voltage filtered by an LC filter is 1.36%.