Reconfigurable Quadratic Converters for Electrolyzers Utilized in DC Microgrids

In this paper, three topologies of quadratic buck DC-DC converters were proposed that are capable of reconfiguring to semi-quadratic buck-boost converters, in case of an open-circuit fault in their power switch. In other words, with the aid of graph-based circuit synthesis concepts, a topology is obtained for a safe transition from one switch to another, where all other components maintain their role in contributing to optimal power conversion. Knowing that the quadratic buck converters have been proven to be an effective DC-DC circuit to supply an electrolyser as a load with specific characteristics i.e., low-voltage and high-current, the reconfigurability feature adds an extra measure of success for safer power delivery for such a load that an undesirable shut-down would negatively impact its life-cycle. The performances of three proposed synthesised topologies were compared and validated through simulation and experiments on laboratory prototypes.


I. INTRODUCTION
Transition to renewable energy systems has been associated with extensive research and development activities in different areas, such as photovoltaic (PV) panels, power converters and energy storage systems to ensure that a reliable, efficient and cost-effective power delivery would be viable [1]. Many studies and technical reports have regarded hydrogen as a suitable energy storage system with a high energy density, which could be of benefit in maintaining a reliable power in a renewable energy microgrid in conjunction with batteries [2]. However, in a carbon-neutral environment, the produced and consumed hydrogen should be green, i.e., produced via renewable energy and electrolysis. The power electronics aspect of hydrogen production through electrolysis is particularly of interest when considering the power conversion stages from the source to the load. As shown in Fig. 1 (a), knowing that electrolyser is a DC load, depending on the power source, the power conversion unit is required to The associate editor coordinating the review of this manuscript and approving it for publication was Francisco Perez-Pinal . transform either an AC power (e.g. grid) or a DC power (e.g. PV) to a DC power, and hence either an AC-DC rectifier or a DC-DC converter would be required [3], [4]. steady state. With that said, assuming a fixed temperature, an electrolyser stack is normally modelled as a small resistive load in steady state [5], [6]. As such, the power converter's terminal will be connected to a low-voltage and high-current resistive load. Fig. 2 shows typical applications of power converters in a renewable energy system, where in both cases the converter is supposed to step down the voltage and supply the electrolyser. Fig. 2 (a) applies to a typical low power system, which resembles a residential rooftop solar system comprised of PV arrays, batteries and Maximum Power Point Tracking (MPPT) charge-controller. As such, considering a typical 24 V system, an electrolyser stack can be connected to this system via a DC-DC converter that typically owns a voltage gain ratio of 6 : 1 and 4 : 1, respectively for a 4 V two-layer and 6 V three-layer stacks. Fig. 2 (b) represents a high-power DC microgrid, where the scalability and reliability of a microgird require a more sophisticated arrangement of PV arrays, batteries and loads in comparison with Fig. 2 (a). In more details, the voltage level of the busbar is rated roughly at 400 V , which allows AC load connection via inverters as well as a battery connection via bidirectional DC-DC converters. It is worth noting that a typical electrolyser of this power range is expected to have more number of stacks which conveys a higher power and/or higher voltage level (e.g. 48 V ). As an instance, a DC-DC converter that liaises between the busbar and electrolyser would typically require the voltage gain ratio of 8 : 1. Therefore, considering the discussions made above in regards to Fig. 2, due to the relatively high voltage step-down and high current step-up capability required in both cases, the conventional buck converter might not be a perfect choice due to its limited gain. Hence, various solutions have been proposed in the literature to overcome this limitation. In [7], it was suggested to use an interleaved buck converter, where the high output current is distributed over different branches of the outgoing node. In [8], the authors proposed the quadratic buck converter due to its high voltage conversion capability. In [9], the direct coupling of PV and electrolyser for loss minimisation was investigated. It has been investigated and proven that the consistency of the power supplied to the electrolyser would have an impact on its lifecycle. Therefore, a converter that can guarantee less intermittency of power across the electrolyser's terminal, would have a better chance of getting an electrolyser operated as usual in long run [10], [11]. Thus, a topology that is capable of coping with the faults and minimising the shut-down occurrences of a power converter supplying an electrolyser is deemed beneficial for extending the lifeycle of such an equipment. In [12], [13], [14], [15], and [16], a team adopted the graph-theory concepts according to works from Maksimovic [17] and Zhou [18] and proposed a synthesis approach to derive fault-tolerant versions of the existing converter topologies. This paper attempts to investigate the quadratic buck converters [19] so that an electrolyser can be supplied with a high step-down voltage gain via a reconfigurable structure. While single-switch quadratic buck and buck-boost converters are the focus of this study [20], [21], [22], the approach may be applied to other quadratic topologies [23], [24], [25].
In this paper, thee reconfigurable dc-dc converters are proposed that are tolerant to the faults created due to the open-circuit of switches, and can transition from one topology to another, i.e., from quadratic buck to semi-quadratic buck-boost. The main motivation behind this work was the electrolyser applications in microgrids, where i) the load has high current and low voltage levels, but the busbar has low current and medium voltage levels, and ii) the reliability is of concern as the converter failure can affect the lifecycle of equipment. Therefore, based on the literature, it has been investigated to find a topology that has these benefits. Previously, it has been proven that reconfigurable topologies are possible to be made from graph theory concepts. However, the concept has not been applied to quadratic topologies, before. In addition, application-wise, there has been minimum effort to address such a concern for particular applications. Therefore, via graph and circuit theories, it has been mathematically proven that two quadratic buck and buck-boost are capable of being merged so that a reconfigurable topology is made, which is suitable for hydrogen applications. Furthermore, a comparison has been made for pre-and post-failure modes so that the fidelity of the discussion is validated through comparison and experiments. Section II proposes three new topologies and their synthesis. Section III presents a comprehensive comparison, while section IV presents the obtained results. Finally, section V concludes the paper.

II. GRAPH-BASED SYNTHESIS APPROACH
The converter synthesis approach was originally presented in [17] and [18], then adopted to derive reconfigurable  topologies in [12] and [14]. Originally, the synthesis approach is established by two equivalent circuits, namely AC and DC equivalents, represented as graphs. After extraction of the equivalent graphs for two different converters, one may investigate the possibility of introducing a reconfigurable topology by merging two (or more) graphs, albeit via the following steps and considerations imposed by the graph theory concepts.

A. PROPOSED TOPOLOGY I
The quadratic converters that were originally presented in [19], are the starting point. In simple terms, as shown in Fig. 3, having two back-to-back cells with the gain of D, of which the second is the conventional buck converter, a quadratic buck converter is made with the gain of D 2 as shown in Fig. 3 (a). The same steps, i.e., cascading the first cell with the conventional buck-boost converter will lead to semi-quadratic buck-boost converter with the gain of −D 2 /(1 − D) as shown in Fig. 3 (b).

1) STEP 1: AC AND DC EQUIVALENTS
In the first step, we intend to obtain the DC and AC equivalent graphs. In summary, the DC and AC graphs are obtained as follows.
• For DC graphs: The capacitors are removed while the inductors are shorted. The sources and loads are considered as external one-port elements and can be removed in DC mode.
• For AC graphs: The voltage sources and capacitors are shorted while the current sources and inductors are removed. Accordingly, Fig. 4 shows the equivalent circuits, where the quadratic buck type I -with the modified position of switch -along with its DC and AC equivalents are presented in Figs

2) STEP 2: SUPERPOSITION RULE
In the second step, we start to investigate the possibility of merging these two converters to establish a reconfigurable fault-tolerant topology. By superimposing the DC graphs in Fig. 4 (b) and Fig. 4 (e), a new DC graph is built up, as per Fig. 4 (g). It is worth noting that diodes are located identically in both DC graphs, while the switches are connected to different nodes which implies the new DC graph will contain two switches and three diodes. Similarly, superimposing the AC graphs leads to a new AC graph shown in Fig. 4 (h). Noteworthy, despite connecting to the same nodes, S x and S 1 both should appear in the AC graph as they have previously appeared in DC graph.

3) STEP 3: INCIDENCE MATRICES
In the third step, we build the incidence matrices for the resultant DC and AC graphs, i.e. A a and A d which are presented in (1) and (2). According to the graph theory, the m th × n th VOLUME 10, 2022 (row m, column n) array is noted as 1, -1, and 0 respectively when the current is outgoing, incoming and not flowing.
As the penultimate step before introducing the reconfigurable topology, we need to shape the modified incidence matrix to accommodate the missing inductors and/or capacitors. To obtain this, we need to add the missing nodes to the matrix A d . To understand why some nodes might have been missed, we need to recall the definition of DC graph. Fig. 5 (a) corresponds to A d , where four nodes are present. We know that in DC graph, capacitors and sources are removed so we can presumably locate V in and V out by a simple inspection. Then, noting that the capacitors and sources were shorted in AC graphs, we can imagine an analogy between A d and A a . In other words, we can conclude that nodes 0 and 1 are grouped into node a. By comparing the corresponding rows of nodes 0 and 1 in A d with the corresponding row of node a in A a , one can claim that row a of A a is in fact the result of aggregation of row 0 and part of row 1 in A d . This will get us to the corresponding rows of nodes 0 and 0' in A d . The same steps are valid when assuming that nodes 2 and 1 in A d are grouped into node c in A a , which yields 2 and 2' of A d . This is also true for nodes 1, 1' and c in A d and A a . Consequently, A d is expressed as (3), which represents Fig. 5 (b).

B. PROPOSED TOPOLOGIES II AND III
There are other possible topologies that could be synthesised with the same number of components, same voltage gain ratio and same reconfigurability, albeit with different combination. Considering the quadratic buck topology type I presented in Fig. 6 (a), with an intention to merge with semi-quadratic Zeta converter as shown in Fig. 6 (c), one might follow the five mentioned steps and build the graphs and matrices and obtain a reconfigurable topology. However, for the sake of simplicity of calculation, as it has been proven above, the common cell including S 2 , S 2 , L 1 , C 1 in Fig. 6 (a) and Fig. 6 (c) can be excluded for investigation of reconfigurability. In other words, merging a buck converter with a Zeta converter will lead to a reconfigurable buck and buck-boost topology as presented in [12], which could then be transformed into a quadratic buck and semi-quadratic buck-boost topology by inserting the buck cell, known as topology II, as illustrated in Fig. 6 (d). If one considers the quadratic buck topology II, as presented in Fig. 6 (b), and intends to merge it with the semi-quadratic Zeta converter, the same synthesis steps that were presented for topology I should be followed, which by inspection, leads to the topology III as depicted in Fig. 6 (e). With a closer look at this topology, one could confirm that this aligns with topology II derivation concepts. In other words, the auxiliary switch (S x ) connects to the same node that the main switch (S 1 ) is connected to in both topologies, i.e. right before the buck cell in topology II and right after the buck cell in topology III. Fig. 7 shows the summary of the proposed converters of which (a), (b) and (c) respectively represent topologies I, II and III.

III. CIRCUIT ANALYSIS AND COMPARISON
Each circuit has got two operating modes, depending on the switch that is in operation. When the switch Q 1 is in operation, the circuit, namely the Q 1 -based configuration, operates a quadratic buck converter. Accordingly, when Q 1 is out of order due to an open-circuit fault, the circuit is reconfigured by putting Q 2 into operation, namely the Q 2 -based configuration, operates as a semi-quadratic buck-boost converter.

A. STEADY-STATE ANALYSIS
Each of these six configurations-i.e., three quadratic buck (Q 1 -based) and three quadratic buck-boost (Q 2 -based) configurations-have partially been previously analysed in the literature as a separate circuit. Therefore, for the sake of simplicity and to avoid excessive repetition of steady-state circuit analysis, Fig. 8    of inductors and the current waveform of capacitors, respectively. As an instance, for topology II, applying KVL to the first loops of Fig. 9 (a) and Fig. 9 (b), one can express the voltage across the inductor L 1 indicated as (4) and (5), respectively for the case that the switch Q 1 is on and off. similarly, applying KVL to the second loops of Fig. 9 (a) and Fig. 9 (b), yields (6) and (7) for the voltage across the inductor L 2 . Considering the volt-second balance, i.e. assuming that the average voltage across inductors over a duty cycle of the switch Q 1 is zero, one can substitute (4) and (5), and (6) and (7) into (8), and obtain the voltage across capacitors C 1 and C 2 , expressed as (9), in line with the information provided in Table 1.
The same goes for the current through capcitors C 1 and C 2 which are expressed as (10) and (11), when KCL applies to the first nodes of Figs. 9 (a)-(b). Similarly, (12) and (13) are the results of KCL on the second nodes of Figs. 9 (a)-(b). Considering the charge-second balance, i.e. assuming that the average current through capacitors over a duty cycle of the switch Q 1 is zero, one can substitute (10) and (11), and (12) and (13) into (14), and obtain the voltage through inductors L 1 and L 2 , expressed as (15), in line with the information provided in Table 1.
The same discussion is valid for the Q 2 -based topology, i.e. when the volt-second and charge-second balance are applied to the loops and nodes of Fig. 9 (c) and Fig. 9 (d).  As indicated before, all three topologies are using the same number of components, i.e. two capacitors, three diodes, and two switches (one active and one reserved switch). This is also evident in Fig. 8 Table 1. It is evident that this transition, is paid at the cost of increased stress, to avoid the shut-down, whereas the difference is significantly lowered as the step-down ratio is increased, and that is what the quadratic buck converter is designed for, i.e. higher step-down capability. Though there have been other quadratic buck converters in the literature which this paper is actually derived from, a fair comparison would be a comparison based on the reconfigurable converters. Therefore, Table 1 along with Fig. 10 could potentially be used as a guideline for the selection of components as well as choosing the right circuit based on a particular application.

B. TRANSIENT ANALYSIS
State-space averaging method, particularly small-signal modelling is used to achieve the control-to-output transfer function so that the transient behaviour of the system is analysed in more details. According to the literature, there are four steps to follow, which have been thoroughly explained by the author in [22] and [26], and are summarised as follows. • Step i: State-space equations for each operating state, when the switch is on and off.  Step iii: applying a small ac perturbation the vicinity of steady-state operating points. • Step iv: applying the Laplace transform and obtaining the transfer function Following the steps above, the state-space equations are expressed as (16) For the quadratic buck (Q 1 -based) and the semi-quadratic buck-boost (Q 2 -based) circuits in topology II and their operating states as presented in Fig.9. After applying a small perturbation, using the Laplace transform, the control-to-output transfer function is expressed as (16).
The coefficients a 1 , a 0 , b 4 , b 3 , b 2 , b 1 , and b 0 for topology II with the parameters presented in section IV are as follows, respectively for Q 1 -based and Q 2 -based circuits. Further discussions in regards to the transfer function derivation is presented in Appendix.

S. A. Gorji: Reconfigurable Quadratic Converters for Electrolyzers Utilized in DC Microgrids
Accordingly, the Bode diagrams associated with each of the transfer functions for (Q 1 -based) and (Q 2 -based) topologies are shown in Fig. 11. This is the key to design an appropriate controller for the closed-loop experiments. In this case, the optimum closed-loop proportional-integral (PI) controller parameters were obtained from Sisotool in MATLAB and the results will be presented in section IV.

C. EFFICIENCY ANALYSIS
The input power goes through several power conversion stages, which are associated with power losses, typically dissipated as heat. In a power converter, one can consider four main types of losses classified as follows.
• The inductor loss P L , which is made up of two terms namely conduction loss P wr caused by winding resistance and the core loss P core caused by hysteresis and eddy current in the magnetic core. • The capacitor loss P C , which is generically negligible and made by the parasitic resistor.
• The switch loss P S , which is made up of two terms, namely conduction loss P SC caused by the switch resistance in on mode, and switching and the switching losses P rf that occurs over the rise-time and fall-time.
• The diode loss P D , which is due to the forward voltage drop of the diode, during the conduction mode. As per the explanation above, the efficiency formula can be expressed as (18), where η, P out and P in denote the efficiency, output power and input power, respectively. η = P out P in = P out P out + P L + P C + P S + P D (18) The efficiency equation along with the datasheet information shall be used to obtain the analytical efficiency of a power converter. This has been applied to the proposed converter and  the result will be presented in section IV, which is particularly important for this paper, when a converter is transitioned from one switch to another.

IV. RESULTS: SIMULATION AND IMPLEMENTATION
The preliminary tests were carried out in MATLAB Simulink (with the aid of PLECS Blockset). The test was conducted on a 0.5 load, where the input voltage of 24 V is supposed to be stepped down to 6 V . The initial results were obtained and illustrated in Fig. 12. This was the basis for circuit implementation and experimental results. As such, Fig. 12 (a) shows the variation records for topology I, and Figs. 12 (b)-(c) captured the same scenario for topologies II and III. The main intention here was to check if the circuits are able to operate smoothly, as per the expectations, when Q 1 is disconnected and Q 2 is activated. These preliminary results validated the circuit analysis and the comparison made in Table 1, where as an instance, the current through inductor L 2 should be I L2 = I out = 12 A (from V out /R) for the circuits that Q 1 is in effect, prior to the incident at t = 2 s. When an open circuit fault occurs in Q 1 and the converter is reconfigured via Q 2 , according to Table 1, I L2 will be then varying from I out to I out /(1 − D), or from 12 A to 20A.
After the initial validation through simulation, the three proposed circuits were prototyped so that the analysis, claims and simulations could be further validated. The prototyped circuits are shown in Fig. 13 (a), Fig. 13 (b) and Fig. 13 (c), which respectively show topologies I, II and III. In addition. The hardware setup has been presented in Fig. 13(d). The converters' components and specifications are presented below: • Input Voltage, Output Voltage: 24 V , 6 V • Power Switches Q 1 , Q 2 : Rohm RGTH00TK65GC11 • Diodes D 1 , D 2 , D 3 : IXYS DPF30I300PA • Inductors L 1 , L 2 : 1 mH on Fair-Rite 5978018601 • Capacitors C 1 , C 2 : 100 µF 470 µF Vihsay 136RVI • Load: 0.5 (paralleled RS100 1R) It is worth noting that some components including capacitors are located at the bottom layers of printed circuit boards (PCBs) in Fig. 13. Furthermore, the switching frequency was set at 64 kHz, provided by TI's F28069M. As inferred from Figs. 13 (a)-(c), there is only one gate-driver UCC21320 used for switches Q 1 and Q 2 , in a sense that the gate-source signals are generated via two separate digital signal processor (DSP) pins, connected to the gate-driver, and generating the gate-source voltages V GS1 and V GS2 . The scenario is formed in a way that if Q 1 stops working for any reason, the circuit is reconfigured through Q 2 , i.e., V GS1 is initially generated so that the circuit operates as a quadratic buck converter; As soon as Q 1 is disconnected due to an open-circuit fault, V GS2 is generated, albeit at a different duty cycle ratio to meet the voltage gain requirements of reconfigured topology that is changed from D 2 to D 2 /(1 − D). Therefore, there is no (or minimum) impact on the output voltage of the converter supplying the external load. It is also worth noting that the load has intentionally been selected to be a relatively low voltage and high current, as per the justifications made in introduction to mimic a three-layer electrolyser stack. In particular, one might find an equivalent lab electrolyser membrane stack of similar specifications. As an instance, a 3-layer stack electrolyser of model Titan EZ-180 is a 0.6 (10A, 6 V) load in steady-state, which resembles the same external load used for experiments. Fig. 14 shows the captured waveforms from the experiments. Fig. 14 (a)-Fig.14 (c) illustrate the case for topology I. The circuit was initially operating with Q 1 . As a result, one would expect the circuit to operate as a quadratic buck converter (Topology I), as per Table 1 and Fig.7. Therefore, prior to the incident, having a duty cycle of 50%, with the input voltage of 24V , output voltage should roughly be equal to 6V , which is evident in this figure. In addition, according to Table 1, the voltage stress on diodes D 1 , D 2 and D 3 and the current through L 1 and L 2 are respectively equivalent to 24V , 24V and 12V , and 6A and 12A. When the incident occurs, i.e., Q 1 is opened and Q 2 comes to effect, the converter transitions from quadratic buck to semi-quadratic buck-boost topology. That being said, the duty cycle clearly needs to be adjusted to 39% so that the output voltage is maintained at the original value. In addition, the voltage stress on diodes, as well as the current through inductor all follow the expectations (Table 1) and are 24 V , 24 V , 16 V and 8 A, 20 A, respectively for D 1 , D 2 , D 3 , and L 1 and L 2 . Figs. 14 (d)-(e) and Figs. 14(f)-(h) show the same scenario for topologies II and III, respectively. Both circuits are experiencing a transition from quadratic buck to quadratic buck-boost when Q 1 is disconnected and Q 2 is activated. In both cases, the duty cycles are adjusted accordingly so that the output voltage is maintained at the original value. In addition, the values for diode voltage and  The converter has also been tested in closed-loop with a PI controller designed as per the discussions in section III. is due to the different time division. This would also convey that in case of an appropriate controller design, the reconfiguration transition either in the load or the source side, would minimise the impact on the load or input busbar in Fig. 2. Eventually, the efficiency discussion in section III is applied to the converter and the efficiency has been calculated versus load variations as presented in Fig. 16 (a). The efficiency variations follow the expected paradigm, i.e. the higher the power rating is, the higher the efficiency drop will be as the current across the components increases. In addition, for this particular converter, it would be of interest to find out the efficiency changes in case there is a switch failure and the converter is reconfigured. Fig. 16 (b) presents this perception, with a similar fashion followed in Fig. 10. As an instance, when the output voltage is set at 6 V , with the input voltage level of 24 V , the efficiency undergoes a slight change, as noted in Fig. 16 (b), from 92% to 88%.

V. CONCLUSION
According to the graph theory for electrical circuits, three quadratic buck topologies were synthesised with three semiquadratic buck-boost topologies in a way that three new reconfigurable topologies were proposed. The resultant topologies are capable of coping with the open-circuit fault of switches so that as soon as one switch fails, the circuit is reconfigured to another topology via the other switch; as such, all other circuit components are utilised in the power conversion process via different paths. The quadratic buck topologies are a good choice for electrolyser applications, where a high step-down voltage conversion ratio is required. In addition, the reconfigurability of such circuits would meet the requirements of electrolyser's lifecycle, where a power outage would have a negative impact. The proposed circuits were analysed, simulated and prototyped to validate the feasibility of the investigated approach. For future work, one can explore the possibility of applying the same approach to the isolated topologies, where the input-output isolation is a requirement and/or another degrees of freedom for changing the voltage gain ratio, namely the transformer, is available.

APPENDIX SMALL-SIGNAL MODELLING
The following shows the steps for derivation of the controlto-output transfer function that was presented in section III.
Step i: For topology II, the equivalent circuits are shown in Fig. 9. For Q 1 -based topology, respectively when the switch is on and off, KVLs and KCLs lead to (19) and (20).  The same goes for (21) and (22) for Q 2 -based topology.
Step ii: Averaging the state-space equations, according to the Volt-second and charge-second balance, i.e. to weighaverage with D and (1 − D) leads to the matrices presented in Table 2. Please note the output matrix C is defined as Step iii: Applying a small perturbation to the inputs replaces them with v in = V in +v in and d = D +d, where ''∧'' represents the small-signal perturbation. Neglecting the second-order terms will lead to the updated matrix B as presented in table 3.
Step iv: One can use the Laplace transform to obtain the transfer functions. Thanks to MATLAB, ss2tf (A, B, C, D, n) can be used to obtain the transfer function via the state-space equations presented above, where n = 1 derives the V out /V in S. A. Gorji: Reconfigurable Quadratic Converters for Electrolyzers Utilized in DC Microgrids and n = 2 derives V out /d. The Bode diagrams for the numerical and the parametric transfer functions of Q 1 -based topology were derived as (17), (23), and plotted in Fig. 17.
The author would like to thank his colleagues Dr. Amir Hakemi, Dr. Amir Ganjavi, and Prof. Dezso Sera for their technical feedback.