A 6.3-ppm/°C, 100-nA Current Reference With Active Trimming in 28-nm Bulk CMOS Technology

This paper introduces a current reference based on <inline-formula> <tex-math notation="LaTeX">$\Delta V_{GS}$ </tex-math></inline-formula> generation principle and adopts integrated poly-p+ resistors and a nW-power OTA to reduce the line sensitivity. Implemented in a 28-nm standard CMOS technology, the circuit provides a nominal current equal to 100nA and operates down to 0.6V with a line sensitivity equal to 1.2%/V in the range [0.8-1.8]V and a temperature coefficient equal to 6.3ppm/°C in the range [10-90]°C. Comparison with the state-of-the-art confirms the validity of the proposed solution and its suitability to be exploited in ultra-low-power and area-constrained applications.

N V = density of state in the valence band at T = 300 K. E g = energy band-gap of silicon. n = 1 + C d /C OX sub-threshold slope factor.

I. INTRODUCTION
The last decade technological improvements in the fabrication of nanometer-scale integrated active devices is doubtless the key factor that has given birth to the paradigm of the Internet-of-Things (IoT). The reduction of cost per transistors has paved the way, for sub-mm 2 electronic devices, to their pervasive use in smartphones, cars, houses, industrial tools and, more recently, implantable medical devices (IMDs) [1], [2], [3]. These lasts, more specifically than the others, are dominated by low invasiveness as main feature. Since most of the area of an electronic device is occupied by its battery, the always growing demand of battery-less and energyautonomous IoT nodes has led to the concept of Energy Harvesting for IMDs [3], [4]. This concept is intended as the ability of scavenge energy from the external environment (i.e., light, heat and vibrations) and/or from externally coupled energy sources as electromagnetic fields or acoustic ultrasonic pressure waves [3]. In addition, being the harvested energy limited in terms of power density and being the maximum overall power budget lower than few mW, the ultralow power (ULP) consumption (i.e., µW or, better, nW-power level [5], [6], [7], [8]) is the second key-factor that enables to disseminate complex electronic systems in human bodies.
Similarly to the review in [34], it is possible to classify the literature on the generation of constant-with-temperature (CWT) currents into four categories: 1) β-multipliers: starting from the results of the Widlar current generator reported in [50], it is possible to divide a proportional-to-absolute-temperature (PTAT)voltage with a poly resistance with the same temperature coefficient (TC), obtaining thus a CWT current as in [11], [16], [20], [21], [22], [23], [25], [26], [28], and [30]. 2) ZTC: since all the transistors show a zero-temperaturecoefficient (ZTC) gate-to-source voltage bias point, these temperature unsensitive currents are generate through a V GS (T ). Indeed, when working in strong-inversion transistors a slightly PTAT bias is required to obtain a ZTC-working transistor, while when in weak-inversion, a complementary-to-absolutetemperature (CTAT) bias point is needed for the same purpose [13], [17], [18], [51]. Also 2T-based current reference belong to this methods, since they generate CTAT (or PTAT) bias voltage by exploiting the 2T-voltage reference structure [29], [33]. 3) PTAT+CTAT: they exploit the weighted sum between PTAT and CTAT current generators. The principle of the PTAT generation relies on V BE /R (using BJTs); on the other hand, the CTAT temperature dependency is obtained by using the ratio between V GS (or a V BE of a BJT) of NMOS transistors and a resistor [12], [14], [15], [19], [24], [27], [31], [32]. This work aims to present a novel current reference implemented in the 28-nm Bulk CMOS technology provided by TSMC. It is based on V GS generation principle and adopts integrated poly-p+ resistors and a nW-power, self-biased, single-stage OTA to reduce the line sensitivity of the circuit that provides a reference current, I REF = 100 nA. Moreover, it is well-suitable to work down-to 0.6-V supply voltage, revealing very-low TC comparable to that of a Bandgap Current reference (BGCR), while the overall power consumption can be reduced down to 180 nW, when V DD = 0.6 V and 230 nW with V DD = 0.8 V. Furthermore, an active trimming network is added to reduce the PVT variation and compensate for the TC in all the five simulated process corners.
The current reference is designed for an implanted biomedical device, where the average operating temperature is  • C. However, it is capable of working with better performance as compared to the state-of-the-art in the range [0-100] • C. The paper is organized as follows. Section II illustrates the working principle of the proposed current reference. Section III explains the proposed current reference with the active trimming network, while Section IV reports the layout and the post-layout simulations of the circuit. Section V presents the comparison of the proposed CR with the previous arts and, finally, in Section VI concluding remarks and comments are reported.

II. WORKING PRINCIPLE A. BEHAVIOUR OF V TH IN SUB-THRESHOLD SHORT-CHANNEL DEVICES
The working principle of the proposed CMOS CR and its temperature stability is explained starting from two main considerations on the variations of the threshold voltage of transistors and with the support of Fig. 1, where the threshold voltage variation of thin-oxide n-type transistors operating in sub-threshold region is reported. The first variation relies on V TH vs. temperature, when transistors work in sub-threshold region. Indeed, as explained in [13] and [52], the behaviour of V TH as function of the temperature is identified and approximated with the following linear equation where V TH 0 is the threshold voltage at room temperature and K T is positive when working in sub-threshold region, as reported in Fig. 1. Furthermore, as it can be observed in Fig. 1, while varying the channel lengths of n-type SVT09 transistors, the decreasing slopes of the curves remain almost equal each other and about K T ≈ 446 µV/ • C. In addition, after having defined the sub-threshold slope factor n = 1 + C d /C OX , it is possible to give out the equation for the temperature coefficient of V TH as [53] From Eq. (2), is observed that K T just depends on the process and does not present any significant process variations.
On the other hand, the second variation of the threshold voltage of the transistors is experimentally observed by simulation results in Fig. 1 and Fig. 2; indeed, while increasing the channel length of short-channel NMOS devices, L N , the value of V THN increases too. In conclusion, it is possible to exploit this last dependency of V TH on the channel length without using devices with different threshold voltages as in Fig. 2 and as adopted by [18], [20], [22], [29], [32], [33]. This last design option leads, as main counterpart, to a more complex layout, to an increase in the number of photo-lithographic masks required for the realization and an increase to the overall cost of the chip.

B. SIMPLIFIED CIRCUIT CONFIGURATION AND ANALYSIS
The simplified circuit for the proposed CR is shown in Fig. 3. It is a 4-transistors (4T), V GS -based, sub-threshold and self-biased current reference, as the one proposed by [22] with the main difference, for the simplified schematic, of the use of the same type of transistors for M 1 and M 2 .
The circuit is essentially made-up by a PMOS current mirror, with thick-oxide (SVT18) transistors, M 3 and M 4 . The analysis of the CR is based on the Kirchhoff's Voltage Law (KVL) inside of the loop made by R 1 , V GS2 and V X . Indeed, by using KVL it is possible to carry-out the following equation Suppose that both M 1 and M 2 are working in sub-threshold region and that their drain currents are given by is possible to simplify the previous equations neglecting the channel length modulation effect as follows In addition, taking into account that both M 1 and M 2 are implemented using the same type of transistors (SVT09), it was supposed, in Eq.(4a) and Eq.(5a), that n 1 = n 2 = n and C OX 1 = C OX 2 = C OX . By solving Eq. (5a) and Eq. (5b) for the gate-source voltages of M 1 and M 2 and substituting these in Eq. (3) it is found out that Since M 1 and M 2 are selected of the same type of transistors (SVT09), in order to obtain a positive quantity for V TH 1 − V TH 2 , to simplify Eq. (6), it was chosen with α a positive multiplicative factor. As a result, Eq. (6) becomes the following where I REF just depends on design choices as the value of the resistance, R 1 , the difference V TH 1 − V TH 2 and the ratio S 3 /S 4 . Moreover, it is important to underline that also the integrated resistor, R 1 , varies with temperature with the following expression where R 10 is the value of R 1 at T = 0 K and b R and c R are positive coefficients. In addition, for a sake of conciseness, it is possible to neglect the 2 nd -order term in Eq. (8), leading to a 1 st -order linear approximation.
The temperature stability of a CR is measured by its temperature coefficient, TC with the equation where  (7), it is possible to find out the optimum ratio, (S 3 /S 4 ) opt , to minimize the TC. The math passages are here summarized where K T 2,1 = K T 2 − K T 1 (for a sake of brevity) and V R1 is derived out from Eq. (3) and Eq. (7). By expanding the intermediate passages reported in Eq. (11) it results that where, for a sake of conciseness, it was indicated V TH 1,2 = V TH 1 − V TH 2 . In a more intuitive way, Eq. (7) suggests that an increase in V TH 1,2 leads to an increase in the CTAT behaviour of the CR, while an increase in the ratio Moreover, by evaluating β R T 0 1 and K T 2,1 0, Eq. (13) is approximated as follows

C. LINE SENSITIVITY
The Line Sensitivity (LS) quantifies the static sensitivity of the output on the DC variations of the power supply line voltage, namely V DD . The equation that allows to evaluate the LS is the following This quantity is a useful tool for characterizing the robustness of the CR in the presence of variations of V DD as in the case battery discharge or various regulated power supply voltages (V DD,L and V DD,H ) inside the same SoC [54]. Since, the reference current in the simplified CR in Fig. 3 depends on the current ratio of I D3 /I D4 provided by the linear current mirror M 3 -M 4 , it is important to investigate on this ratio when varying V DD .
Since V X ,Y < V DD it is possible to approximate Eq. (16) as follows From Eq. (17) is possible to understand that just if V X = V Y it is true that I D3 /I D4 = S 3 /S 4 ; otherwise, this above mentioned current ratio will vary with V DD as reported in Fig. 4 with the red curve. Indeed, while V DD increases, the drain current of M 3 increases too, leading to an increase of V GS1 = V X , but also I REF increases lowering the voltage on node V Y .

III. THE ACTIVE TRIMMING NETWORK
The schematic in Fig. 5 shows the complete circuit of the proposed CR without the trimming network. It takes into account the advantages of the solution depicted with Fig. 3 in the previous section with the addition of a self-biased singlestage OTA (shown in Fig. 6) to improved the line sensitivity and a start-up circuit to avoid any zero bias point. The used technology is the 28-nm Bulk CMOS provided by TSMC and the simulation environment is Cadence Virtuoso. The nominal value of the reference current is set equal to I REF = 100 nA. It was realized making a V TH 1,2 ∼ 18 mV drops on a nominal R 1 = 180 k . This last integrated resistor was realized in poly-p+ and presents a specific resistance-over-square equals to R s = 576 / , while β R ≈ 0.0275 %/ • C. The theoretical value for (S 3 /S 4 ) th kept from Eq.  The addition of the OTA provides a negative feedback control on the voltage V G and allows keeping V X = V Y 330 mV whatever it will be the variation on V DD . Moreover, since it does not require any stringent specification in terms  Corner analysis reported in Fig. 8 and Tab. 1 shows that without any trimming sub-circuit the variations around the reference current are in the order of ±40%. Although this high inaccuracy, the minimum TC results about 10-50 ppm/ • C for V DD ∼ 0.8 V in the temperature range T ∈ [0 − 100] • C.   The schematic shown in Fig. 9a) and b) depicts the adopted trimming network for the proposed CR. The sub-circuit in Fig. 9a)  . It is also worth noticing that ON-resistances of switches, R ON , have been taken into account. On the other side, the sub-circuit in Fig. 9b) compensates for the TC by properly modifying the ratio S 3 /S 4 (see Eq. (12)). After post-layout simulations, it was found out that just two bits are required for this purpose. When B 4(5) is high (B 4(5) is low), M 3A(3B) is connected in parallel with M 3 increasing its aspect ratio; on the contrary, when B 4(5) is low (B 4(5) is high), thanks to switches M B4N (B5N ) the gate of M 3A(3B) is short-circuited to V DD and no current (expect from leakage one) passes through it. In addition, the trimming circuit is driven by B 0 . . . B 5 signals in the range of [0; V DD ] and the negated ones are internally generated by exploiting minimum sized inverters.  Fig. 5, Fig. 6 and Fig. 9. TABLE 3. 6-Bit Binary words used in post-layout simulations for the trimming circuit in Fig. 9a),b).

IV. POST-LAYOUT SIMULATIONS
The layout of the circuit is shown in Fig. 10, where different areas have been enclosed in yellow boxes. It is important to underline that the CR Core area includes also the start-up circuit and the Active Trimming embeds the minimum size inverters for the generation of negated trimming signals, B 4 and B 5 . Fig. 11a) reports the power breakdown of the proposed CR circuit, referring to the static power consumption of the OTA, VOLUME 10, 2022 the reference current, I REF and the left branch of the CR, namely I D1 , since it depends on the current passing through transistor M 1 (see Fig. 5). On the other side, Fig. 11b) shows the area breakdown of circuit referring to the layout reported in Fig. 10. As regard the post-layout simulations, they can be divided in two sets, since they mainly concentrate on the the temperature stability and on the line sensitivity.

A. CORNER ANALYSIS
As it possible to observe from Fig. 12, the TT-corner manifests a TC TT = 13 ppm/ • C over the temperature range T ∈ [0 − 100] • C, while it reduces down to TC * TT = 6.3 ppm/ • C over the temperature range T * ∈ [10 − 90] • C; in both this cases, the power supply is V DD = 0.8 V, but, as can be appreciated from Fig. 12, when V DD = 0.6 V, TC TT = 250 ppm/ • C for T ∈ [0 − 100] • C. Hence, for the higher nominal power supply, the temperature behaviour of the CR meets the typical specification of the more power-wasting BGCRs with 2 nd -order temperature compensation.

B. LINE SENSITIVITY
The second set of results concentrates on the variation of the power-supply V DD . Indeed, Fig. 15 shows that the minimum temperature coefficient for all the five corners is obtained around V DD = 0.8 V, so it is possible to take this last value as the optimum one to guarantee the maximum temperature stability of the proposed CR. As concern the results shown in Fig. 16, they manifest an overall variation of the reference current at room temperature about equal to 4 nA, that is extremely low if compared to  was around 70 nA, from the SS to the FF corner. In addition, it is possible to notice that the line sensitivity for the SS and the SF corner is higher than other cases; this is due to the active trimming circuit, since, in these corners, all the switches are closed, but they are driven by V DD -amplitude signals. By increasing V DD , it will reduce the R ON of switches and, thus, the nominal value of R 1 . This will lead to an increase of the reference current. Nevertheless, it is also possible to change the binary word used for the trimming in Tab. 3 to increase the overall R 1 value.

C. MONTE CARLO SIMULATIONS
Monte Carlo simulations have been executed on the proposed CR to demonstrate the robustness of the implemented system. The results of 200 simulations taking into account global and local variations around TT corner are summarized in Fig. 17. In particular, Fig. 17(left) reports the DC value of the reference current, I REF . The mean value is µ = 99.8 nA, while the standard deviation is σ = 5.12 nA, leading to a relative percentage variation of σ/µ ≈ 5 %. Fig. 17(right) shows the TC evaluated in the range T ∈ [0 − 100] • C. The mean value is equal to µ = 24.7 ppm/ • C, while it not possible VOLUME 10, 2022  to evaluate a standard deviation, since the distribution is not a Gaussian one. On the other hand, it is possible to observe that the minimum and maximum TC value is equal to to 7.6 ppm/ • C and 152.3 ppm/ • C, respectively.

V. COMPARISON
The state-of-the-art comparison is proposed in Tab proposed in [31] is also included in Tab. 5 and Tab. 6 which takes into account the TC and the temperature range, but also the ratio I DD /I REF , where I DD is the overall static current consumption of the CR. The proposed CR shows the lowest FOM (1.2X lower than the best one in the state-of-the-art comparison tables), while maintaining one of the lowest area occupation. Note, however, that the temperature range of the proposed CR it is not the widest one, since it was designed to be used in IMD or in IoT wearable nodes, where the usual temperature is in the range of [0-100] • C (or [10-90] • C). For these properties, it is seen from that the proposed solution is

VI. CONCLUSION
A novel current reference has been introduced in this work. The reference current is generated exploiting the voltage difference of the threshold voltage of MOS transistors operating in weak inversion. Designed in a standard 28-nm CMOS technology, post-layout simulations shows high stability over process, corner and voltage variations thanks to the adoption of an embedded trimming circuit. As highlighted by comparison with the state-of-the-art, the proposed solution is a good 1 It was excluded [26] since it was not declared the area occupation of the proposed circuit. candidate for area-and power-constrained applications, such as IoT sensor nodes and IMDs.
As compared to other solutions exploiting the same principle of operation, the main innovations of the proposed circuit and the contribution of the work can be summarized as follows: 1) the same kind of transistor is exploited in the CR and the adopted technology is the most scaled compared to previous works; 2) the adoption of an OTA in the reference core increases the performance in terms of line sensitivity; 3) a theoretical analysis of the line sensitivity is carried out providing design guidelines to increase the performance; 4) an active trimming circuit is introduced, for the first time in the literature, to simultaneously reduce the effects of process variations on the nominal reference current and the temperature variations leading to a very low TC within the five process corners.