Enhanced Fault-Tolerant Robust Deadbeat Predictive Control for Nine-Level ANPC-Based Converter

Deadbeat model predictive control (DB-MPC) is one of the advanced promising control methods for power converters thanks to its simplicity, high steady-state performance and fast dynamic response. However, the high sensitivity to parameter mismatch and the difficulty of handling multiple control targets are problematic issues in DB-MPC. This work presents an improved robust DB-MPC for a new nine-level ANPC-based inverter. This inverter requires a low number of power devices compared to other single dc-source inverters. Only nine active switches and two discrete diodes are utilized to obtain a nine-level waveform. Without the need for weighting factors, the proposed DB-MPC method tackles three control goals; current control, flying capacitors (FCs) stabilization and dc-link balance, which saves the laborious effort of adjusting the weighting factors in the traditional finite control set MPC (FCS-MPC) method. Moreover, an effective dc-link balancing scheme based on power flow control is proposed and integrated into the FCs control objective. To enhance the control robustness, an EKF-based estimator is designed to identify the system parameters online. In addition, the proposed DB-MPC scheme allows the considered inverter to continue operating with the generation of five levels in the failure condition of the four-quadrant switch, improving the fault tolerance of the inverter. The developed DB-MPC method is experimentally verified in steady-state and transient operation. To demonstrate the excellent performance of the presented DB-MPC scheme, experimental comparisons with other popular MPC methods are performed.


I. INTRODUCTION
Multilevel inverters (MLIs) provide attractive features over traditional two-level inverters, particularly in medium and high voltage/power applications. They have lower voltage stress on power devices, lower switching frequency, lower harmonic content, and higher efficiency [1]. Accordingly, MLIs are considered a cost-effective solution for medium and high voltage/power applications [2], [3]. There are The associate editor coordinating the review of this manuscript and approving it for publication was Alfeu J. Sguarezi Filho . three conventional topologies of MLIs, known as neutral point clamped (NPC), flying capacitor (FC), and cascaded H-bridge (CHB) inverters. The three-level configuration of these topologies have successfully been adopted for various applications according to the merits and demerits of each type [1], [2], [4]. However, in order to generate a higher number of levels from the conventional topologies, some challenges arise, such as the need for a large number of diodes in NPC, a large number of capacitors in FC, and multiple isolated dc sources in CHB inverters. In general, as the number of levels increases, improved waveforms with low harmonic content are achieved, reducing filter size and improving system efficiency. However, the required semiconductor devices and passive components are increased as well.
Hybrid MLIs offer an effective solution to produce a large number of voltage levels with a reduced number of components employed. Several hybrid structures have recently been reported in the literature [5], [6], [7], [8], [9]. Lately, an interesting MLI called nine-level split-capacitor active-neutral-point-clamped (9L-SC-ANPC) inverter was presented in [10]. The single-phase structure of this inverter employs nine power switches, two power diodes, and two FCs. Comparing with classical and recent 9L MLIs, this topology has several merits regarding the required components, conduction losses, efficiency, and overall cost as demonstrated in [10] through a comprehensive comparison. Thence, this inverter is considered in this work.
The control problem of MLIs is typically a multi-objective task, making it challenging with traditional control methods. For instance, considering FC-based MLIs, in addition to regulating the output current, the FCs and dc-link capacitors must also be balanced. Model predictive control (MPC) is considered an attractive alternative to traditional control strategies thanks to its ability to incorporate system nonlinearities and constraints with fast dynamic response [11]. One of the MPC strategies is the finite control set MPC (FCS-MPC). FCS-MPC makes use of the discrete nature of the topology by estimating the available states in a cost function considering the control goals and operational restrictions. Among MPC schemes, FCS-MPC occupies a prominent position because of its key features of being able to handle multiple goals with ease of concept, inclusion of constraints and nonlinearities, and straightforward implementation. However, variable switching frequency and, as a result, distributed harmonic spectrum, and heavy computational burden for high-level topologies are serious concerns of this method [12], [13].
Continuous control set MPC (CCS-MPC) and deadbeat MPC (DB-MPC) are two different types of MPC that offer a constant switching frequency and reduced steady-state error [14], [15]. The first method requires complex mathematical formulations and a digital platform with high computing power, and in some cases solving the control problem offline is inevitable. While DB-MPC significantly reduces the computational load by directly calculating the reference voltage that nullifies the current error at the next sample using the system-discrete model. Then, a modulation stage is used to generate the pulses for switches. DB-MPC cannot process multiple targets during the reference voltage calculation. However, handling multiple objectives is still possible during the modulation stage and is subject to the availability of the redundant states of the converter under consideration.
DB-MPC has been adopted in motor drives with conventional two-level inverters [16], [17], [18], achieving a fast dynamic performance as with FCS-MPC. In addition, compared to FCS-MPC, a much lower computational load is required for DB-MPC because there is no need for switching states evaluation, cost function optimization, or weighting factors tuning. Moreover, thanks to the presence of the modulation stage, improved steady-state behavior has been achieved with a fixed switching frequency. Despite the attractive features of DB-MPC, very few works have been reported in the literature on the application of this method to MLIs. In [19], a dual-vector MPC method based on the DB concept is presented for a CHB rectifier. In this method, the supply current regulation is targeted as a prime control objective, while the capacitors balancing is realized with available redundancies of the CHB converter. However, due to the lack of a traditional modulation stage such as carrier-based PWM (CB-PWM) or space-vector PWM (SV-PWM), fixed switching frequency operation is not realized. The authors in [14] developed a DB-MPC for controlling permanent magnet synchronous motors (PMSM) supplied by a 3L-NPC inverter. To improve the robustness of this approach, the saturation effects of the PMSM were taken into account. In [20], three DB-based MPC methods are reported for three-phase 3L-NPC to reduce the computational efforts of the traditional FCS-MPC. The three schemes depend on calculating the reference voltage using the DB concept to nullify the current error at the next sample. However, cost function optimization and weighting factor tuning are still required. In addition, the switching frequency was not constant, bringing again some of the shortcomings of the traditional FCS-MPC.
Modeling accuracy is quite significant in DB-MPC since the future decision is based solely on the calculated reference voltage, which is estimated according to the system parameters. To address the system parameters mismatch and uncertainties, several estimation approaches have been reported in the literature. In [21], a discrete-time disturbance observer is presented and incorporated into the DB-MPC for a fivephase PMSM to address the machine parameter variation issue. In [22], an online estimator based on an Extended Kalman filter is presented to estimate the filter parameters for a grid-tied modified packed U-cell MLI (MPUC-MLI). The authors in [16] investigated the performance of the traditional DB-MPC for PMSM under system parameters mismatch. Accordingly, an observer based on the sliding mode exponential law was developed to predict the stator currents and track the disturbances resulting from parameter variations.
Influenced by the challenges discussed above, an improved DB-MPC method for a new 9L-SC-ANPC inverter is proposed in this paper, addressing the issues of traditional FCS-MPC such as high computational load, variable switching frequency, weighting factors tuning, and control sensitivity to parameter mismatch. The major contributions of this paper are as follows: 1) A multi-objective low-complexity DB-MPC method is proposed to handle three goals; current control, FCs balancing and NP potential control, 2) A dc-link balancing method is developed and integrated into the FCs balancing by regulating the power transfer in the inverter. This method is suitable for MLIs with a reduced number of switches when the redundancies The rest of the paper is organized as follows. First, the operation and continuous-time model of the 9L-SC-ANPC are presented in Section II. Second, the traditional FCS-MPC is designed considering three control goals in Section III. Third, the proposed DB-MPC method is described in Section IV. Finally, the experimental implementation, results and performance evaluations are presented in Section V.

II. CONVERTER DESCRIPTION AND SYSTEM MODEL
The power circuit of the 9L-SC-ANPC topology is illustrated in Fig. 1. It consists of nine IGBTs, two diodes and two FCs supplied from a common dc-link consisting of capacitors C 1 and C 2 . According to the switching frequency, this topology has two cells, a low-frequency cell consisting of switches S 1 , S 2 , S 3 , S 4 and S 5 and a high-frequency cell consisting of switches S 6 , S 7 and S 8 . It is noteworthy that switches with high switching frequency have a lower standing voltage compared to other power switches, improving the power loss sharing in the inverter. According to the comprehensive comparison in [10], the 9L-SC-ANPC has a low number of power devices and FCs compared to the existing ninelevel topologies. In addition, low conduction losses, high efficiency and low saturation voltage are outstanding features of this inverter as a result of the low number of on-state power devices. Based on its merits, this topology is recommended for low/medium-voltage/power high-efficiency applications.
Presuming that the dc source voltage V dc = 8E and the two FCs C f 1 , C f 2 are well stabilized at E, nine levels can be produced. The switching function s i (i = {1, 2, 3, .., 8}) of switch S i can be defined as  Fig. 1 as where i o represents the current of the 9L-SC-ANPC at the ac side. R and L are the load resistance and the filter inductance, respectively. v o is the ac inverter voltage and is given as a function of the switches states as V c1 , V c2 , V f 1 and V f 2 are the voltages of C 1 , C 2 , C f 1 and C f 1 , respectively. s a , and s b are defined as The FCs model is built according to the inverter states in Table 1 as i f 1 and i f 2 in (5) refer to the currents of C f 1 and C f 1 , respectively, assuming the polarity shown in Fig. 1. Similarly, the dc-link C 1 and C 2 model is given as where i c1 and i c2 are the current flowing in C 1 and C 2 , respectively, as depicted in Fig. 1. Suppose that C 1 and C 2 are identical and have a value of C, the relationship between the capacitors current difference i c = i c1 − i c2 and the voltage difference V c = V c1 − V c2 can be derived as i c can also be expressed as a function of the switches states as

III. TRADITIONAL FCS-MPC
The design of the traditional FCS-MPC is presented here for the 9L-SC-ANPC as a standard MPC method to be compared with the developed DB-MPC. Besides the primary current control objective, FCs balance and NP potential stabilization are included in the control design for the considered inverter. By applying Euler approach as a discretization method [22] to (2) with a sampling period T s , the future current at (k +1) th sample can be obtained as By the same way, the voltages of C f 1 , C f 1 can be predicted by discretizing (5) as Similarly, V c (k + 1) is determined from (7) as Taking into account the l 2 -norm [23], the cost function g is where λ 1 and λ 2 denotes to the weighting factors and are determined by trial and errors to achieve acceptable performance in terms of all goals. i * o (k + 1) in (12) is the reference value i o (k) at (k + 1) th instant and is determined from Lagrange extrapolation [22]. As mentioned before, FCs are maintained at In traditional FCS-MPC, variables prediction and cost function estimation are performed each control period several times equal to the total number of converter states. Accord- , and the cost function g are calculated 12 times each T s according to (9), (10), (11) and (12), respectively, resulting in high computational burden and, therefore, the control execution is time-consuming. Additionally, adjusting the two weighting factors is a cumbersome process as there are no straightforward outlines in the literature for setting the weighting factors. Also, high steady-state error and variable switching frequency are two other major drawbacks of the traditional FCS-MPC. To address these shortcomings, a DB-MPC with the ability to handle the three control targets is developed in the next section.

IV. PROPOSED DB-MPC
Multiple goals handling is one of the distinct features of the traditional FCS-MPC. On the other hand, DB-MPC is usually a single-objective control method. This is an important reason for interpreting the limited application of DB-MPC to MLIs as the control problem of MLIs is typically a multi-objective task. Fortunately, handling several targets in DB-MPC is still possible in the modulation stage if there are sufficient redundancies in the inverter states. However, the MLIs with a reduced number of switches are always accompanied by a reduction in the redundant states, which limits the number of variables that can be controlled. In this regard, MLIs are divided into three types; non-redundant, semi-redundant and redundant converters [24]. Due to the significant reduction in power devices, the considered 9L-SC-ANPC can be classified as a semi-redundant topology since the redundancies are available for only ±2E and 0. Accordingly, the available redundancies are not sufficient to balance both FCs and NP potential with the conventional concept. Thus, the prime current tracking objective is realized from the conventional DB-MPC concept and FCs balancing is realized by exploiting the redundancies. Whereas the dc-link capacitors are stabilized through the power flow control in the converter without requiring further redundancies, as described later.
By adopting Euler method, Equation (2) is written as follows: As discussed before, the first control objective is current tracking, which means generating the inverter voltage that Note that i * o (k + 1) is obtained from Lagrange extrapolation as in the traditional FCS-MPC. Then, the calculated v * o (k) is inputted to the carrier-based PD-PWM stage to generate the pulses. Fig. 2 shows the PD-PWM waveforms.

A. FLYING CAPACITORS BALANCING
As clear in Table 1, there are redundant states for levels ±2E and 0. The zero-level redundancy does not affect the VOLUME 10, 2022 FCs and is therefore used to reduce the number of power device commutations. While the redundancies of ±2E can be utilized to realize the FCs balancing. As can be noticed from Table 1, for ±2E-level states (V 3 , V 4 , V 9 and V 10 ), the effect on C f 1 and C f 2 is the same (charging or discharging). Therefore, based on the voltage deviation of each capacitor, the priority should be first identified. In doing so, the priority P is determined as where V f 1 (k) and V f 2 (k) are the voltage deviations of C f 1 and C f 2 , respectively, and are calculated as Assuming that C f 1 has priority (P=1) and the inverter is generating voltage level +2E, switching state V 3 or V 4 should be applied based on the polarity of the V f 1 (k) and

to charge the capacitor and increase its voltage. To this end, a Heaviside function H (y) is defined as
According to (17), f ( V fi ) is given as Hence, the state of ±2E to be applied is selected as where ⊕ and represent the logical operations XOR and XNOR, respectively. Equation (20) defines the appropriate switching state that reduces the voltage deviation of the FCs based on the direction of i o and the actual FCs voltages. First, after sensing V f 1 (k) and V f 2 (k), the priority is determined based on V f 1 (k) and V f 2 (k) according to (15). Then, taking +2E as an example and assume that the FC with the priority has a voltage lower than its reference ( V fi > 0), V 3 is applied if i o (k) ≥ 0 and V 4 is applied if i o (k) < 0 to charge this FC, as shown in Table 1. The same concept is valid for −2E.

B. DC-LINK BALANCING
Since the 9L-SC-ANPC inverter has a limited number of redundant states due to the significant reduction in the used components and is classified as a semi-redundant topology, the available redundancies are not sufficient to achieve NP potential control in addition to balancing the FCs in the single-phase operation. Therefore, inspired by the concept presented in [10] for traditional CB-PWM, the NP balance is realized in this work by regulating the power transfer in the topology. The NP balance is integrated into the designed DB-MPC method. This approach can be applied to any FC-based MLI. Fig. 3 shows the power supplied from the dc-link to FCs and the ac side (ac load) during an entire sinusoidal cycle. According to the power flow analysis, it is clear that during the positive half-cycle, the upper capacitor C 1 provides power P 1f to the FCs and P 1 to the ac load, whereas C 2 takes over the power feed task in the negative half-cycle with providing powers P 1f and P 1f , as shown in Fig. 3b. Accordingly, the total power supplied by the dc-link is the summation of the power P c1 from C 1 and the power P c2 from C 2 . P c1 and P c1 can be expressed as From (21), it is clear that the energy provided by C 1 can be regulated by P 1f of the FCs. Likewise, the power P 2f affects the total energy provided by C 2 . Note that, P 1f and P 2f can be controlled via the reference value V * f . Accordingly, to control the NP potential, V * f need to be estimated in each half-cycle based on V c1 and V c2 . For clarification, if V c1 > V c2 , V * f is increased in the positive half-cycle to increase P 1f and draw more energy from C 1 , and is reduced in the negative part of the cycle to reduce P 2f . As a result, V c1 will decrease V c2 will increase. According to that, V * f is estimated as where β is the ratio of the FCs voltage to the dc-link capacitor voltage in the balancing operation, β = E/4E = 0.25. The calculated value of V * f (k) according to (22) is then used in (16) to include the NP stabilization in the FCs balancing.

C. OPERATION UNDER FAULT CONDITION
One distinct feature of the 9L-SC-ANPC topology is the capability to operate with different number of levels. By exploiting this feature, the control is designed to enable the inverter to continue operating even in a failure condition of the four-quarter switch S 8 . According to Table 1, there are 12 states in the normal operation allowing the generation of nine voltage levels. However, if an open circuit fault occurs in S 8 , the healthy switching states will be reduced to only eight. Whereas V 2 , V 5 , V 8 and V 11 in Table 1 will be faulty states. In this case, the FCs C f 1 and C f 2 are connected in series, forming one capacitor with a value C f and voltage V f , where C f and V f are given as with regulating C f at V dc /4 (2E), five levels (±4E, ±2E, 0) can be obtained from the 9L-SC-ANPC. The switching states and produced levels in this case are shown in Table 2.
To include the NP control, the reference voltage of C f is calculated from (22) with a different value of β according to its definition, where β = 2E/4E = 0.5. It should be mentioned that the transition from the healthy operation to the faulty condition is realized by the controller with no transient time as the FC C f is balanced at the same voltage (2E assuming a balanced NP potential) in both conditions. Since there is only one FC, no priority check according to (15) is required. After calculating the new V * f (k) by (22) with Subsequently, the redundant states of ±2E in Table 2 can be identified as

D. MODEL PARAMETERS ESTIMATOR DESIGN
Since the future decision in the DB-MPC depends only on the calculated reference voltage, the modeling accuracy is considered quite significant. A slight variation in the model parameters due to ageing or thermal effects can lead to a deterioration of the system performance. To deal with this matter, an EKF-based estimator is developed to identify the filter and load parameters (R, L).
To design the EKF-based estimator, the state-space model should be first established in the discrete-time form. The continuous-time state-space model including disturbances is represented asẋ where x = (i o , R, L) T is the state vector, u = v o is the system input, and y = i o is the output. A, B, C, and D represent the system matrices. While w and v refer to the model uncertainties and noises related to measurements, respectively. w and v have covariance matrices represented by Q and R, respectively. The entries of Q and R are determined using the particle swarm optimization (PSO) method [25] as they have a crucial influence on the estimation accuracy. For the considered system in Fig. 1, A, B For discretization, forward Euler approach is applied to (26), which results in (28) are defined as The implementation of the EKF algorithm is depicted in Fig. 4 and can be summarized in steps as follows 1) Initialization of state vector x 0 = x(0) and covariance matrices Q and R. 2) Prediction phase a) State predictionx − (k), b) Error covariance matrix prediction P − (k), where J (k) is the Jacobian matrix and written as According to the system model, J (k) is expressed as 3) Kalman gain K (k) computation, 4) Correction phase using measurements a) State vector update, 5) Go to step 2. The flowchart of the proposed DB-MPC method is shown in Fig. 5. Since the FCs balancing is realized using the available redundancies in PWM-based schemes, the operation at low line frequencies is limited with the proposed DB-MPC method due to the low number of redundant vectors in the 9L-SC-ANPC inverter. Accordingly, this inverter is recommended for grid-connected applications, where operation at low line frequencies is not required, as discussed in [10].

V. EXPERIMENTAL RESULTS
For the experimental validation, three distinct MPC methods are experimentally implemented and compared under the same operating conditions, which are defined as follows. The first method is the traditional FCS-MPC algorithm, detailed in Section III. The second method is the single-predictive FCS-MPC. This method is first proposed in [26] for the conventional two-level converter and the 3L-NPC converter to eliminate the computational load required for the current prediction in FCS-MPC. Due to its high performance and low computational load, this concept is then applied to various converter topologies such as the 5L-ANPC inverter in [12] and the 3L T-type converter in [27]. To eliminate the calculation efforts required for the current prediction in this approach, the reference voltage that obliges i o to follow i * o at (k + 1) th sample is estimated by (14). Then, the current tracking objective is expressed in terms of voltage instead of current. Accordingly, the cost function in (12) of the traditional FCS-MPC is modified as follows: where λ v1 and λ v2 are two weighting factors. Note that instead of 12 × current predictions in traditional FCS-MPC, this method estimates the reference voltage only once per sample, so it is called single-predictive FCS-MPC. However, it is still required to perform 12 × predictions for the FCs and dc-link voltages and 12 × cost function evaluation. The third implemented method is the DB-MPC proposed in this paper. Fig. 6 shows the experimental setup used in the validation. A dSPACE Microlabbox is used as a digital controller to implement the two control methods. The parameters of the experimental implementation are provided in Table 3. The    delay compensation method presented in [28] is adopted in the validation.
As previously discussed, the weighting factors λ 1 and λ 2 in traditional FCS-MPC and λ v1 and λ v2 in singlepredictive FCS-MPC should be first tuned. For a fair and meaningful comparison with multiple control objectives, λ 1 , λ 2 , λ v1 , and λ v2 are tuned to give the same voltage ripples in the FCs and dc-link as in the DB-MPC method. Subsequently, the comparison can be assessed in terms of the current tracking as a prime control target. Considering the experimental parameters in Table 3 and i * o =8 A, λ 1 , λ 2 , λ v1 , and λ v2 are determined by trial and errors and found to be 0.25, 0.06, 2700, and 450, respectively. Under these values, the three MPC methods have voltage tolerances of 3.5 V and 5 V in FCs and dc-link capacitors, respectively.

A. STEADY-STATE AND DYNAMIC OPERATION AT NOMINAL SYSTEM PARAMETERS
For a fair comparison, the same average switching frequency f s should be adopted for the MPC methods under consideration [29]. f s of the 9L-SC-ANPC converter is calculated as where f si is the average switching frequency of switch S i , with i ∈ {1, 2, 3, 4, 5, 6, 7, 8}, and is calculated based on the number of commutations n si in the period T c as f si = n si /T c [27]. The proposed DB-MPC method is validated experimentally at T s = 50 µs and carrier frequency f c = 5 kHz. According to (38), f s of the DB-MPC is found to be 2 kHz. For the traditional and single-predictive FCS-MPC methods, a sampling period T s of 65 µs is chosen to result in the same average  switching frequency, f s = 2 kHz. Fig. 7 shows the experimen- The spectrum of the current harmonics is shown in Fig. 8. As can be seen, all MPC methods have very low THDs, valued at 2.92%, 2.94%, and 2.35% for the traditional, single-predictive FCS-MPC, and the proposed DB-MPC, respectively. However, the harmonics in the traditional and single-predictive FCS-MPC methods are distributed over a wide frequency range, making filter design for grid-tied applications a challenging task. In contrast, for the DB-MPC method, the harmonics are concentrated at the carrier switching frequency and its multiples (f c , 3f c , 5f c ). Fig. 9 depicts the harmonics spectrum of v o . Although the THD v of the DB-MPC is slightly higher than that of FCS-MPC, it is concentrated at f c and its multiples, which can be easily filtered, in contrast to the FCS-MPC. For a clear and supported performance assessment, Table 4 lists three performance indicators for all methods, which are the mean absolute current error e i [29] and the total harmonic distortion THD i and THD v of i o and v o , respectively. According to Table 4, the developed DB-MPC method has better values in terms of e i and THD i . To examine the transient operation, Fig. 10   IGBT and IDP30E65D1 diode manufactured by Infineon are utilized with the thermal and losses description provided by the manufacturer. The resulting switching P sw and conduction P con losses are given in Fig. 11. Note that the four-quadrant switch S 8 consists of two power devices, denoted as S 1 8 and S 2 8 . From Fig. 11, one can observe that the conduction losses of the power devices are much higher than the switching losses in all MPC schemes. In addition, the three MPC schemes have a very similar loss distribution, which can be interpreted as operating at the same average switching frequency. According to the loss analysis under the same conditions, the efficiency of the traditional, singlepredictive FCS-MPC, and the DB-MPC is 98.93%, 98.91%, and 98.90%, respectively. An important observation from the power loss analysis is that the four-quadrant switch has the highest power loss compared to other switches, where S 1 8 and S 2 8 have about 32% of the total losses in the 9L-SC-ANPC inverter. This confirms the feasibility of the suggested DB-MPC strategy to ensure converter operation under the failure condition of the four-quadrant switch.

B. OPERATION UNDER PARAMETER MISMATCH AND EKF-BASED ESTIMATION
In this test, the robustness and the estimating ability of the EKF-based estimator with variations in parameters R and L are investigated. For the traditional and single-predictive FCS-MPC, the system model assumes constant parameters equal to the nominal values R n and L n . While for the proposed DB-MPC, the model parameters used in the control algorithm are estimated using the designed EKF-based estimator and denoted asR andL. The variation of model

parameters ( R, L) is defined as
where R act and L act refer to the real values of the load resistance and filter inductance, respectively. Fig. 12 shows the experimental results for the change of the real system resistance between the nominal value (22 ) and another value (14.7 ), with a change percentage of 33.3%. As can be observed, for the proposed DB-MPC, the estimated resistancê R follows the actual valueR with a fast dynamic response and very low steady-state error. As a result, the control has high tracking quality in terms of current control despite the significant change in R act . While for other FCS-MPC methods, due to the mismatch between R act and R n , a steadystate error is observed in the current. The control performance in this case in terms of e i , THD i and THD v is summarized in Table 5. The control performance with filter inductance variation is depicted in Fig. 13, where L act is varied from 6 mH to 2.4 mH ( L = −60%). As can be seen, the designed EKF-based estimator can accurately estimate the actual filter inductance, resulting in an acceptable control performance even with a −60% reduction in the filter inductance. For FCS-MPC, very high ripples are observed in the current and also the inverter voltage is highly distorted. The considered performance indicators are summarized in Table 6, which shows a clear superiority of the proposed DB-MPC over traditional and single-predictive FCS-MPC methods.
C. PERFORMANCE EVALUATION AT THE SAME CONTROL PERIOD T s As discussed in Section V-A, The performance of the MPC methods is compared at the same average switching frequency f s , which necessitated the implementation of the  traditional and single predictive FCS-MPC methods at T s = 65 µs to get f s = 2 kHz as in the proposed DB-MPC method. In this section, the performance is compared at the same control period by experimentally implementing the traditional and single-predictive FCS-MPC methods at T s = 50 µs. Fig. 14   execute algorithm sub-parts is also measured through atomic subsystems. The measured times of the three MPC methods are listed in Table 8  traditional method, where 11.1 µs is required for the whole developed DB-MPC method compared to 11.3 µs for traditional FCS-MPC.

E. OPERATION UNDER THE FAILURE OF THE FOUR-QUADRANT SWITCH S 8
As theoretically discussed, with the proposed DB-MPC, the 9L-SC-SNPC can continue to operate even in a failure condition of the four-quarter switch S 8 . In this test, the operation is experimentally verified with an open-circuit fault in S 8 . Fig. 15 shows the experimental results for this case. As can be   seen, in normal operation, the inverter produces a nine-level voltage waveform, and when a fault occurred in S 8 , the 9L-SC-ANPC was directly changed to the five-level mode with no transient time because the FCs were still stabilized at the same voltage. C f 1 and C f 2 are seen as on capacitor with a voltage V f balanced at V dc /4 (100 V). It is also clear that the dc-link capacitors are well balanced in all cases. The operation is also experimentally validated in the five-level mode with a step-change in i * o from 8 A to 4 A in Fig. 16. The results prove the ability of the proposed DB-MPC with the 9L-SC-ANPC topology to operate with a faulty state of S 8 in steady-state and dynamic operation. As expected, due to the reduction of the voltage levels to five, an increase is observed in the tracking errors and harmonic contents compared to the nine-level normal operation, where e i , THD i and THD v were found to be 3.10%, 4.25% and 35.10%.

VI. CONCLUSION
In this article, an improved robust DB-MPC method was developed and applied to a recently proposed nine-level inverter. The proposed method is suitable for single-phase ANPC-based MLIs. From the theoretical investigations Although the operation of the 9L-SC-ANPC is ensured under the faulty case of the four-quadrant switch S 8 , it is suggested to investigate the operation under the fault conditions of other power switches in future work. In addition, the operation at low line frequencies is recommended to be considered in future work with ensuring the FCs and dc-link balance.