A High Step-Up Interleaved Current-Fed Resonant Converter for High-Voltage Applications

A current-fed LLC resonant converter is proposed for high-voltage and high-power applications. Here, a two-phase interleaved structure is used in the input stage under the continuous conduction mode (CCM) to effectively reduce the input current and output voltage ripple values and the input filter and the output capacitors volumes. Due to the expandable structure and high voltage gain, the proposed configuration is suitable for high voltage applications since low voltage stresses are applied across its components. In fact, voltage stresses across the power semiconductors, i.e., MOSFETs and output diodes, along with the output capacitors, are almost one-third of the output voltage in the implemented three-stage configuration of the proposed converter. Here, the switching frequency is chosen close to, but less than, the converter series resonant frequency to reduce its different components’ current stresses and perform soft-switching operation for all power devices under wide input voltage and output power variations. Therefore, conduction and switching losses, and EMI noises are effectively reduced. Consequently, efficiency is improved and high-frequency operation is possible, which reduces the volume of passive components to achieve high-power density. The given topology is thoroughly analyzed mathematically. Also, a 1 kW prototype converter has been implemented to validate the given simulations and analyses. Here, wide input voltage (100 V-200 V) and output power (100 W-1000 W) variations are applied, and an asymmetric pulse width modulation (APWM) technique is used at 143 kHz switching frequency to regulate the output voltage at 1 kV. The obtained maximum efficiency value is 95.3%.


I. INTRODUCTION
Recently, renewable energy sources have been regarded as a solution to the environmental issues [1], [2]. Since depletable energy sources mostly have low and fluctuating output voltage, using a dc-dc step-up power converter is indispensable to both level up and regulate their output voltages [3], [4]. Till now, various converters such as high step-up, high voltage, interleaved, and resonant converters have been introduced to increase voltage gain, output voltage, and output power of the dc-dc converters. The given converters in [5], [6], [7], and [8] that have been introduced for high voltage The associate editor coordinating the review of this manuscript and approving it for publication was Kan Liu . applications usually use large transformers turn-ratios to obtain high voltage gains, which in practice increase voltage stresses on some output stage components.
On the other hand, although the transformer turn ratios in most of the high step-up converters [4], [9], [10], [11], [12], [13] are lower than the previously referred ones, they still use large transformer turn ratios to obtain high voltage gains. Consequently, these converters also suffer from similar disadvantages, as mentioned earlier. In some other converters [14], [15], where the transformer turn ratios are small, lower voltage gains are obtained in practice.
Interleaved structures [2], [16], [17], [18], [19], [20], [21] are another large category of converters, which are proposed to increase output power, but they often give small output VOLUME 10, 2022 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ voltages, and they are not suitable for high voltage applications. Some of these converters have been used as PFC converters [22], [23], [24]. On the other hand, among the different isolated and nonisolated dc-dc topologies, the full-bridge converter is preferred in many pieces of literature [18], [25], [26], [27], [28]. The soft switching operation is achievable for this converter by phase-shifting without using auxiliary circuits. But, the soft-switching range in conventional phase-shifted fullbridge (PSFB) converter is limited due to the loss of zero voltage switching (ZVS) for primary switches in worstcase conditions. Also, circulating currents power losses are high [29]. Albeit using additional circuits may widen the softswitching range [30], [31], [32], [33], it leads to higher components count and cost. Resonant-type full-bridge converters can realize soft-switching operation by using resonant tank on the primary side, which can improve the efficiency by eliminating MOSFET-based [28], [34] and IGBT-based [35] converters' turn-on and turn-off switching losses, respectively.
Another one of the most widely used converters is LLC-based resonant converters, which have received much attention from researchers and industry in recent years due to their good features. These resonant converters have low electromagnetic interference (EMI), and they can provide ZVS condition for primary MOSFETs and zero current switching (ZCS) turn-off condition for output diodes when they operate between series-resonance and parallel-resonance frequencies [36], [37]. Moreover, by paralleling small capacitors to the drain-source of MOSFETs, their turn-off switching losses can be reduced [38], [39]. The LLC resonant converter is widely used in practice in many applications such as renewable energy systems [40], [41], on-board chargers [42], [43], light-emitting diodes (LEDs) [44], [45], and power factor correction (PFC) [46]. To regulate the output voltage of the LLC-based resonant converters, several methods such as Pulse Frequency Modulation (PFM), Phase Shift Modulation (PSM), Pulse Width Modulation (PWM), Asymmetric PWM (APWM), or hybrid modulation strategies like PFM + PWM and PFM + PSM can be utilized [26]. In the PFM strategy that operates based on the resonant tank impedance modification, a wide frequency range is used to regulate the output voltage. So, optimal designs of transformer(s) and inductor(s) are a challenge [47]. Besides, in the PSM strategy, the lagging leg soft commutation may also be lost under the light-load conditions [48].
Interleaving the primary current fed stages and stacking the output rectifiers stages of series-based [19] or LLCbased [55] resonant topologies is a good approach to increase the converter voltage gain, output voltage, and power values. However, many components must be used in these topologies, which in practice reduce the converters' reliabilities and increase their costs.
Finally, it should be mentioned that [7] is a good configuration for high-voltage high power applications, but its VM rectifier stage needs more capacitors, and lower voltage gain is achieved as compared to the given one here, which has a continuous input current with small ripple value instead of a pulsating current waveform.
Here, a high step-up interleaved current-fed LLC resonant converter, suitable for high-voltage high-power applications, is introduced. Low input current and output voltage ripples values, as well as soft-switching operations, are performed under wide input voltage and output power variations by using the well-known asymmetric PWM (APWM) technique to control the output voltage. So, low EMI, high efficiency, high frequency operation, and high power density are practically achievable.
The proposed converter is introduced in Sec. II and its key waveforms and different operational states are given in Sec. III. Then, its steady-state and dead-time analyses are given in Sec. IV and V, respectively. Next, the resonant tank components are calculated in Sec. VI. Also, output stage capacitors values are derived in Sec. VII. Finally, experimental results and conclusions are respectively given in VIII and IX.

II. PROPOSED CONVERTER
The proposed converter with full-bridge topology, suitable for high-power applications, is shown in Fig. 1. This converter current-fed interleaved structure reduces the input current ripple, as well as the input filter volume. The LLC resonant circuit is employed, among existing resonant topologies, due to its excellent features such as soft switching operation of all primary stage switches and output stage diodes even under the wide input voltage and output load variations, low EMI, high efficiency, high power density, low circulating currents, and so forth. A full-wave rectifier is used for each output stage to reduce each diode voltage and current stress. Also, the outputstage diodes and capacitors voltages stresses can be reduced by adding more stages. So, the proposed converter can be used for high-voltage applications. Here, two small capacitors are connected in parallel to M a 1 and M b 1 MOSFETs to reduce all power MOSFETs' turn-off switching losses. Furthermore, the output voltage is regulated by the APWM technique at a desired fixed switching frequency. As a result, unlike pulse frequency modulation (PFM), magnetic components can be designed more efficiently.

III. PROPOSED CONVERTER KEY WAVEFORMS AND ITS DIFFERENT OPERATIONAL STATES
The fundamental waveforms of the proposed converter are plotted in Fig. 2. Based on these waveforms, the proposed converter has eight different operational states during a switching period for a three-stage configuration, as depicted in Fig. 3. These states are summarized as follows: State I [t 0 -t 1 ]: at the beginning of this interval, the body diode of M a 2 begins conducting. Therefore, this power switch can be turned on under ZVS condition, as shown in Fig. 2. Diodes D a 2,4 and D b 1,3 also start conducting current from zero by increasing their currents sinusoidally. Here, D a 2,4 and D b 1,3 are conducting and delivering power to the load during this interval, M b 1 is also conducting current and M a 1 , M b 2 , D a 1,3 , and D b 2,4 are all off, as shown in Fig. 3(a). This state ends after M a 2 is turned off. The resonant tank capacitor voltage and inductors current waveforms are respectively given as follows: where, State II [t 1 -t 2 ]: during this interval, M b 1 continues to conduct current, but M a 2 is turned off with small switching losses due to the presence of its drain-source equivalent parasitic capacitance, its fast gate drive signal, and a properly selected dead-time value. In addition, the output stage diodes are switched off under ZCS condition. Therefore, the reverse recovery issue is simply overcome. The conducting states of the different components of the converter are shown in Fig. 3 : at the beginning of this interval, the body diode of M a 1 starts conducting current after discharging its drain-source capacitance at the end of the previous state. Therefore, M a 1 can be switched on under ZVS condition. M b 1 is still conducting, but M a 2 and M b 2 are off. Since, the transformer magnetizing current reaches the resonant inductor current, no current passes from the primary side winding to the secondary and third windings. As a result, the output diodes are off and the output load is fully powered by the output capacitors. The conducting states of the converter components are shown in Fig.3(c). The resonant tank capacitor voltage and inductors currents can be given as follows: where, State IV [t 3 -t 4 ]: during this state, the body diode of M a 1 continues to conduct current, but M b 1 is turned off with small switching losses, as previously explained for M a 2 during operational State II. All output diodes are still off, and the load is still powered by the output capacitors, as shown in Fig. 3(d). During the next half-switching period, the different operating states of the converter are the same as previously described for States I-IV, but in the opposite direction. Also, the operating states for D < 0.5 are the same as described for D > 0.5, but there are two simple differences.
For D < 0.5, M a 2 and M b 2 gate-source signals overlap, in contrast to D > 0.5, where the gate-source signals of the lower switches, i.e., M a 1 and M b 1 overlap. States III and IV are depicted in Fig. 4 for D < 0.5. States VII and VIII are similar to States III and IV, but in opposite directions.

IV. STEADY-STATE ANALYSIS OF THE CONVERTER
To simplify the analysis of the steady-state behavior of the converter, following assumptions are considered: 1) During a switching period, voltage ripples of the output capacitors (i.e., C out 1 − C out m ) are ignored.
2) The primary stage switches and the output stage diodes are considered ideal.
3) Both input inductors are the same (L a = L b = L). 4) Two non-dominant operational States of II and IV are ignored first, but the converter behavior during the deadtime is separately analyzed in more details later. 5) Different turns ratios of the transformer are considering being the same, i.e., N 2 N 1 = · · · = N m N 1 = n.

1) VOLTAGE STRESSES OF THE OUTPUT CAPACITORS
By applying the volt-second balance principle to one of the input inductors, voltage across C out 1 is derived.
Thus, voltages of the other capacitors can be identified.
where, m is the number of the stages of the converter.

2) INITIAL RESONANT INDUCTOR CURRENT AND RESONANT CAPACITOR VOLTAGE
By ignoring the non-dominant operational States, i.e., II and IV, the following equations set can be derived during a half switching period: Furthermore, since non-dominant operational states are ignored, the following expressions can then be derived: where, i L m 1 , v C r 1 and i L m 3 , v C r 3 are the magnetizing inductor current and resonant capacitor voltage during operational States I and III, respectively. By using (10)- (12), the resonant inductor current and capacitor voltage initial values, i.e., i L r (0) and v C r (0), are derived as: where the given coefficients are calculated as follows: Here θ x , θ y , λ, and F parameters are given as follows:

A. CONVERTER VOLTAGE GAIN
Voltage gain of the proposed converter can be derived by calculating the average output current value as follows: VOLUME 10, 2022 By substituting (2), (3), (8), (9), (13), and (14) into (23) and doing some straightforward algebraic calculations, the converter voltage gain is derived, given by as in (24), shown at the bottom of the page. Here, R N = R L Z 0 is the normalized output load resistance value. (24) clearly shows that the converter voltage gain depends on the converter duty cycle, normalized output load, and normalized switching frequency.
Since the output voltage regulation by varying switching frequency can cause some problems such as inefficient design of magnetic components and also efficient usage of parasitic components of the transformer is a challenge by employing this approach [4], [56]; therefore, the APWM approach is used here to regulate the output voltage.
To identify the necessary duty cycle variations for regulating the output voltage at a desired switching frequency when both input voltage and load variations are applied to the converter, the normalized output voltage is defined as follows: Here, V in N is the normalized input voltage and V b is defined as: Using (25), the converter normalized output voltage has been plotted in Fig. 5 under the two worst-case conditions, i.e., (a) minimum input voltage and minimum output load resistance and (b) maximum input voltage and maximum output load resistance. Fig. 5(a) depicts three-dimensional normalized circuit voltage gain versus normalized load resistance, R N and duty cycle. The intersections of the desired normalized output voltage value with the two other normalized output voltage curves under the worst-case conditions, shown in dashed lines, specify the duty cycle variations to regulate the output voltage when wide input voltage and output power variations are applied to the converter. Here, the duty cycle should theoretically vary from 0.3 to 0.75 to regulate the output voltage, as it is depicted in Fig. 5(b).

B. MINIMUM AND MAXIMUM VALUES OF THE INPUT INDUCTORS CURRENT AND THE CONVERTER INPUT CURRENT RIPPLE VALUE
The input inductors current for D > 0.5 are shown in Fig. 6. Considering these waveforms, the L a inductor current during a switching period can be expressed as follows: By substituting (8) into (27), using average value of i in = V out I out ηV in and i in = i L a + i L b , and doing some algebraic calculations, the minimum and maximum values of the input current are derived as follows: where η and M are the efficiency and voltage gain of the converter, respectively. Since a two-phase interleaved structure is used at the primary side of the proposed converter, the input current ripple is minimized because the inductors currents are the same, but 180 degrees out of phase, as shown in Fig. 6. It should be noted that when D = 0.5, the inductors currents cancel out each other ripples; thus, the converter has a ripple-free input current under this condition. In addition, when the proposed converter operates under the CCM conditions, the inductors current ripple values as well as the converter input current ripple are further reduced. Therefore, a smaller input filter can be used. Both inductors current  ripple values are the same and can be calculated as follows: Calculating the ratio of the converter input current ripple value to each of its input inductor current ripple values, i.e., i in to i L , it can be shown that how much the input current ripple value decreases with respect to the values of the inductors currents ripples values in the given interleaved structure.
By substituting (29) into (30), the normalized input current ripple of the interleaved two-phase structure can be derived as: Based on (31), some curves are plotted in Fig. 7, where Fig. 7(a) illustrates the normalized input current ripple versus different duty cycles and normalized output resistance load values. This figure clearly shows that the input current ripple value increases by increasing the output power value. In addition, when the duty cycle deviates from D = 0.5, then the input current ripple increases. Therefore, to minimize the input current ripple, the converter should operate around D = 0.5 under full load conditions. Fig. 7(b) shows the normalized input current ripple versus λ. Because λ has a little effect on the normalized input current ripple value, as shown in Fig. 7(b), using large magnetizing inductor value is preferred to minimize the circulating currents and conduction losses.

V. DEAD-TIME ANALYSIS
Although turn-on switching losses of the MOSFETs of the proposed converter are almost eliminated due to their ZVS operation, their turn-off switching losses are still remaining. To decrease these switching losses, small capacitors may be connected in parallel with the MOSFETs' drain-source [39], [57], [58], in addition to their parasitic capacitances, by turning them off fast and properly considering dead-time subintervals. These switching losses are effectively reduced by increasing the abovementioned capacitances, even when the minimum input voltage is applied to the converter and maximum power is delivered to the load, which is the worstcase condition for turn-off switching losses of the MOSFETs. However, using higher capacitances lead to a narrower ZVS operation range because larger currents are required to fully charge/discharge these capacitors to provide the ZVS condition. Thus, ZVS operation may not be fulfilled under the light load conditions, especially when the maximum input voltage is applied to the converter. This is also a worst-case condition to fully charge/discharge the MOSFETs parallel connected capacitors during the dead-time subintervals to realize the ZVS operation. Consequently, a proper trade-off between reducing the turn-off switching losses and providing the ZVS condition for reducing the turn-on switching losses must be addressed here for the abovementioned worst-case conditions to overcome this issue in practice. Fig. 8 shows the operational State II, occurring due to the considered dead-time subinterval. Therefore, maximum capacitance value, C S , can be identified as follows: By keeping in mind that i L r (t 2 ) = i L m (t 2 ) and using (3), (9), (16), (28), and (32), the maximum capacitance value of C S can be calculated as follows: Here, T is the dead-time value which can be obtained from the datasheet of the used power MOSFET by considering some parameters such as rise and fall times, turn on and off delay times, and body-diode reverse recovery duration time [59].

VI. CALCULATING THE RESONANT TANK COMPONENTS VALUES
Here, a simple approach is used to calculate the converter components values. V C out 1 is approximately applied to the transformer primary winding because the converter operates near its series resonant frequency. Therefore, the transformer turns ratios can be approximated as follows: So, the transformer turns ratios can easily be identified. Since the output stage capacitors with the same voltages stresses are preferred in practice, the transformer unity turns ratios are considered here. Considering Fig. 9, voltage of C r changes from minimum to maximum value during t x to t z time duration and these values are respectively occurringwhen i D b 1 (t x ) = i D a 1 (t z ) = I out during States I and IV. Therefore, Substituting (2), (3), (13), and (14) into (35), t x and t z can be obtained numerically. Consequently, peak-to-peak voltage variation of C r is obtained as follows: Doing some algebraic calculations, V C r can be calculated as expressed in (37), shown at the bottom of the next page.
Here, different parameters are given as follows: Considering (38), and substituting (4) and (7) into (37), C r can be identified numerically from (37) for given voltage ripple value under the worst-case condition. Then, for given resonant frequency, L r is also simply identified from (4).

VII. CALCULATING THE OUTPUT STAGE CAPACITORS VALUES
To limit the output voltage ripple value, the output stage capacitors values must be chosen properly. Fig. 10 shows the different output capacitors voltages ripples and currents waveforms for D > 0.5 during a switching period. Considering these waveforms, the capacitors voltages ripples are calculated. As illustrated in Fig. 10, V C out1max is occurred at t y , which can be identified as follows: Therefore, peak-to-peak voltage variations of C out 1 is identified. where, Moreover, V C out 2,··· ,m varies from its minimum to maximum value during t x to t p . Therefore, peak-to-peak voltage variations of V C out 2,··· ,m is obtained as follows: Also, t p can be approximated as follows: Now, for the given voltages ripples values, the output stage capacitors can be identified by considering (40) and (VII). Finally, it must be mentioned that voltage stresses of all power MOSFETs are equal to V C out 1 . Also, each stage output capacitor and diodes voltage stresses are the same. Since all output capacitors voltages are almost equal, consequently, all power diodes voltage stresses are also the same. Therefore, each MOSFET, diode, and capacitor voltage stress can be identified.
The converter stages number can be identified easily by considering the available devices volt-ratings and the desired output voltage values properly. Because the converter devices entirely operate under the soft switching conditions over wide input voltage and output power variation ranges, the conduction losses are dominant components of the converter losses. Thus, to reduce the converter conduction losses and to improve its efficiency, low volt-rating devices are preferred. Therefore, a trade-off between efficiency, cost, and complexity of the converter must be done to properly identify the converter stage number in practice.

VIII. EXPERIMENTAL RESULTS
To confirm the theoretical analyses of the proposed converter, a 1 kW prototype converter has been implemented, as shown in Fig. 11. The implemented converter can step up wide input voltage variation ranges (100-200 V) to be regulated to 1000 V at the output port. Also, its output power varies in a wide range (100 W-1 kW). Here, unlike the conventional LLC resonant converter, where the minimum switching frequency determines the sizes of the converter's magnetic devices, the switching frequency is fixed at f s = 143 kHz, and the output voltage is regulated by the APWM method, as mentioned before. Therefore, the converter's magnetic components used in the input filter, resonant inductor, and multi-winding transformer can be designed more appropriately. The specifications of the main parameters of the prototype converter are given in Table 1. Here, the gate driver  signals are generated by a STM32F334R8 board. The steadystate experimental waveforms for two worst-case conditions, i.e., V in = 100 V , P out = 1 kW and V in = 200 V , P out = 100 W are given. Figs. 12 and 13 show the ZVS operation of the primary stage MOSFETs for the two worst-case conditions, respectively. Like the other resonant converters, to realize ZVS operation, the resonant tank network input current waveform must be lagged properly compared to the output voltage of the switching network [60]. Consequently, by turning on M a 1 MOSFET, for instance, the converter current fully discharges the parallel connected C S 1 capacitor during the dead-time. Then, anti-parallel body-diode D M a 1 is forward-biased and starts conducting the current. So, M a 1 power MOSFET can be turned on a short time later under the zero-voltage condition without having switching losses. To realize the ZVS operation, each power MOSFET anti-parallel body-diode must first conduct the current. This means that each power MOSFET current waveform must have a negative part before turning it on by the control circuit, which passes through the anti-parallel body-diode of the MOSFET in the reverse direction, as clearly marked with a dashed curve in Figs. 12 and 13. As shown in Figs. 12 and 13, all MOSFETs' drain-source voltages reach zero before applying their gate-source signals under the given two worst-case conditions. So, all MOSFETs turn-on switching losses are effectively eliminated due to their ZVS operation. Switching losses of the MOSFETs are illustrated by the bottommost waveforms of the different parts of Figs. 12 and 13, too.
Also, the bottommost waveforms of Figs. 14 and 15 clearly show that the output stage diodes turn-off switching losses are effectively eliminated due to their ZCS operations that significantly alleviate their reverse recovery problem. Therefore, the soft-switching operation is guaranteed for all power switches of the proposed converter in all input voltage and output power variations ranges. It means that high efficiency, low EMI noises, and high switching frequency operation are achievable. Consequently, high power densities can be realized in practice. Fig. 16 shows the input inductors currents and the converter input current waveforms under the abovementioned two worst-case conditions. Due to the converter interleaved structure, its input current ripple value is effectively lower than both input inductors current ripple values, as clearly illustrated in Fig. 16. Also, the input current frequency is twice the frequency of both input inductors current waveforms, which is effectively reducing the input filter volume. Fig. 17 shows the resonant tank inductor current and capacitor voltage waveforms under the abovementioned two worst-case conditions when the output oltage is 1 kV. Also, Fig. 18 shows the different output stage capacitors voltages as well as the converter output voltage waveforms under the two worst-case conditions. This clearly illustrates that the output voltage is almost equally divided between the output capacitors. Thus, these capacitors, as well as the output stage diodes, experience the same voltage stresses, even when more stages are used to employ either lower volt-rating devices or to achieve higher output voltage values in practice. Also, Fig. 19(a) shows the converter's different efficiency curves versus output power for different input voltages. Besides, Fig. 19(b) depicts the loss distribution of the proposed converter. Based on Fig. 19(b), although the dominant switching losses of the MOSFETs are eliminated due to soft-switching, most of the    100 W (a) D a 1 , D a 3 , D b 2 , and D b 4 , and  (b) D a 2 , D a 4 , D b 1 , and D losses are related to the conduction losses of the MOSFETs. Thus, by selecting switches with a lower r ds on higher efficiencies can be achieved. To gain a deeper insight about this issue, the proposed converter is compared with the most similar converters in Table 2. Although some better efficiencies have been reported in the literature, this is mainly due to their used components with lower conduction losses and switches  with lower on-state resistances, as clearly given in Table 2. Based on Figs. 12-15, the dominant switching losses of the MOSFETs and diodes are eliminated due to the converter's soft-switching operation in wide input voltage and output power variation ranges. Effects of the power MOSFETs and diodes conduction losses on the converter efficiency curves have been simulated, as given in Fig. 19(c). These simulation  results clearly show that to improve the converter efficiency, different components with low conduction losses can be used. In practice, a trade-off between the converter efficiency and its cost can be done to improve the converter efficiency and pay a reasonable cost by choosing low-loss inductors and transformer, low-ESR capacitors, and low voltage drop MOSFETs and diodes.
By considering Table 2, some conclusions are given as follows: a) Generally, transformers and inductors are massive components that strongly affect the converter's power densities and prices. However, Table 2 clearly shows that this is a common issue in many dc-dc converters. The soft-switching operation of the converters, which is also achieved here, is an efficient approach to overcome this problem and improve the power density and reduce the cost. b) Number of the active switches and their driver and control circuits are other issues. But, Table 2 clearly shows that the proposed converter is one of the best solutions from this point of view. c) Input filter and output capacitors are also reduced here due to the given symmetrical configuration. d) Although more diodes have been used here, as tabulated in Table 2, this is not a significant issue because lower current and voltage stresses are applied to these components, and this issue cannot very much affect the price and power density of the proposed converter in practice. Fig. 20 shows the dynamic response of the proposed converter when the load changes between 90% and 10%. To have a better clarification, an implemented 3-stage configuration of the proposed converter has been compared in more details in Table 3 with some other existing high step-up, high-voltage, interleaved, and LLC-based converters.
Finally, it must be mentioned that some unavoidable manufacturing mismatches may lead to improper operation of this proposed converter in practice, like many well-known power electronics converters, including interleaved-based topologies. For instance, any mismatches between the input inductors, the power switches of the different legs, their gate-drive circuits, their gate-source generated pulses, and so forth can affect the ideal operation of the proposed converter. This is a well-known issue in the power electronics field, and there are some solutions to overcome this problem. For instance, the average or peak current control approach can easily be used here to overcome this issue. However, the small signal modeling and closed-loop control approach of the proposed converter are ignored and not addressed here in detail to shorten the subject.

IX. CONCLUSION
In this paper, a new expandable high step-up LLC-based converter is proposed. The experimental results clearly show that all its primary stage MOSFETs and output stage diodes are operating under the soft-switching conditions in the entire wide input voltage and output power variation ranges. Therefore, high efficiency and low EMI noises are achievable, and high frequency operation is possible to reduce its passive components volume and thereby increase its power density. Also, integrating a two-phase interleaved current-fed structure with a LLC resonant converter makes it possible to achieve high voltage gain, as well as low input current ripple value. Besides, the input current frequency is twice the switching frequency that effectively reduces the input filter volume in practice. To regulate the output voltage, an asymmetric PWM technique at a fixed switching frequency is used to design the converter magnetic components, including input filter, resonant inductor, and multi-winding transformer, more effectively. A 1 kW prototype converter has also been implemented to verify the given analyses results. Wide input voltage 100-200 V, and output power 100-1000 W variations are applied to the converter. The APWM technique at 143 kHz switching frequency is used to regulate the output voltage at 1 kV. FREDE BLAABJERG (Fellow, IEEE) received the Ph.D. degree in electrical engineering from Aalborg University, in 1995. He is currently pursuing the Honoris Causa degree with University Politehnica Timisoara (UPT), Romania, and Tallinn Technical University, Estonia. He was with ABB-Scandia, Randers, Denmark, from 1987 to 1988. He became an Assistant Professor, an Associate Professor, and a Full Professor of power electronics and drives with Aalborg University, in 1992, 1996, and 1998, respectively. In 2017, he became a Villum Investigator. He has published more than 600 journal articles in the fields of power electronics and its applications. He has coauthored four monographs and an editor of ten books in power electronics and its applications. His current research interests include power electronics and its applications, such as in wind turbines, PV systems, reliability, harmonics, and adjustable speed drives. He has received 33