A Low-Phase-Noise CMOS Ring Voltage-Controlled Oscillator Intended for Time-Based Sensor Interfaces

We describe in this paper an improved ring voltage-controlled oscillator (VCO) showing a reduced phase noise while allowing an extended frequency tuning range. The phase noise improvement is obtained through the minimized contribution of tuning line noise while maintaining a rail-to-rail swing. The proposed VCO features a linear tuning characteristic yielding a constant gain over a wide range of operating frequencies. An analytical model is extracted resulting in closed-form expressions for the VCO phase noise. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The VCO prototype was fabricated in a 0.35 $\mu \text{m}$ CMOS process. It consumes 0.903 mW from a 3.3 V supply when running at its maximum oscillation frequency of 9.37 MHz. The measured VCO phase noise is −147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the circuit occupies a silicon area of 0.005 mm2. A state-variable MATLAB® model of a time-based sensor interface has been developed including the impact of phase noise nonideality. The system-level simulations demonstrate that the PLL-based sensor interface exploiting the proposed VCO characteristics can achieve a 88.43 dB signal-to-noise ratio over a 1-kHz bandwidth.

directed towards smaller technologies that are especially 23 effective for digital circuits while raising some difficulties 24 in designing analog systems [5], [6]. Supply voltage reduc-25 tion, weak intrinsic transistor properties (e.g., lower gain and 26 devices' mismatch), large power and chip area result in poor 27 The associate editor coordinating the review of this manuscript and approving it for publication was Jiann-Jong Chen . portability of purely analog solutions to other technology 28 nodes [7]. Therefore, time-based and digitally-oriented struc-29 tures became increasingly popular among electronic research 30 trends. 31 Moreover, VCO-based architectures are of great inter-32 est in time-based integrated circuits (ICs) such as time-33 domain comparators, analog-to-digital converters (ADCs), 34 time to digital converters, time-based sensor interfaces, etc. 35 This stems from the fact that VCOs offer highly digital, 36 energy-efficient, and scalable solutions [8]. Also, they realize 37 relatively simple configurations of multi-bit noise shaping 38 in A/D conversion or quantizer in delta-sigma modulator 39 [9], [10]. Fig. 1 conceptually illustrates the VCO's function in 40 two important types of time-based sensor interfaces or sensor 41 to digital converters. The inherent first-order noise-shaping 42 and the additional feedback network results in a low conver-79 sion speed, a larger area, and an increased power budget [24]. 80 The limiting factor in these close-loop time-based interfaces 81 is the VCO phase noise [20]. As a result, an on-chip VCO 82 design with improved linearity correction, less gain varia-83 tions, low phase noise, and full-swing is significantly required 84 in any analog/digital applications. 85 Generally, there are two types of ring VCOs: single-ended 86 and differential. Single-ended VCOs are widely used in dig-87 ital nature applications due to their low complexity, smaller 88 area, lower temperature coefficient, and wider tuning range. 89 Also, a differential ring VCO may show larger phase noise 90 compared to a single-ended VCO at the same power, oper-91 ation frequency, and the number of delay stages. While, its 92 phase noise performance could even be worse without tail 93 current noise minimization technique [25]. In contrast, differ-94 ential ring VCOs offer better common-mode noise rejection 95 with a lower sensitivity to substrate and supply noises. In a 96 single-ended ring VCO, these sensitivities can be reduced 97 to some extent through proper layout design consideration. 98 In addition, in the closed-loop time-based sensor interface 99 shown in Fig. 1(b), the common-mode sensitivity of the 100 single-ended VCO can be suppressed by having two identical 101 oscillators laid out close together. It is due to the fact that 102 when two oscillators operate in the same physical environ-103 ment, the related noise appears as a common mode perturba-104 tion on their oscillation frequencies [24]. Therefore, the above 105 factors should be considered when selecting the appropriate 106 design of ring VCO for a particular application. 107 In an attempt to obtain a VCO with low phase noise, 108 authors in [26] promote rail-to-rail voltage swings. How-109 ever, their employed delay cells limit the noise performance 110 by injecting a substantial noise during the VCO's transi-111 tion periods. Another study presented in [15] focused on 112 reducing injected channel thermal noise in transistors during 113 VCO's output transitions. Nevertheless, the VCO perfor-114 mance remains limited due to the low-frequency tuning range 115 and the large power consumption. A band switch function 116 is employed in [2] to suppress the control line noise and 117 compensate for tuning range. However, the additional mecha-118 nism for band switch control increases the overall phase noise 119 while suffering from power overhead. An ultra-low-power 120 ring VCO was reported in [27]. It uses a differential delay 121 cell to generate negative conductance without requiring the 122 cross-coupled latch. This design suffers from an unattractive 123 phase noise performance, a low frequency tuning range, and 124 a large occupied area due to the passive components used in 125 the delay cell implementation.

126
This work presents a compact, wide-swing, enhanced 127 phase-noise, and low-power CMOS ring VCO. The delay 128 elements used in the proposed VCO show a full-swing output, 129 a linearized characteristic, and a steady gain. A theoretical 130 analysis considering the impact of intrinsic and extrinsic 131 sources of noise has been developed to study the VCO 132 phase noise. Also, the effectiveness of this architecture is 133 validated through a Matlab/Simulink model of a closed-loop 134 VOLUME 10, 2022    The output oscillation frequency of a VCO is determined 188 by its control voltage through the VCO gain (or sensitivity), 189 K VCO . Suppose an injected voltage noise at the tuning node 190 of the oscillator. For a given noise amplitude, the noise in 191 the output frequency is amplified by K VCO . Clearly, it will 192 affect the noise spectral density and thereby the phase noise 193 behavioral model. Accordingly, the flicker noise impact on 194 phase noise can be determined by considering the direct mod-195 ulation of oscillation frequency caused by the circuit transfer 196 function. As any noise generated in the control scheme can 197 provoke additional phase noise, it is necessary to examine the 198 disturbance of the output phase and frequency arising from 199 the circuit's integrated noise and the extrinsic noise accom-200 panied by the control voltage. We leverage these principles to 201 find the phase noise expression for the proposed VCO, which 202 is described in detail in section III-C. It consists of five delay cell stages in addition to a buffer at 206 the output of the VCO to sharpen the generated signal and 207 drive the VCO load. The implementation of the proposed 208 linearized delay cell is illustrated in Fig. 2(b). In each current-209 starved delay cell, the control voltage (V cont ) is applied to the 210 voltage-controlled current source M P1 and the resulting cur-211 rent, I cont , is mirrored to the inverter (constructed from M P4 212 and M N4 ) through the current mirror M N1 , M N2 , and M P2 . 213 The replica current source M P1 in each stage dynamically 214 biases the current-starved inverter and avoids current varia-215 tion at I cont which may lead to some linearity error. Also, the 216   to be sufficient to cover this range of frequency. Also, fewer 223 number of delay cells mitigates phase errors that might be 224 added due to the mismatch of delay cells [23]. Transistors' 225 aspect ratios shown in Table 1 are considered for the con-

III. PROPOSED VCO ARCHITECTURE
The propagation delay is measured when the output signal

240
where C tot is the total parasitic capacitance seen at the output 241 of each delay element [32].

242
Supposing I N j I P j I out , the nominal frequency of 243 oscillation is given by 245 Therefore, the output frequency of a ring VCO is directly 246 related to the current supplied to the inverter branches.  In the proposed delay cell implementation, shown in 258 Fig. 2(b), this nonlinearized circuitry is rectified by means 259 of entering V cont to a voltage-controlled current source, 260 M P1 , and using a current mirror biased in strong inversion. 261 As depicted in Fig. 3(a), owing to the saturation-operating of 262 M P1 , the resulting control current, I cont , shows a nonlinear 263 behaviour with V cont . To compensate for this nonlinearity, 264 the current mirror transistors are designed to transfer a linear 265 biasing voltage (V CP or V CN ) as functions of V cont to the load 266 transistors M P3 or M N3 in the pull-up or pull-down operation, 267 respectively.

268
Considering the pull-up network activation moment, the 269 load transistor M P3 is biased in the triode region, and its 270 drain-source current equals I out . So, the output current of the 271 proposed VCO is linearly related to its V GS p3 and, hence, 272 to its bias voltage V CP (see Fig. 3(b)). This feature, along 273 with the linear behavior of V CP versus the controlling voltage 274 V cont (see Fig. 3(c)) ensures that the proposed VCO maintains 275 a linear relationship between I out and V cont and controls the 276 frequency response nonlinearity. Fig. 4 shows the operation 277 frequency of the proposed VCO with and without the lin-278 earization versus its control voltage. As can be seen, a good 279 enhancement in the VCO linearity compared to the design 280 without the proposed linearization is obtained. The VCO's gain is defined as Since the propagation delay time is estimated by the aver-285 age output tail current going through the output capacitance, 286 VOLUME 10, 2022 the gain can be expressed as where V sw is the voltage swing of V out . It is noteworthy that 289 V sw may be reduced at a quite small I out due to slowed swing The uncertainty in propagation delay of the proposed VCO 334 can be modeled in the output current I out across the C tot . 335 This current is accompanied by a noise current source with 336 a white noise spectral density of S W i n = i 2 n = 4k B T γ g m , 337 where coefficient γ is typically equal to 2/3 for long-channel 338 transistors. i 2 n would result in a Gaussian distribution of the 339 propagation delay (t p ), which can be referred to as timing 340 jitter. The total variance of the period jitter in view of the 341 uncertainty in rising edge (t p rise ) and falling edge propagation 342 delay (t p fall ) can be calculated as where the variance of the jitter due to the uncorrelated white 345 noise is σ 2

346
Using equations (7) and (2), the total period jitter approxi-347 mated as The general relationship between phase noise and jitter, 350 where the phase noise is dominated by white noise, is [14], 351 [20], Therefore, the SSB phase noise of VCO due to white noise 354 can be estimated as   The delay is directly modulated by the flicker noise asso-373 ciated with pullup and pulldown current supplies. Therefore, 374 according to (3) and (11), the equivalent SSB phase noise due 375 to flicker noise contribution can be written as [30]

394
The MOSFET flicker noise PSD in the active region is Consequently, equation (14) combined with (10) approx-405 imate the total phase noise characteristics of the proposed 406 VCO. Usually phase noise is expressed in decibels (dB) as 407 10 · log(L{ f }), and its units are dB below the carrier in a 408 1 Hz bandwidth, generally abbreviated as dBc/Hz [31].

409
As specified in the analytical model equations (10) 410 and (14), the white and flicker phase noise are inversely 411 proportional to the drain current of MOSFETs in the inverter 412 stack. This is because the delay is directly affected by the 413 noise associated with the transistors connected to the output 414 nodes [15]. Therefore, as the current noise associated with the 415 current mirror transistors is reflected to the inverter with a κ m 416 of less than one, the noise originating from those MOSs is not 417 included in the model to simplify the analysis.

418
At the low offset frequency, the flicker noise of transis-419 tors used to implement the delay element is the dominant 420 close-in phase noise source. Generally, transistors operating 421 in a periodically stable region have more contribution to the 422 circuit phase noise than transistors functioning in a switch-423 ing mode. Thus, transistors composing the current source 424 (M P1 ), and inverter (M P4 -M N4 ) which run in a period stable 425 state, generate more 1/f noise. This impact was reduced by 426 adopting PMOS transistors for input controlling source since 427 holes are less likely to be trapped and leads to inherent lower 428 flicker noise than NMOS transistors. Also, the transistors' 429 sizes are selected large enough with respect to the I out and f osc 430 VOLUME 10, 2022

450
The proposed ring-VCO is designed and fabricated using a  The simulated and measured oscillation frequency and 465 its corresponding core power consumption of the integrated 466 VCO as a function of its tuning voltage are depicted in 467 Fig. 7(a). The proposed VCO visually exhibits improved 468 linear performance. The simulated and measured nonlinearity 469 error over the tuning range is presented in Fig. 7(b), yielding 470 a maximum error of 0.8% and 0.9%, respectively. As can 471 be seen in the figure, nonlinearity might be increased for 472 V cont ≥ 2 V.

473
The VCO was designed to generate an output frequency 474 between 0.01 MHz and 10 MHz for a control voltage varying 475 from 0 to 2 V. However, the measured output is from 0.01 up 476 to 9.37 MHz resulting in a tuning range, TR f , of 199.5%. This 477 slight reduction in the maximum measured frequency is due 478 to process variations and the parasitic capacitances from PCB 479 traces and the coaxial cable in the signal path.  1.039 mrad). Since SSB phase noise 486 follows a slope of -30 dB/dec up to 100 kHz offset frequency, 487 we can conclude that flicker noise is the main contributor 488 to the proposed VCO's phase noise, as was expected based 489 on its operating frequency range. In addition, the measured 490 spectrum of the presented VCO circuit, when tuned to gener-491 ate a maximum frequency of 9.37 MHz (with V cont = 0 V), 492 is shown in Fig. 9(a). Fig. 9(b) illustrates the output signal 493 power of the proposed VCO corresponding to the operating 494 frequencies over a control voltage varying from 0 to 2 V. 495 The results include the loss associated with the cable and 496 interfaces.   in the inset. The carrier frequency in the analytical equa-504 tions is optimized with respect to the measured value of 505 the maximum oscillation frequency of 9.37 MHz. Since the 506 control voltage is provided from a DC generator during 507 measurement, the measured PSD of υ n ext = 5 nV/

√
Hz is 508 used for the extrinsic noise accompanying the bias voltage. 509 As the tuning voltage increases, the output current and the 510 oscillation frequency decrease. As shown in analytical equa-511 tions (10) and (14), oscillation frequency and output current 512 have opposing effects on the phase noise. Thus, control volt-513 age increments have only resulted in a few dB improvements. 514 Comparison of the analytical model prediction with the 515 measured phase noise shows that the average phase noise 516 difference is less than 8% as the frequency offset changes 517 from 1 kHz to 1 MHz. This slight difference stems from some 518 correlated noise sources on different nodes of the oscillator. 519 For instance, substrate and supply noise arising from current 520 switching in other parts of the chip are considered negligible 521 in the analytical model. Also, the induced phase noise of 522 the output buffer, which is not considered in the analytical 523 model, influences the total phase noise result. Because of 524 this, the measured phase noise for the offset of more than 525 10 kHz does not follow the same slope as the estimated 526 From the FoM 1 perspective, the performance of all VCOs 561 in terms of power consumption and phase noise with respect 562 to two different carrier frequencies are examined. The FoM 1 563 of the proposed VCO is -174.75 and -167.5 dBc/Hz at 10 kHz 564 and 1 MHz frequency offset, respectively. As shown in 565 Table 2, the presented work shows a better FoM 1 amidst the 566 designs with roughly the same operating frequency. Struc-567 tures reported in [16], [33], and [34] have good FoM 1 or 568 FoM 2 , but exhibit high phase noise, large area, and limited 569 tuning frequency range.

570
The proposed VCO achieves low power and a small inte-571 gration area compared with similar designs listed in Table 2. 572 The average power consumption is 0.32 mW, and the power 573 dissipation at a maximum oscillation frequency of 9.37 MHz 574 is 0.903 mW including the power of the output buffer. Despite 575 the high supply voltage and the long-channel technology 576 whose power consumption is inferior, the proposed VCO 577 shows a wide frequency range with a tuning voltage up to 2 V 578 and a FoM 2 of -193.45 dBc/Hz. In addition, it shows a linear 579 voltage tuning range over 60% of VDD while significantly 580 outperforming conventional techniques in terms of phase 581 noise property.

582
Additionally, the VCO contributed noise can be character-583 ized by the input-referred phase noise spectrum as a func-584 tion of the offset frequency. Phase noise can be accurately 585 represented as input-referred noise by applying the inverse 586 of the system transfer function [13], [14]. Since phase is the 587 integral of the frequency, the VCO acts as an ideal integrator 588 for the control voltage when the output variable is a phase. So, 589 its transfer function can be simply expressed as H VCO (s) = 590 K VCO s . The one-sided PSD of input-referred phase noise as a 591 function of the certain f , can be defined as [13] and [31] where S φ ( f ) is the one-sided PSD of phase noise. So, the 594 input-referred noise of the proposed VCO with a phase noise 595 of -147.57 dBc/Hz at 1 MHz offset and a gain of 4.7 MHz/V 596 is calculated to be 12.58 nV/

597
As explained, the proposed VCO is designed for a sen-598 sor interface application where a low-frequency range was 599 adopted. However, by adjusting transistors' feature size in 600 the proposed design, a higher oscillation frequency could 601 be achieved. Generally, the maximum oscillator frequency 602 as a function of the CMOS technology development has an 603 ascending behavior while the phase noise performance is 604 descending. Therefore, the proposed design at higher fre-605 quencies and scaled technology nodes may experience some 606 degradation in its phase noise performance. parameters are adopted in this implementation and the overall 612 performance is examined. Fig. 12 shows the correspond-613 ing simulation model of the closed-loop PLL-based sensor 614 interface presented in Fig. 1(b) [14], [20]. The conversion is the 1/f 2 phase noise using (9) [14] and [20]. Although the 650 result of this approximation is not quite realistic, it is a tolera-651 ble approach to evaluate the influence of the VCO phase noise 652 on the system's SNR. Fig. 15 shows the SNR as a function   strategy at the cost of input bandwidth [14]. Fig. 16 shows 658 the cross-section view of Fig. 15 at OSR = 5000. It can be 659 seen when the phase noise is insignificant (for the phase noise 660 less than -160 dBc/Hz), the gain has no effect on the SNR 661 performance while the SNR increases by 6.02 dB for each 662 quantizer bit as expected from the ideal definition. On the 663 contrary, in the phase noise dominant region (right-side), 664 doubling the VCO gain improves SNR by around 4 to 8 dB 665 depending on the phase noise value. 666 We can conclude that in a VCO-based sensor interface, 667 the oscillator phase noise performance has a major impact 668 VOLUME 10, 2022