A Framework for Sensitivity Analysis of Real-Time Power Hardware-in-the-Loop (PHIL) Systems

Power hardware-in-the-loop (PHIL) simulation leverages the advanced real-time emulation based technique to carry out in-depth investigations on novel real-world power components. Power amplifiers, sensors, and signal conversion units based power interfaces (PI) incorporate physical hardware systems and real-time simulation platforms into PHIL setups. However, the employment of any interfacing technique inevitably introduces disturbances such as sensor noise, switching harmonics, or quantization noise to PHIL systems. To facilitate quantitatively analyzing and assessing the impact of external disturbances on PHIL simulation systems, a framework for sensitivity analysis of PHIL setups has been developed in this paper. Detailed modelling principles related to the sensitivity analysis of PHIL systems and the inherent relationship between sensitivity transfer functions and stability criteria are elaborated along with theoretical and experimental validation. Based on this concept, accuracy assessment methods are employed in this framework to quantify generic sensitivity criteria. Moreover, physical passive load and converter-based PHIL setups are applied and experimental results are presented to characterize and demonstrate the applicability of the proposed framework.


FIGURE 1.
Principle topology of (a) the system of interest (SOI) and (b) the corresponding PHIL simulation system. framework and allows for a precise estimation of PHIL 89 system properties prior to experimental testing. 90 3) Along with the sensitivity analysis criteria, practical 91 methods involving the signal-to-noise (SNR) and the 92 total harmonic distortion plus noise (THD+N) are 93 presented to quantity the sensitivity, which are easily 94 applied to practical experiments. 95 4) Based on the voltage-type and current-type ITM inter-96 faces, the framework for sensitivity analysis was 97 characterized and verified by experimental PHIL 98 setups at two laboratories, the Dynamic Power Systems 99 Laboratory at the University of Strathclyde and the 100 Electric Energy Systems Laboratory at the NTUA of 101 Athens, demonstrating its applicability for simplified 102 to complex power system and component testing. 103 This article is structured in subsequent manner: follow-104 ing this Introduction, the detailed modelling of the PHIL 105 system is presented in Section II. Section III provides 106 the in-depth details of the sensitivity analysis framework. 107 Analytical assessments of the proposed sensitivity framework 108 are presented in IV, followed by its experimental validation 109 presented in Section V. Section VI concludes this article. 112 This section presents the topology of the PHIL system along 113 with its detailed modelling, characteristics and properties. 114 A. PHIL TOPOLOGY 115 PHIL simulation combines the physical power component 116 with real-time emulated system into a closed-loop testing 117 configuration that mimics the original system of interest 118 (SOI). Fig. 1 illustrates the SOI and its corresponding PHIL 119 simulation setup. The original SOI is expressed by a lumped 120 voltage divider topology comprising two series-connected 121 Thévenin equivalent circuits S 1 and S 2 , respectively. System 122 S 1 comprises a voltage source U S in series with an equiv-123 alent impedance Z 1 and system S 2 comprises an equivalent 124 impedance Z 2 . S 1 represents the real-time emulated power 125 network in DRTS referred to as software side and S 2 repre-126 sents the real-world HUT referred to as hardware side, both 127 of which are coupled through a PI in the PHIL setup. 128 The PI comprises one or several PA, sensors, analogue-129 to-digital (ADC) and digital-to-analogue (DAC) conversion 130 cards, and signal processing units such as low-pass filter-131 ing blocks for noise mitigation. The configuration of these 132 S 1 and S 2 , can be expressed by their continuous-time system  (SISO) closed-loop PHIL system and the respective equiv-169 alent block diagram is presented in Fig. 2

PHIL SIMULATION SYSTEMS
where T FW (s), T FB (s) represent the signal processing unit 173 in the feed-forward and feed-back path respectively, T VA (s) 174 represents the dynamic behavior of the PA in voltage mode, 175 T CM (s) represents the current measurement unit, and τ s is the 176 time step size of the DRTS. In contrast to the V-ITM, as shown in Fig. 3, the I-ITM 179 is configured as a current source on the hardware side 180 and a voltage source on the software side, which are con-181 trolled by a current-type PA and a voltage sensor signal, 182 respectively.

183
In analogy to the equivalent SISO closed-loop block dia-184 gram as, shown in Fig. 3 (bottom), the open-loop transfer 185 function F i O (s) of the I-ITM PHIL setup is given by

212
where ω cg is the gain crossover frequency at which the mag-

222
Assuming the ITM interface presents unity-gain and infi- 234 Alternatively, as presented in [5] and [24], the accuracy met- The sensitivity function S 1 (s) of signals of interest U (s) or 261 I (s) related to associated local disturbances δU (s) or δI (s), 262 respectively, is defined as , , .
where subscripts A and D represent analogue and digital sig-265 nals, respectively. Sensitivity functions for other disturbances 266 with respect to the signal of interest can be derived in a 267 similar manner. The following two sub-sections present the 268 sensitivity functions for the two types of the ITM interface.

295
For a disturbance with frequency ω, the magnitude of the 296 sensitivity function S 1 (jω) defined in (8) is given by . curve is to the Nyquist point. In this case, the PHIL system is 306 less robust.

307
The maximum magnitude of the sensitivity function given 308 by |S 1 (jω)| max indicates the robustness of overall PHIL sta-309 bility and is given by Substituting (13) into (14), the inequalities between the sen-319 sitivity function and stability margins are given by given by   Table 2 yields to: To ensure linearity and thus make the system amenable for  are both equal to zero. From the Nyquist diagram, one can 378 also assess that the system has infinite phase margin, since 379 any rotation of the curve does not change the number of 380 encirclements around (−1, 0). This is confirmed in Fig. 8, 381 where it is shown that the gain of F v O (s) is smaller than 382 1 for all frequencies. The GM is also straightforward to 383 compute and it is equal to 54.6 dB, obtained at a frequency 384 of approximately 2.75 kHz.    In the present case, disturbances with frequencies up to 405 10 kHz are attenuated by 34.8 dB representing a gain of 406 approximately 0.0184, with an even more consistent reduc-407 tion at higher frequencies. The phase shift is negligible 408 up to 350 Hz and then gradually decreases, until reaching 409 −180 degrees at about 10 MHz. The stability and sensitivity analysis has also been performed 412 for the I-ITM interface, considering the block diagram in 413 Fig. 5. The parametrization of this PHIL setup is tabulated 414 in Table 3 in Appendix A. The analysis discusses a numerical 415 case representing a realistic scenario and which is consistent 416 with experimental results from Section V-B.

417
In this case, the sensitivity analysis has focused on the 418 impact of the output voltage disturbance δU A of the power 419 converter, stemming from the measurement noise and switch-420 ing of the power converter as HUT, on the analogue and 421 digital interface signals in the PHIL setup. For a given distur-422 bance with frequency ω, the frequency-dependant magnitude 423 and phase response of the analogue and digital signals can 424 be derived from the sensitivity metrics in (10) for further 425 analysis. For the disturbance δU A , the magnitude and phase 426  Fig. 9.

428
For the analytical assessment of the sensitivity and stability 429 criteria defined in Section III-C, a case study involving differ-430 ent software side impedance as given in Table 1 is discussed.  non-relative factors that might impact the sensitivity analysis 462 to a minimum. Compared with the setup for the analytical 463 evaluation from Table 2   This case study involves incorporating a voltage source back-509 to-back converter into a PHIL simulation setup by applying 510 the I-ITM interface. Fig. 15 illustrates the setup for this 511 PHIL experimental test. The digital current signal I D mea-512 sured from the real-time network model is transmitted to 513 the Triphase 15 kVA (TP15 kVA) current-type PA as a com-514 mand signal to command the resulting output current I A . 515 The output terminal of the TP15 kVA is coupled with that 516 of the Triphase 90 kVA (TP90 kVA) power converter with 517 the former sourcing current to the latter. The output voltage 518 U A of the TP90 kVA is measured and transmitted to the 519 DRTS as the command voltage signal U D for the controllable 520 voltage source. For the modelling process, the parametriza-521 tion of each component in this PHIL setup is shown 522 in Table 3.

523
An equivalent voltage source with a nominal line-to-line 524 (LL) AC voltage U S,LL of 400 V, and the fundamental fre-525 quency f 0 of 50 Hz emulates a low-voltage grid. A low X /R 526 ratio grid impedance, as listed in Table 3, emulates a strong 527 grid. The output voltage of the TP90 kVA power converter 528 VOLUME 10, 2022  analogue signal U A is distorted by the harmonics and 538 high-frequency noise introduced by the pulsating modulation 539 of the converter. Due to the implementation of a low-pass 540 filter with a cut-off frequency of 1500 Hz, the digital voltage 541 U D presents a higher SNR and lower THD+N than that of the 542 analogue voltage U A and is less noisy. The SNR and THD+N 543 of the digital current I D are approximately equal to that of the 544 digital voltage U D . However, the amplitude of most frequency 545 components of I A are greater than that of the reference sig-546 nal I D and correspondingly the current I A presents a lower 547 FIGURE 20. Interface signals of the I-ITM PHIL setup with varying grid impedance Z 12 (s) and Z 13 (s) as given in Table 1. SNR and higher THD+N than that of the current I D . The   injected voltage signal U A with a fix harmonic can be directly 579 revealed from their phase response. Fig. 18(a) presents the 580 phase response of I D and U A over the fundamental frequency. 581 Based on these phase responses, the phase difference between 582 these two interface signals is calculated and illustrated in 583 Fig. 18(b) and Fig. 18(c). This phase difference slightly devi-584 ates from the constant value 176.72 deg (blue dashed line) that 585 corresponds to the phase response of the sensitivity metric 586 (S i 3 (s)) at the fundamental frequency in Fig. 9. Furthermore, 587 the phase response of I D and U A over the seventh harmonics 588 is presented in Fig. 19(a) along with their phase difference as 589 presented in Fig. 19(b) and Fig. 19(c). Once again, this phase 590 difference deviates from the phase response (155.25 deg) 591 of the sensitivity metric (S i 3 (s)) at 350 Hz in Fig. 9. The 592 discrepancy between the experimental phase shift and the 593 phase shift of the analytical sensitivity metric may arise from 594 the the additional time delay stemming from the current or 595 voltage measurement units, and the variable time delay in the 596 power amplifier.

598
Based on the I-ITM PHIL setup, grid side impedance vari-599 ations are emulated to verify the stability and sensitivity 600 criteria. Impedances Z 12 (s) to Z 13 (s) are modified at t = 601 0.2 s, as given in Table 1, and the interface signals are shown 602 in Fig. 20. After the impedance change, the interface sig-603 nals present significant oscillations and the PHIL system 604 is unstable. This is consistent with the analytical stability 605 analysis in Section IV-B. As given in Table 1, the stability 606 margin decreases as a result of the grid side impedance 607 decrement. When the grid side impedance witness a vari-608 ation from Z 12 (s) to Z 13 (s), the inequalities between gain 609 margin, phase margin and vector margin defined in (14) 610 and (15) are no longer guaranteed and the system becomes 611 instable.

613
This work presents a comprehensive framework for the pur-614 pose of sensitivity analysis for PHIL simulation systems. 615 One major contribution is represented by the introduction 616 of an analytical modelling of PHIL systems with partic-617 ular reference to potential disturbances causing sensitivity 618 issues regarding interfacing methodologies. Based on model-619 ing principles, sensitivity transfer functions for PHIL setups 620 with voltage-type and current-type interfaces are introduced. 621 The introduced sensitivity functions are of major importance 622 when evaluating robustness or enhanced stability proper-623 ties of PHIL setups with power interfacing techniques. 624 Based on the generic concept using continuous time-625 modeling, sensitivity analysis can be performed for PHIL 626 systems.

627
A second major contribution is given by the analytical 628 and experimental assessment of the proposed sensitivity 629 VOLUME 10, 2022    System parametrization used for analysis of the I-ITM inter-656 face in Section IV-B, and in the corresponding experimental 657 setup in Section V-B, is reported in Table 3. For this setup, 658 the time step size and the fundamental frequency are set as 659 50 µs and 50 Hz, respectively and the line-to-line software 660 side voltage is 400 V. The forward signal processing and the 661 feedback voltage measurement are assumed to be ideal, thus 662 respective transfer functions T FW (s) and T VM (s) are equal 663 to 1. The current-type PA shows a low-pass behaviour with a 664 cut-off frequency of 768 Hz, as highlighted in the table. The 665 cut-off frequency of T FB (s) is 1500 Hz. Complex software 666 and hardware system impedances including grid impedance 667 properties as well as the converter output impedance are 668 shown in Table 3.  In 2019, she was also an Intern with BayWa 855 r.e, Berlin. Since 2019, she has been working as 856 a Researcher with the Department of Electrical 857 and Computer Engineering, National Technical University of Athens. Her 858 research interests include control of power inverters, converter-driven stabil-859 ity, microgrids, cyber-security aspects of smart grids, and laboratory valida-860 tion methods. She has contributed to several European and national research 861 projects in the field of power systems. She is a member of the Technical 862 Chamber of Greece. 863 VOLUME 10, 2022