A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs

For the design of inverter-based OTAs with differential input and single-ended output, the differential to single-ended (D2S) converter is a key building block. In fact, the performance of the D2S strongly affects the overall common-mode rejection ratio (CMRR) and input common-mode range (ICMR) of the whole OTA. In recent literature, inverter-based OTAs rely on a D2S topology based on an inverter driving another inverter with the input and output tight together which behaves as a “diode” connected device to implement a voltage gain approximately equal to −1. However, since this approach is based on the matching of the inverters, the performance of this D2S results sensitive to PVT variations if the bias point of the inverters is not properly stabilized. In this paper we present a novel topology of inverter-based D2S converter, exploiting an auxiliary, standard-cell-based, error amplifier and a local feedback loop. The proposed D2S, compared to the conventional one, exhibits higher CMRR, improved ICMR and better robustness with respect to PVT variations. We present also an ULV, standard-cell-based OTA, which exploits the proposed D2S converter and shows excellent performance figures of merit with low area footprint.

many IoT circuits require energy harvested architectures [1], 23 [2], the design of Ultra-Low-Voltage (ULV) analog building 24 blocks suitable to operate with supply voltages as low as 0.3V, 25 is becoming more and more attractive. 26 The Operational Transconductance Amplifier (OTA) is 27 surely one of the most useful analog building blocks in elec-28 tronic apparatuses, and stands out for its application in several 29 analog circuits such as filters, comparators, analog to digital 30 The associate editor coordinating the review of this manuscript and approving it for publication was Tae Wook Kim . converters (ADCs), digital to analog converters (DACs), low 31 dropout regulators (LDOs), and so on. 32 In this ultra-constrained scenario several high performance 33 OTAs which exploit body-driven gate-biased architectures 34 have been presented in the recent literature [3], [4], [5]. 35 In detail, the usage of the body-driven approach has resulted 36 in a plenty of topologies which exhibit state-of-the-art perfor-37 mances, both in terms of small signal and large signal figures 38 of merit, and good robustness with respect to process, supply 39 voltage and temperature (PVT) variations [3], [6], [7]. How-40 ever, such OTAs have to be designed and routed manually 41 and very often result in huge area occupation, due to the fact 42 that separate wells are mandatory to implement body-driven 43 architectures. 44 On the other hand, several inverter-based OTAs have been 45 proposed in the literature. The Nauta transconductor has been 46 presented for the first time in 1992 [8] and it has been recently 47 exploited in [9] and [10] to implement fully differential OTAs 48 for high speed applications. However, it has to be noted that 49 most of the inverter-based implementations available in the 50 input and output tight together which behaves as a ''diode'' 107 connected device to implement a voltage gain approximately 108 equal to −1. However, since this approach is based on the 109 matching of the inverters, the performance of this D2S results 110 sensitive to PVT variations if the bias point of the inverters 111 is not properly stabilized. To overcome this issue, in [29] a 112 body-bias strategy to set the static output voltage and the bias 113 current of inverters has been proposed; however this approach 114 requires ad-hoc circuits whose supply voltage is larger than 115 the one of the ULV OTA. Recently a similar replica-bias 116 approach to set the output static voltage of the basic amplifier 117 cells has been presented in [31]. 118 In this work we propose a novel topology of inverter-119 based D2S converter which exploits a local feedback to 120 achieve higher CMRR and better robustness with respect 121 to the previously published inverter-based D2S. An ULV 122 standard-cell-based OTA which exploits the proposed D2S is 123 also presented, showing outstanding performance in terms of 124 performance figures of merit with limited area footprint. 125 In the following, section II reviews the previously pub-126 lished inverter-based D2S converter and presents for the 127 first time a detailed analysis of its performances. The novel, 128 improved, inverter-based, D2S converter is introduced and 129 analyzed in section III. The design of an ULV, standard-130 cell-based OTA exploiting the novel D2S converter is pre-131 sented in section IV, and simulation results are discussed in 132 section V. Finally, a comparison against the state of the art of 133 ULV OTAs, and some conclusions are reported in sections VI 134 and VII respectively.

137
In the context of analog design, the differential to 138 single-ended conversion is usually carried out in the first 139 stage of the OTA by means of the well known differential pair 140 with current mirror active load. The same kind of differential 141 to single-ended conversion is needed also in inverter-based 142 or standard-cell-based OTAs exhibiting a differential input 143 and a single-ended output. In recent research works dealing 144 with inverter-based analog circuits such as [6], [7], [11], 145 [29], [30], the differential to single-ended conversion is often 146 performed exploiting the circuit topology depicted in Fig. 1. 147 In the following we will refer to the circuit in Fig. 1 as the 148 ''conventional inverter-based D2S'' stage.  inverters I 1 and I 1 with a current mirror active load which is 152 implemented by the inverters I 2 and I 2 . In particular, since I 2 has the input and output tight together, it behaves as a 154 ''diode'' connected device to mimic the input transistor of a 155 current mirror.

156
In order to gain insight into the behaviour of this D2S, 157 we express its performance by modelling the generic inverter 158 I i as a transconductance amplifier whose parameters are (1) 164 and the same notation is used for the output conductance g ds i 165 and the parasitic capacitances C gd i and C gs i of MOS transis-166 tors as follows: where the dc gain A v D2S 0 is: and the time constants τ o and τ 1 are: As can be observed in eq. (5) the ''diode'' connection of Eq. (8) clearly shows that the current gain of the conventional 199 inverter-based current mirror tends to unity if the two follow-200 ing conditions are fulfilled: 203 It is therefore evident that the conventional current mirror 204 exhibits a limited accuracy due to the relatively small value 205 of the intrinsic voltage gain of inverters in nanometer tech-206 nologies. An additional effect that further limits the accuracy 207 of the conventional inverter-based current mirror is related 208 to the different static voltages across the two inverters I 2 209 and I 2 that strongly affect the ability to achieve the second 210 condition: g m 2 = g m 2 . In fact, referring to Fig. 3, the output 211 of the inverter I 2 in short circuit condition (i.e. Z L = 0) 212 is connected to the analog ground equal to V DD /2, whereas 213 the static voltage at the input node of the current mirror is 214 dependent on inverters' sizes and is sensitive to mismatches. 215 This effect is similar to the one present in a traditional analog 216 current mirror when the drain source voltages of the input and 217 output transistors of the mirror are not well matched to each 218 other.

220
The common-mode rejection ratio CMRR of the conventional 221 inverter-based D2S can be easily computed as follows: From eq. (9) it is evident that the D2S in Fig. 1   According to the block scheme in Fig. 4, and noting that the 244 unity gain configuration for the D2S results in a ''diode'' con-245 nection for the inverter I 1 , the output current offset (whose 246 standard deviation is denoted as σ I ) at the node where V o 247 is connected to V m can be multiplied by the factor 1/g m 1 to 248 compute the output voltage offset (whose standard deviation 249 is denoted as σ V ), obtaining:

252
In this section we introduce a novel, inverter-based, D2S Referring to Fig. 6, the input-output transfer characteristic 280 of the improved current mirror can be written as: where: In this case eq. (12) shows that the current gain of the pro-285 posed improved inverter-based current mirror tends to unity 286 if the two following conditions are fulfilled: It is therefore evident that the proposed current mirror 290 exhibits an improved accuracy with respect to the conven-291 tional one, due to the gain provided by the auxiliary differ-292 ential amplifier. An additional important advantage of the 293 proposed improved current mirror which further improves 294 its accuracy with respect to the conventional inverter-based 295 current mirror is related to the static voltages across the two 296 inverters I 2 and I 2 that have a strong impact on the possibility 297 to achieve the condition g m 2 = g m 2 . In fact, referring to differential gain can be written as: 334 where the dc gain A v D2S 0 is: 342 and 343 A D = g m 3 g ds 3 + g ds 4 (18) 344 As it can be observed form eq. (16), the feedback allows to 345 shift the pole-zero doublet to frequencies greater than the one 346 of conventional D2S (summarized in eq. (5)). Furthermore, 347 as done for eq. (5) we can neglect the effect of the pole-zero 348 doublet given by τ A and simplify the frequency response as 349 follows: Thus, as a first order approximation the proposed D2S 352 exhibits the same frequency response of the conventional 353 one.

355
The CMRR of the improved D2S can be easily derived as: Therefore, by comparing eq. (9) with eq. (20), it is evident 358 that the proposed D2S converter exhibits a CMRR which is 359 higher than the one of the conventional D2S of the factor 360 A D ≈ The block scheme for computing the offset standard devi-363 ation σ v of the proposed improved inverter-based D2S in 364 unity gain configuration is reported in Fig. 7. According to 365 the block scheme in Fig.7, and noting that the unity gain 366 configuration for the D2S results in a ''diode'' connection 367 for the inverter I 1 , the output current offset (whose standard 368 deviation is denoted as σ I ) at the node where V o is connected 369 to V m can be multiplied by the factor 1 g m1 to compute the 370 output voltage offset (whose standard deviation is denoted as 371 σ V ), obtaining: By comparing eq. (10) and eq. (21) it can be seen how 374 the proposed implementation significantly decrease the off-375 set given by I 2 . However the offset of the differential auxil-376 iary amplifier is added to the overall offset, thus resulting in 377 greater standard deviation with respect to conventional D2S 378 converter. Eq. (21) shows that there is a trade-off in designing 379 VOLUME 10, 2022 R. D. Sala et al.: Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs   The differential gain of the proposed ULV, standard-cell-394 based OTA can be derived as: 399 and 400 C Z = C gd 5 · g m 5 g ds 5 + C gs 5 + C gd 1 + C gd 2 (25) 401 is the total capacitance at node Z in Fig. 8. Since our goal is to design an OTA which is able to drive 413 both on-chip and off-chip capacitive loads, we set the value 414 of the minimum load capacitance C L min to a value which 415 is integrable on-chip and we then size the inverter I 5 so as 416 to attain the required phase margin for such minimum load 417 capacitance.

419
Since the topology of the proposed OTA is derived by simply 420 adding the inverter I 5 to the proposed D2S, the CMRR of 421 the OTA is the same obtained by the D2S converter and is 422 expressed by eq. (20).

424
The positive and negative slew rate (SR + and SR − ) are set by 425 the output capacitance C L and the maximum output current 426 I 5,max of the inverter I 5 during the low-to-high and high-to-427 low transitions respectively. An expression of SR + and SR − 428 can be derived as follows: Therefore the SR is set by the values of V th n,p and I d 0n,p in the 432 adopted CMOS technology.

434
Both the proposed D2S converter in Fig. 5 and the ULV 435 standard-cell-based OTA in Fig. 8  In this subsection we compare the conventional inverter-453 based D2S against the proposed improved inverter-based 454 D2S from a simulation perspective, where all the invert-455 ers are taken from the same standard-cell library. The his-456 togram of the common-mode rejection ratio CMRR for 457 both the conventional and the proposed D2S is reported 458 in Fig. 9 after 200 Monte Carlo mismatch simulations. 459 Fig. 9 shows that the CMRR of the proposed D2S exhibits 460 a larger standard deviation with respect to the conventional 461 98184 VOLUME 10, 2022  The frequency response of the differential gain (magni-491 tude and phase) of the proposed standard-cell-based OTA is 492 depicted in Fig. 10, showing a differential gain of about 35 dB 493 with a phase margin mϕ 60 deg . The simulated differential 494 gain results to be about equal to the gain of the D2S with a 495 cascaded inverter: A v D (0) ≈ A 2 0 /2 ≈ 35 dB, as expected from 496 the theoretical analysis in section III. The frequency response 497 of the common-mode gain of the proposed standard-cell-498 based OTA is depicted in Fig. 11. Considering a differential 499 gain of about 35 dB, the CMRR at DC results to be about 500 27 dB, in very good agreement with the theoretical analysis 501 in section III.  The OTA has then been tested in closed-loop, non-503 inverting, unity gain configuration and the frequency 504 response is reported depicted in Fig. 12.

505
The time domain response to a full-swing input pulse is 506 shown in Fig. 13, highlighting the rail-to-rail characteristics 507 due to the enhanced D2S. The total harmonic distortion vs 508 a sinusoidal waveform of frequency 1 MHz whose amplitude 509 varies around 10% and 100% of the V DD is reported in Fig. 14. 510 VOLUME 10, 2022    lower input common-mode range. This behaviour is due to 530 the fact that no reference voltage is provided in the conven-531 tional D2S architecture and thus, under large common-mode 532 input signals, the diode-connected inverter (I 2 ) works with 533 a static voltage which strongly differs from the one of I 2 , 534 thus the accuracy of the differential to single-ended con-535 version is drastically reduced with respect to the proposed 536 D2S. On the other hand, in the proposed D2S, the local 537 feedback sets the node A at the reference voltage (V ref = 538 AGND), even for large commone-mode variations, and pro-539 vides a better accuracy and a larger input common-mode 540 range. The robustness of the architecture has been investigated with 543 respect to process, supply voltage and temperature (PVT) 544 variations and results of the analysis are summarized in 545 Tables 3-4. As it can be observed in Table 3, both the differ-546 ential and the common-mode gains are stable with respect to 547 different corners, as well as the offset and the phase margin, 548

578
The proposed amplifier has been tested under mismatch vari-579 ations and results of the analysis are reported in Tab. 5. As it 580 can be observed, the common-mode gain shows a certain sen-581 sitivity to mismatch variations due to the fact that matching 582 between g m 2 and g m 2 strongly affects the overall CMRR (see 583 eq. (8)). However, as outlined in Fig. 9, both the mean value 584 and the standard deviation result greater than the one showed 585 by the conventional D2S, and this allows to attain better 586 CMRR with a greater yield if compared with the conventional 587 D2S.

588
In addition, as outlined from Tab. 5, the GBW, the phase 589 margin, the P D and also the SR p,m result in very good agree-590 ment with typical simulations. The offset, which is one of 591 the main drawbacks of fully synthesizable OTAs results to 592 be in line with literature [3], [7], [30], [32] and, if compared 593 with the same OTA which exploits the conventional D2S 594 appears to be comparable, in spite of having adopted mini-595 mum sized standard cells for the error amplifier A D . Indeed, 596 under mismatch variations, the same architecture with con-597 ventional D2S shows an offset whose mean value is com-598 parable with the one presented in Tab. 5, but the standard 599 deviation results slightly higher (9.81 mV) than the one of 600 the proposed (8.91 mV). This result is not obvious, since 601 as outlined in Section III-D a further mismatch contribution 602 was added. However, the effect of the negative feedback is 603 to impose the reference voltage to the internal node A of the 604 OTA, thus under mismatch variations the internal nodes of the 605 OTA result to be better biased than the one in which the con-606 ventional D2S is exploited. Moreover, when the non inverting 607 buffer is closed, the contribution of σ A D to the σ V O,D2S can be 608 neglected, since is attenuated by the overall A V D gain. 609 VOLUME 10, 2022 In order to investigate the possibility of scaling the perfor-  The performance of the most performant ULV OTAs (i.e. 655 operating down to 0.3V of supply voltage) with respect to 656 Area-normalized FOMs have been depicted in Tab. 7. As it 657 can be observed, just [11] results in lower area footprint and 658 higher FOM S,A , FOM L,A . It has to be noted that also the DIG-659 ITAL OTA, presented in [2] results in low area-consumption 660 and good trade-off between performance and area consump-661 tion. Moreover, among the full custom OTAs, despite its high 662 also [32] shows very good values of the area normalized 664 FOMs.

666
In this paper we have proposed a novel topology of inverter- The netlist of the architecture depicted in Fig. 8 is as follow: