JCI-CAC: An Efficient Crosstalk Avoidance Code Considering Joint Capacitive and Inductive Effects

Capacitive coupling and inductive coupling are the two main factors in the occurrence of crosstalk fault in the communication bus. Among the various methods for reducing crosstalk fault, Crosstalk Avoidance Codes (CAC) codes are effective. However, with technology scaling, CACs are not able to prevent inductive effects. The proposed CACs methods are mainly based on capacitive coupling and do not consider inductive effects. To overcome this issue, a coding method is presented to avoid crosstalk fault called Joint Capacitive and Inductive CAC (JCI-CAC). The JCI-CAC coding reduces crosstalk faults by removing patterns of inductive coupling as <inline-formula> <tex-math notation="LaTeX">$'11111'$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$'00000'$ </tex-math></inline-formula> and capacitive coupling as <inline-formula> <tex-math notation="LaTeX">$'10101'$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$'01010'$ </tex-math></inline-formula>. The JCI-CAC offers a new method to generate a new numerical system for data encoding that has a low computational overhead so that it can be used for any desired width of the communication bus. The simulation results of the proposed JCI-CAC mechanism are investigated in different criteria of delay, power consumption and area overhead. The simulation results provide less power consumption in JCI-CAC than other recent approaches. There have also been improvements in overhead area and critical paths in JCI-CAC coding. The main novelty of this paper is to provide a new numerical system and a new coding algorithm with minimum cell area overhead and power consumption, considering inductance coupling in addition to capacitive coupling. Based on simulation results, power consumption of JCI-CAC in the 8-bit and 16-bit bus is reduced by up to 20% compared to SOTA and FPF (PS-Fibo, S2AP, Improved Fibo-CAC, Fibo-CAC) codings. Also, cell area overhead in JCI-CAC compared to SOTA coding in an 8-bit bus is reduced by 4.8%.


FIGURE 1. 3-bit communication bus capacitors.
The rest of the paper presents the necessary background 99 and motivations for the importance of crosstalk faults and 100 coding against crosstalk faults on the chips communication 101 bus. In the following, previous works in the literature are 102 reviewed, then the proposed method for crosstalk avoidance 103 coding is presented. Finally, the simulation results of the 104 proposed method are compared and analyzed in comparison 105 with other recent CACs methods in various aspects including 106 delay, power consumption, area overhead, and occurrence of 107 forbidden transition patterns. 109 The two main factors of crosstalk fault on the communication 110 bus are: capacitive coupling and inductive coupling [9]. When 111 two wires are adjacent to each other, an unwanted capacitor 112 is created between them; Which is called the coupling capac-113 itor [11]. On the other hand, changes in the magnetic field 114 around the wires lead to inductive coupling. Capacitive and 115 inductive coupling between adjacent wires leads to the mutual 116 interaction of the communication wires [9]. The phenomenon 117 of energy exchange between two wires is called crosstalk 118 fault [7]. 119 A communication bus with 3 wires is shown in Figure 1. 120 Each wire is represented as a cylindrical that is used to trans-121 mit a bit of data. Five electrical capacitors are formed next 122 to each bus wire in this way: the capacitor with the substrate 123 is shown as C g1 , the capacitor with the symbol C g2 that is 124 formed between the wire and the side plates of the wire, the 125 capacitors between adjacent wires are shown with C c [11]. 126 In addition to the capacitive coupling, inductive coupling 127 also occurs between the bus wires. The cause of inductive 128 coupling changes in the magnetic field around the wires. 129 Also, with increasing clock frequencies in the size of GHz, 130 the changes of the magnetic field around the bus wires inten-131 sify. As a result, each wire has significant inductive effects on 132 the surrounding wires. 133 To consider inductive coupling along with capacitive cou-134 pling in a communication bus on-chip, an electrical model 135 for a 5-bit bus is presented. Each wire b i in the bus has a 136 capacitor C iG (equal to the sum of capacitors C g1 and C g2 137 in Figure 1), resistance R i and inductor L i . Capacitors C (i,i+1) 138 and C (i,i−1) are considered to represent the effect of capacitive 139 coupling and capacitors I (i−2,i) , I (i−1,i) , I (i,i+2) and I (i,i−1) are 140 considered to show the inductive coupling impact [12]. 141 According to research in the transition to deep fabrica-142 tion technologies, wire height (shown with T int in Figure 1) 143 decreases at a lower rate than wire width (W int ) and distance 144 between adjacent wires (S int ) [13]. To have a closer look, 145 the transition voltage generated by capacitive coupling and 146 inductive coupling raises the signal level by up to 20% above 147 the supply voltage [14]. Therefore, the capacitor coupling 148 decreases at a lower rate than the substrate capacitor and   forms becomes the bottleneck of the system [16].   Thus, inductive effects cannot be ignored in the design of 196 high-performance circuits nowadays, especially for global 197 connections such as clock wires and signal buses [15]. Also, 198 the worst patterns due to inductive coupling are quite dif-199 ferent from capacitive coupling patterns, which makes the 200 previously proposed coding schemes inefficient. Therefore, 201 considering the effects of RLC to develop coding schemes to 202 reduce bus delay is very important, because inductive in the 203 design of high-performance circuits cannot be ignored [15]. 204 When the signals of adjacent wires change in opposite 205 directions, the worst-case transmission pattern delay occurs 206 due to capacitive coupling. In contrast, the worst-case transi-207 tion patterns are due to the effect of the inductive coupling, 208 which occurs by changing adjacent wires in one direction. 209 Therefore, considering inductive coupling is very important 210 for the development of encryption schemes to reduce bus 211 delay because today, inductive coupling can not be ignored 212 in the design of high-performance circuits.

213
To investigate the effect of inductive coupling in this 214 section, a classification of transition patterns is introduced 215 which is based on the general magnetic inductive on the 216 middle wire (k-th wire). The specified value in Eq (1) is 217 defined to measure inductive coupling [9]: In Eq. (1) in which is equal to the number of adjacent 220 wires considered for the mutual inductive effect, w i is equal to  Wire sizing and spacing [20], shielding [20], and repeater 255 insertion [21] are the samples of physical level mechanisms.

TABLE 2. Transition patterns classification based on
The skewing transition is part of the transistor level [20]. The 257 approaches of physical level and transistor-level have more 258 power consumption and area overhead than register transfer 259 approaches. In the register transfer level, Error checking and 260 correction (ECC) methods and Crosstalk Avoidance Codes 261 (CACs) to avoid compliance are introduced. In [22], [23] 262 and [24], some ECC-based methods are discussed. Among 263 the coding methods CACs effectively are used to reduce the 264 delay of crosstalk fault.

265
CACs prevent transition patterns to reduce the crosstalk 266 delay. For this purpose, CACs encode a data word into a code 267 word that lacks prohibition transitions. In one sense, CACs 268 can be classified into two types of CACs with memory and 269 memoryless. In memory-base CACs have to store all code 270 words of codebooks because the encoding needs to the previ-271 ously sent code word. In contrast, memoryless CACs encod-272 ing just belongs to the data word. Thus, the implementation 273 of memoryless CACs is simpler [9]. The previous approaches 274 like Forbidden Overlap Code (FOC) [25], Forbidden Transi-275 tion Code (FTC) [26], Forbidden Pattern Code (FPC) [27], 276 [28], [29], [30], [31], [32], One Lambda Code (OLC) [28] 277 and Improved OLC (IOLC) [10] are memoryless CACs. FPC 278 methods that do not have forbidden transition patterns are 279 also called Forbidden Pattern Free (FPF). The [27] method is 280 based on the fibonacci series numeral system. S2AP method 281 provides another numerical system to prevent the occurrence 282 of forbidden transition patterns in the 3-wire model, so that it 283 is complete and unambiguous [29]. The PS-Fibo method pro-284 vides another numerical system based on the fibonacci series 285 of forbidden transition patterns in the 3-wire model [ based on a numerical system that considers the effect of 320 capacitive coupling and inductive coupling at the same time.

321
SOTA coding for generating the code word depends on the 322 input parameter P [9]. Also, the production of the numerical Numerical System coding methods for crosstalk fault avoid-352 ance that are employed for preventing the occurrence of for-353 bidden transition patterns, map the transmitted data words to 354 the code words which are free from forbidden transitions [27]. 355 For this purpose, the transmitter requires an encoder circuit to 356 map the data word as v to the code word as (d m , . . . , d 2 , d 1 ) 357 where m is the width of the communication bus. The gener-358 ated code word is obtained based on the numerical system 359 by the coding algorithm. The receiver requires a 360 decoder circuit to perform inverse mapping. The decoder 361 obtains the transmitted data word by obtaining the sum of 362 the base coefficients in the code word as m i=1 d i U i . The 363 encoding/decoding process is shown in Figure 4. In Figure 4, 364 the input/output is shown as a parallelogram and process-365 ing/operation is shown as a rectangle. The whole process 366 from the start to the end is related to the encoding and 367 decoding process. In Figure 4, the first rectangle shows the 368 encoding process and the second rectangle shows the decod-369 ing process. Both encoder and decoder sides have the {U i } m i=1 370 numeral system and use it to perform encoding/decoding 371 operations.

372
In CAC methods, to send data in the communication bus, 373 they must be encoded so that the sent code word has no 374 forbidden transitions. Forbidden transition patterns are deter-375 mined by the transition classification model. It is necessary 376 to determine the model of transition classification to design a 377 coding method in the CAC algorithm. A CAC is presented 378 in the 5-wire model, considering the effects of capacitive 379 coupling and the effects of inductive coupling between com-380 munication bus wires. By directional transitions avoidance, 381 inductive coupling is avoided. On the other hand, by oppo-382 site transitions avoidance, capacitive coupling is avoided. 383 Therefore, the accuracy of this method is higher than other 384 crosstalk avoidance coding. The inductance impact is also 385 considered between the wires in the communication bus. As a 386 result, code words generated in the provided CAC do not have 387 the patterns 00000, 11111, 01010, and 10101.According to 388 Table 2, patterns 00100 and 11011 also causes much severe 389 inductance coupling effect. However, these patterns are not 390 considered as forbidden patterns because they are in Class 4, 391 while patterns 11111 and 00000 are in Class 5 as the worst 392 cases delay.

393
To encode a data message, first, a numerical system is 394 provided and then a coding algorithm using the correspond-395 ing numerical system is proposed so that each code word 396 has no directional or reverse directional patterns. Encoder 397 and decoder at the source and destination use a numeri-398 cal system to encode/decode data word. Since the auxiliary 399 functions in calculating the proposed numerical system have 400 been omitted, the proposed method is called Joint Capacitive 401 and Inductive CAC, JCI-CAC for short. JCI-CAC numerical 402 system has two main features: completeness and unambi-403 guity. JCI-CAC numerical system is complete so that all 404 data words in display data range can be encoded with it, 405 such that m is the width of the communication bus. otherwise, (2) 426 JCI-CAC numerical system can be generated recursively 427 at different widths of the communication bus by Eq (2). The 428 numerical system generated by Eq (2) in 5-bit to 10-bit bus 429 is shown in Table 3. For example, according to Eq (2), the 430 proposed numerical system for m = 8 (8-bit bus width) is 431 14 7 5 4 3 2 1 1 from the most valuable bit to the least 432 valuable bit from left to right. It should be noted that the U 433 numerical system in the mapping algorithm can be used to 434 generate word ambiguous and complete code so that it lacks 435 forbidden patterns.

436
In a binary numerical system as Since all zero and all one patterns have been removed 442 in this encoding, the minimum data word that can be sent in 443 the k-bit bus, indicated by the P parameter, must be found. 444 In this way, the value of P is added to data message v 445 and the resulting number is encoded. Therefore, the range 446 of the transmitted data is changed to [P, P + m i=1 f i ] so that 447 the parameter P is the first code word without the same 448 direction and opposite direction patterns. Consider Min and 449 Max functions to find the minimum and maximum data sent 450 as Eq (3) and Eq (4), respectively, without the same-direction 451 and opposite-direction transition patterns.

485
For example, in a 5-bit bus, the minimum value of the 486 transmitted data is P = 2 according to Eq (6). The code 487 words generated by Algorithm (1) are shown in Table 4.

488
According to

502
In this paper, the Modelsim simulator tool [37] is used to 503 verify the performance of the encoder and decoder in JCI-504 CAC method. Next, the Design Compiler [38] is used to 505 synthesize encoder and decoder to generate related hardware. 506 As a result, critical path delay, power consumption, and area 507 overhead are measured in encoder and decoder units. In this 508 section, the proposed methods are implemented and analyzed 509 using Modelsim and Design Compiler tools and the evalua-510 tion results are presented.

511
This section evaluates the JCI-CAC coding method com-512 pared to other coding methods including SOTA, FPF, and 513 IOLC codings. Both methods have been modeled using Ver-514 ilog language to compare JCI-CAC method with SOTA cod-515 ing and show the accurate assessment of area overheads, 516 delay, and power consumption. In this step, the correct oper-517 ation of the encoder and decoder is ensured. After ensuring 518 98354 VOLUME 10, 2022   in Figure 6. Due to the high value of PDP in FPF(PS-Fibo, 554 S2AP, Improved Fibo-CAC, Fibo-CAC) codings, the diagram 555 in Figure 6 is drawn as two vertical values. The improvement 556 of JCI-CAC PDP compared to SOTA CACs in 8-bit, 16-bit 557 and 32-bit busses is 23%, 22%, and 46%, respectively.

559
Area overhead is one of the measurement criteria of CAC 560 method. The area overhead is actually the area related to 561 CAC, the amount of which has been checked in the proposed 562 method compared to other CAC methods in different widths 563 of the communication bus. Since CAC methods can be used 564 in the communication bus with different widths, the area 565 overhead has been measured in 8-, 16-and 32-bit widths.  Table 7.

571
According to Table 7, cell area overhead in JCI-CAC com-572 pared to SOTA coding in 8-bit bus is reduced by 4.8%. On the 573 other hand, cell area overhead has increased by increases in 574 the width of the communication bus by up to 3% in the 32-bit 575 bus. It can be concluded that JCI-CAC performs better in 576 lower width busses. A comparison diagram of cell area over-577 head in SOTA and JCI-CAC is shown in Figure 7. According 578 to the experimental results of JCI-CAC compared to SOTA 579 coding, in the 32-bit bus despite a minimum reduction of 20% 580 in power consumption, 3% increase in cell area overhead is 581 negligible. 582 VOLUME 10, 2022  means that more wire usage is used to display more code 605 words, which reduces the redundant wire. To investigate the effect of the proposed numerical system on 609 reducing crosstalk fault effects, a simulation environment has 610 been developed. According to the explanations of the previ-611 ous sections, analysis of power consumption and wire delay 612 is important, because these factors are affected by crosstalk 613 fault. Various applications have been applied to generalize 614 the results. As a result, the simulation is checked on real 615 data. To examine the proposed method on real data, three 616 standard criteria video streaming of the foreman, football2, 617 and mobile3 have been used to obtain real repetitive patterns 618 and transmission factors. A comparison of the occurrence 619 rates of each pattern class on the 6 video input files mentioned 620 is shown in Figure 9.

621
The occurrence of 5-wire transition patterns on 6 input files 622 in two modes encoded by JCI-CAC and without encoding is 623 shown in Figure 9. The delay of the class patterns increases 624 from 0C to 5C, respectively, from left to right of the dia-625 grams in Figure 9. According to the diagrams, the incidence 626 of 2C to 5C class patterns in JCI-CAC is zero due to the 627 removal of patterns 00000 and 11111. Based on Figure 9, 628 the incidence of Class patterns 2C, 3C, and 4C in JCI-CAC 629 has been reduced by up to 26%, 11%, and 3% compared to 630 According to the evaluation results, the power consump-659 tion of JCI-CAC framework has improved by at least 20% 660 compared to SOTA coding. Therefore, imposed area over-661 head of 3% can be ignored due to the increase in coding 662 calculations. Also, the reduction of the PDP criterion is at 663 least 22% compared to the SOTA method.

664
One of the limitations of the proposed method is its equal 665 delay compared to the SOTA method. However, due to the 666 reduction of cell area overhead and power consumption com-667 pared to existing methods, it has valuable results.

669
Connection between chips become an important bottleneck in 670 performance and energy consumption in chip design, when 671 the design scale is reduced to nanometers. System perfor-672 mance is introduced under the reliability factor. Since the 673 occurrence of errors and defects due to the crosstalk is one 674 of the issues that jeopardize the reliability of chips and data 675 in communication bus, it needs to be carefully studied. The 676 proposed methods for crosstalk lead to delay, power con-677 sumption, and area overloads in the communication bus on 678 the chip. Therefore, the imposed overhead on the chip is 679 one of the important issues studied in the field of reliabil-680 ity. By reducing the scale of the devices to the nanometers, 681 an important bottleneck in performance and power consump-682 tion in the chip design is the connection between the chips.