Wide-Bandwidth Electronically Programmable CMOS Instrumentation Amplifier for Bioimpedance Spectroscopy

An instrumentation amplifier (IA) with continuous tuning of the voltage gain, suitable for operation over a wide frequency range, and aimed to electrical bioimpedance spectroscopy, is proposed. The operation principle of the IA is based on indirect current feedback (ICF), which leads to an almost-constant bandwidth regardless of the value of the programmed voltage gain. The use of improved voltage followers in the transconductors required in the ICF technique allows achieving a compact implementation with a bandwidth compatible with bioimpedance spectroscopy applications. The tuning strategy relies on a continuously programmable current mirror that can be electronically adjusted by means of a control current. The IA has been designed and fabricated in 180 nm CMOS technology to operate with a 1.8-V single supply. The experimental characterization of the silicon prototypes showed a gain programmability range higher than 45 dB, between −4.6 dB and 41.2 dB, a BW around 3 MHz, and a maximum CMRR at DC higher than 86 dB, all this with a minimum current consumption of $144.8~\mu \text{A}$ and an area occupation of 0.0196 mm2.

indirect current feedback technique [6], [29] the stacking of 90 blocks is avoided and the feedback loop involves only the 91 output transconductor, thus resulting more suitable for low-92 voltage wide-bandwidth applications. 93 A. CONCEPTUAL BLOCK DIAGRAM OF THE IA 94 The block diagram of the proposed IA is illustrated in 95 the dotted box of Fig. 1. As observed, it consists of 96 two transconductors, G mI and G mO , a current-mode gain 97 block, k CM , and a summing stage, . The voltage-to-current 98 (V-to-I) converter G mI generates an output current, i I , from 99 the input differential-mode (DM) voltage, v I ,DM , whereas 100 G mO converts the voltage difference V REF − v O into the 101 current i O . The signal V REF is a reference voltage used set 102 the DC level of the output signal. The current produced by 103 the input transconductor is multiplied by the gain of a current 104 mirror, k CM , and the resulting signal, k CM · i I , is compared in 105 the summing stage with the current generated by the output 106 V-to-I converter. The action of the feedback loop established 107 around G mO is twofold. On the one hand, the resulting current 108 at the output of the summing stage is forced to be ideally zero, 109 thus making currents k CM · i I and i O equal. On the other 110 hand, the virtual ground principle at the input of G mO induces 111 a DC voltage level equal to V REF at the output of the IA. 112 The transfer function of the block diagram depicted in 113 Fig. 1 can be expressed as: where R out and C L are the output resistance and the load 116 capacitance, respectively. Assuming a sufficiently high gain 117 in the loop around G mO , the voltage gain, A v , and the BW of 118 the IA can easily be deduced from (1) to be: The gain of the IA can be nominally adjusted by means of the 122 ratio G mI /G mO and subsequently programmed by means of 123 the current gain k CM . Besides, the selection of an appropriate 124 value of C L is used to set the BW, also obtaining a suitable 125 phase margin for the feedback loop. It is worth to note that the 126 BW of the IA does not rely on the gain k CM , which ensures 127 a roughly constant frequency response over the entire gain 128 programmability range. The electronic programmability of the voltage gain of the 131 proposed IA is based on the continuously tunable current 132 mirror illustrated in Fig. 2. In a conventional current mirror 133 the same gate-to-source voltage is applied to the input and 134 the output transistor, obtaining a fixed current gain that relies 135 on the ratio of the geometries of both devices provided that 136 they are biased in saturation. The principle of operation of 137 VOLUME 10, 2022 and V A enables the electronic programmability of the circuit 178 section.

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A particular expression can be easily derived for the current 180 gain of the current mirror in (4). Nevertheless, to do so 181 an inversion region, i.e., weak, moderate, or strong, has to 182 be assumed. As the principle of operation of the proposed 183 tunable current mirror is suitable for any inversion level, 184 a design space has been built by means of simulations instead. 185 The current gain of the programmable current mirror has 186 been evaluated by modifying the biasing current of the dif-187 ferential pair, I BT , the aspect ratio of the differential pair 188 driver transistors, (W/L) MDP1−2 , and the aspect ratio of the 189 devices in the current mirror, (W/L) MCM 1−2 . The current 190 I TUN , which is considered the control variable to obtain elec-191 tronic programmability, has also been swept in the three cases 192 indicated. The corresponding design spaces are depicted in 193 Figs. 3a, 3b, and 3c, where the input current was fixed to 194 the value i IN = 10 µA. In Fig. 3a the biasing current of 195 the differential pair I BT was swept in the range [1:101] µA, 196 while the control current I TUN was moved between 5% and 197 95% the value of I BT . As observed, the output current of 198  where R, MD, MBD, and MF are the linearization resistor 245 and the driver, current source, and feedback transistor, respec-246 tively, at the input and output transconductors. As observed 247 in the most right term in the denominator of (5), the load 248 regulation effect is highly reduced by the gain of the feedback 249 loop implicit in the SSF, i.e., by the term g m,MF /(g o,MD + 250 g o,MBD ), thus leading to a voltage gain very close to unity. 251 As a consequence, the effective transconductance of the input 252 and the output V-to-I converter can be expressed as: where R represents resistors R I and R O in G mI and G mO , 255 respectively. As observed in Fig. 4, the current signal pro-256 duced in the output transconductor, i O , is conveyed to the 257 summing stage by means of current mirrors with a fixed cur-258 rent gain 1:1. Alternatively, the two tuning sections enclosed 259 in dashed boxes in Fig. 4 have been incorporated in order to 260 amplify the current signal generated by G mI , i.e., i I , which 261 VOLUME 10, 2022 appears at the summing stage as k CM · i I . Considering the 262 expression in (6) and taking into account that the linearization 263 resistors at the input and the output V-to-I converter are 264 named in Fig. 4 as R and k R R, respectively, the voltage gain 265 and BW of the proposed IA can be written as: The gain of the IA can be adjusted by means of the ratio 269 G mI /G mO = k R and subsequently programmed by the current    It is worth to mention that the systematic offset of the 315 single-ended structure proposed has been reduced by includ-316 ing cascode transistors in each SSF cell, devices MFCI and 317 MFCO, and by properly sizing the PMOS current mirror, 318 transistors M3-M4, used to carry out the differential-to-319 single conversion. Besides, capacitors C C1 to C C4 have been 320 included to stabilize the frequency response of the four SSF 321 cells used in the input and the output V-to-I converter.

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The proposed IA has been designed and fabricated in 180 nm 324 CMOS technology to operate with a single supply voltage 325 of 1.8 V. A microphotograph of the circuit, which occupies a 326 silicon area of 0.0196 mm 2 , is shown in Fig. 5a, where the lay-327 out is also detailed. Besides, the transistor aspect ratios of the 328 IA are given in Table 1. The experimental characterization of 329 the electronically programmable IA has been carried out over 330 7 different samples of the silicon prototype and the general 331 testbench used in the different measurements is represented 332 in Fig. 5b. The on-chip voltage buffer prevents an excessive 333 loading of the output node of the IA and helps to keep a 334 nearly constant BW regardless the value of the off-chip load 335 capacitance.

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The biasing current, I B , was adjusted to be 10 µA, which 337 led to a tail current of 20 µA for the SSF blocks and 10 µA 338 for the tuning sections. The reference voltage, V REF , used to 339 establish the DC output level and to bias the gate terminal 340 of the cascode transistors, was set equal to 0.9 V, i.e., to 341 midsupply. The minimum gain of the tunable current mirrors 342  The AC characterization of the IA allowed also determin-385 ing the BW, which is depicted in Fig. 7 as a function of I TUN . 386 It remains roughly constant over the entire programmability 387 range with an approximate measured value of around 3 MHz. 388 When the level of the tuning variable I TUN is adjusted to 389 values close to the extremes, i.e., zero and I BT , the DC 390 current through one of the two branches of the tuning section 391 decreases. As a result, the position of the corresponding 392 non-dominant pole is reduced, thus resulting in a drop of 393 the BW of the IA. The difference between experimental 394 and simulated values of the BW, also illustrated in Fig. 7, 395 is ascribed to the impact of the test buffer on the capacitance 396 at the output node of the IA, which is higher than expected 397 from simulations.

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Frequency measurements gave rise too to the experimental 399 values of the CMRR, which is represented in Fig. 8 as a 400 function of I TUN in the range [0.3:9.7] µA and compared to 401 the simulated response. The simulated CMRR was obtained 402 from a set of 1000-run process and mismatch Montecarlo 403 analyses, in which all the parameters of the devices were 404 randomly varied with a value of sigma equal to 3. The error 405 bars (standard deviation) associated to the each simulated 406 value of the CMRR (mean value) comprise the measured data 407 in all the cases. The minimum values of the experimental 408 CMRR, around 55 dB, take place for the lowest values of the 409 DM voltage gain, that is, for high values of I TUN , whereas the 410 maximum measured value of the CMRR is higher than 86 dB. 411 The CMRR was also measured at the frequency of the 412  as a function of I TUN at a frequency of 1 MHz. As observed 433 in the plots, experimental and simulated data show a similar 434 trend, even though the minimum measurable noise is limited 435 by the test setup. For high levels of I TUN , that is, for low 436 values of the voltage gain, the noise of the input and the output 437 V-to-I converter have a similar contribution to the total noise. 438 As the gain of the instrumentation amplifier is increased the 439 input-referred noise of the output transconductor becomes 440 negligible, thus leading to a lower overall input-referred 441 noise. Besides, the noise was measured for I TUN = 5 µA and 442 integrated in the frequency band between 100 Hz and the BW 443 and the corresponding value is reported in Table 2. 444 The experimental performance of the proposed electroni-445 cally programmable IA is summarized in Table 2, where it is 446 also compared to other similar solutions previously reported. 447 As observed in Table 2, the proposed solution leads to the 448 widest programmability range of the IA gain, featuring a 449 BW suitable for bioimpedance spectroscopy applications and 450 presenting a current consumption similar to that of the other 451 proposals. In general, current mode techniques [21], [22], 452