Parameters Optimization of an Intermediate Frequency Isolated SiC Power DC-DC Converter

To improve the lightweight level of auxiliary converters for urban rail vehicles, full SiC intermediate frequency auxiliary converters have become a trend. Aiming at its core component, a full SiC intermediate frequency isolated DC-DC converter using Boost + LLC topology is studied in this paper. The working principle and characteristics of the converter are analyzed in detail. Based on the operating characteristics of the LLC resonant converter and the realization mechanism of soft switching, an optimization design method of the resonant parameters is proposed, which can make LLC resonant converters exhibit the characteristics of DC transformers and realize soft switching in the full load range. Considering the power losses of the converter and the voltage stress of SiC MOSFET, the intermediate bus voltage design method is given. Finally, the correctness of the parameter design method is verified by simulation and experiment, and the performance of the full SiC intermediate frequency isolated DC-DC converter is analyzed. When the input voltage is 1500V and the output power is 15kW, the efficiency of the converter reaches 96.21%. Compared with the Si intermediate frequency isolated DC-DC converter, the power density is improved by 80.62%.

The literature [6], [7] investigated full SiC intermediate fre- 23 quency isolated DC-DC converters with DC 750V input using 24 a phase-shifted full-bridge topology. In the literature [7], the 25 full SiC intermediate frequency isolated  was rated at 40 kW and operated at 40 kHz, reducing the 27 The associate editor coordinating the review of this manuscript and approving it for publication was Zhilei Yao . size of the magnetic components by nearly 80% compared to 28 the silicon intermediate frequency isolated DC-DC converter 29 that operated at only 5 kHz. In the literature [8], a full SiC 30 intermediate frequency isolated DC-DC converter with DC 31 1500V input is studied, also using a phase-shifted full-bridge 32 topology. Since the maximum withstands voltage of current 33 commercial full SiC power modules is only 1700V, it uses two 34 sets of phase-shifted full-bridge input-series-output-parallel 35 (ISOP) structure. The converter is rated at 70kW and operates 36 at 40kHz with a full load efficiency of 95%.

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It should be noted that although the phase-shifted 38 full-bridge topology has been successfully used in full SiC 39 intermediate frequency isolated DC-DC converters, some 40 shortcomings should be pointed out. First, the resonant states 41 of the overrunning bridge arm and the lagging bridge arm 42 in the phase-shifted full-bridge converter are not identical, 43 and the lagging bridge arm is more difficult to achieve zero-44 voltage turn-on of its switches [7], [8]. Second, the converter 45 has the phenomenon of effective duty cycle loss during the 46 primary-side commutation [7], [8]. Finally, due to the presence of the secondary filter inductor, there are large voltage 48 spikes in the rectifier diode when it is turned off, which not 49 only affects the system efficiency but also causes oscillations. 50 Especially, with the adoption of SiC power devices, the oper-51 ating frequency of the converter is significantly increased and 52 the voltage spikes and oscillation problems are even worse, 53 thus requiring additional buffering and absorption circuits [7], 54 [8], [9]. At low power conditions, the efficiency improvement 55 of the converter is not significant. converter has excellent soft switching performance, so the 63 system has high efficiency [1], [10]. The increase in operating 64 frequency results in a significant reduction in the weight and 65 size of the magnetic components in the system. Combined  The equivalent circuit of the interleaved Boost converter is 100 shown in Fig. 2, where V in is the input voltage, V cb1 and 101 V cb2 are the output voltages of the two Boost converters, 102 respectively. Since the boost inductors L b1 and L b2 of the 103 two converters are connected in series, they can be treated 104 as equivalent inductor L b in the analysis, and have L b = 105 L b1 + L b2 , v Lb and i Lb are the voltage and current of the 106 equivalent inductor L b , respectively. Since the duty cycle of 107 the two Boost converters is the same, with the same DC 108 voltage gain of the two full-bridge LLC resonant converters, 109 there is V Cb1 = V Cb2 = V Cb established. The drive signals 110 of Q 11 and Q 21 are always kept low, using only their body 111 diodes, and Q 12 and Q 22 are used as main switching tubes 112 and interleaved control. According to the relationship between V in and V cb , the 114 interleaved Boost converter has two operating modes with 115 duty cycle D b 0.5 and D b >0.5. Figure 3 gives the main 116 operating waveforms in these two modes, T sb is the switching 117 period. In both operating modes, the drive signals of Q12 118 and Q22 are staggered by 180 • , and the current pulsation 119 frequency of the inductor is twice the switching frequency f sB . 120 VOLUME 10, 2022 Operating mode I (V in ≥ V cb , D b ≤0.5): When Q 12 is on 121 and Q 22 is off or Q 12 is off and Q 22 is on, v Lb = V in − V cb , 122 i Lb rises linearly; while when Q 12 and Q 22 are off at the same 123 time, v Lb = V in −2V cb , i Lb decreases linearly. The operating 124 waveform is shown in Fig. 3(a).

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And inductor current ripple i Lb /I Lb can be expressed as

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where i Lb and I Lb are the pulsating and RMS values of 139 the inductor current, respectively, and P in is the input power.

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Then the maximum i Lb /I Lb can be derived as Define f r as the resonant frequency of C r and L r , and 163 f p as the resonant frequency of C r , L r , and L p , as shown 164 in (4) and (5), respectively. The zero-voltage turn-on of SiC 165 MOSFETs (zero-voltage-switching, ZVS) and zero-current 166 turn-off of rectifier diodes (zero-current-switching, ZCS) can 167 be achieved simultaneously when the switching frequency 168 f s is between f p and f r . And, the closer the f s is to f r , the 169 higher the efficiency of the converter. When f s = f r , the LLC 170 resonant converter works at the highest efficiency point.
Since there will be a slight error in the resonance parame-174 ters in practical applications, this paper chooses f s slightly less 175 than f r , when the efficiency of the full-bridge LLC resonant 176 converter is close to the highest and can ensure good soft-177 switching performance. The main waveforms in this operat-178 ing mode are given in Fig. 5, from which it can be seen that 179 a switching cycle can be divided into 8 time periods in this 180 operating mode, and the operating process is analyzed next. 181 Stage 1 [t 0 , t 1 ]: At the moment of t 0 , Q 1 and Q 4 turn on with 182 zero voltage, i Lr is greater than i Lp , D R1 and D R4 conduct, 183 the primary side transfers energy to the secondary side, v Lp 184 is clamped to nV o , i Lp rises linearly, and only L r and C r 185 participate in resonance. In this period, the expressions of i Lr 186 and i Lp are shown where, ω r =2πf r , is the resonant angular frequency; I Lrm is 189 the peak resonant current; θ is the phase angle between i Lr 190 and the resonant cavity input voltage v AB : i Lp still satisfy (9), and the voltages of to fully realize ZVS, two conditions need to be satisfied: First, 218 the peak value of i Lp should be large enough to ensure that 219 the junction capacitance can be discharged to zero within t d , 220 according to which the range of L p can be obtained as (10); 221 second, in the dead time, i Lr cannot be reversed, otherwise, 222 the junction capacitance of the SiC MOSFET will be charged 223 immediately after it is discharged to zero, and ZVS cannot be 224 achieved. The condition in (11) must be fulfilled to make i Lr 225 not reverse during the dead time.
where, λ = L p /L r ; f n = f s /f r ; Q = 2πf r L r /R ac ; R ac = 8 240 n 2 R Ld /π 2 . To achieve ZVS, Z in,AB needs to remain inductive 241 over the full load range so its imaginary part needs to be large 242 than zero, so the quality factor Q should satisfy (14).
From (12), it can be seen that the voltage gain of the con-245 verter is influenced by the resonance parameter, the switching 246 frequency, and the load at the same time. Fig. 6(a) shows the 247 curve of M versus f n for different Q. When the value of Q is 248 large and does not satisfy (14), it can be seen that M decreases 249 as Q increases, and the voltage gain curve will be below the 250 voltage gain curve of the resistive resonant network. At this 251 time, the resonant network is capacitive, ZVS can not be 252 achieved, and the smaller the Q value, the closer the voltage 253 gain curve to the curve at no load, that is, the less M is affected 254 by the load. It can also be seen that when f n = 1, M is not 255 affected by the load and is constant at 1.

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The curves of M versus f n when the resonant network is 257 resistive for different λ are given in Fig. 6(b). As λ increases, 258 the voltage gain curve keeps shifting downward, which, com-259 bined with the analysis of Fig. 6(a), shows that the range 260 of loads that can make the resonant network inductive is 261 VOLUME 10, 2022 expanded. It can also be seen that as λ increases, the slope 262 of the voltage gain curve at f n slightly less than 1 is closer to zero, which means that M can be stabilized at the target value 264 even if there is some error in the resonance parameters. The conditions for achieving ZVS when the resonant net-290 work is inductive are given in (10) and (11), and the range of 291 values of L p can be obtained by combining them. The (16) 292 gives the expression of I Lrm . Substituting (10), (15) and (16) 293 into (11), we can obtain the function F(L p ) in (17), and ZVS 294 can be realized when the resonant network is inductive only 295 when F(L p ) ≥0. Fig. 7 gives the relationship curve between F(L p ) and L p . 300 According to the condition that F(L p ) ≥0, the range of 301 L p values given by (10) can be divided into three intervals. 302 In region 1 and region 3, both have F(L p ) ≥0, and the 303 LLC resonant converter has the conditions to realize ZVS. 304 However, from (6) and (16), it can be seen that the larger the 305 L p , the smaller the i Lp and i Lr , and the smaller the conduction 306 loss and turn-off loss of the primary-side SiC MOSFET for 307 the same load. Meanwhile, according to the analysis results 308 in Section II.C, the larger the value of λ, the more stable the 309 voltage gain of the LLC resonant converter, while the increase 310 of L p and the decrease of L r can increase λ. In summary, the 311 value of L p should be 312 L p = t d 8f r C ds (18) 313 From (14), the value of λ determines whether the reso-314 nant network can maintain inductance under the constant f n . 315 Before designing L r , it is necessary to design λ. From (14), 316 the range of values of λ that enables the resonant network to 317 maintain inductance is Besides, the value of λ also determines the stability of the 320 voltage gain of the LLC resonant converter. In the full load 321 range, let the maximum deviation of the normalized voltage 322 gain M be δ, which can be obtained from (12).
As can be seen from (5) Combining (19) and (21), the value of λ that stabilizes the 334 voltage gain and keeps the resonant network inductive is From which, due to the large load power, L r can be taken After the design of L r is completed, the resonant capaci-341 tor C r is designed as The power device losses of the LLC resonant converter 382 are mainly composed of the pass-state losses of the SiC 383 MOSFETs and the rectifier diodes. The total pass-state losses 384 of SiC MOSFETs in the two LLC resonant converters are 385 P con,LLC = R ds,on 8R 2 In the two LLC resonant converters, the total on-state loss 387 of the sub-side rectifier diode is where V FD is the forward conduction voltage drop of the recti-390 fier diode. It can be seen that the loss of the secondary rectifier 391 circuit is independent of the intermediate bus and depends 392 only on the output power and output voltage. In summary, the 393 total power device losses of the two LLC resonant converters 394 can be obtained as Combining (29) and (32), the total power device loss of the 397 whole converter can be obtained as 398 P loss,total = P Boost + P LLC (33) 399 Since the input voltage range of the auxiliary power supply 400 system is large, Fig. 8 gives the total power device loss curves 401 for different input voltages. From Fig. 8, it can be seen that 402 the total power device loss decreases as the input voltage 403 VOLUME 10, 2022    operating conditions are given in Fig. 9. It can be seen that 432 v Cb is stable at 1050 V, while the pulsation frequency of the 433 inductor current is twice the switching frequency.

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The main simulated waveforms of the LLC resonant con-435 verter for different load cases are given in Fig. 10. It can 436 be seen that the ZVS of the SiC MOSFET and the ZCS of 437 the rectifier diode is achieved simultaneously in the full load 438 range. i Lr is already small when the SiC MOSFET is turned 439 off, so the SiC MOSFET also approximates the ZCS. It can 440 also be seen that the output voltage is stable at about 700 V 441 when the load is varied, which indicates that the LLC resonant 442 converter has good voltage gain stability. 443 Fig. 11(a) gives the simulated waveform of the LLC res-444 onant converter at L p =135µH, when L p is in region 1 in 445 Fig. 7 and F(L p ) 0. Despite the realization of ZVS, the 446 smaller L p leads to a high excitation current and a low 447 efficiency of the converter. Fig. 11(b) gives the simulation 448 waveform when L p =800µH, at this time L p is in region 2 in 449 Fig. 7, F(L p )<0. At this time, the resonant current in the dead 450 zone is reversed, and the ZVS is not realized effectively.

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The above simulation results verify the correctness of the 452 proposed parameter optimization design method.   two submodules, and i SIV is the single-phase output current of 472 the three-phase inverter. It can be seen that the intermediate 473 bus voltage and output current of the two sub-modules are 474 well synchronized without additional voltage and current 475 equalization control strategies, and the full-bridge LLC reso-476 nant converter plays the role of a DC transformer. The above 477 experimental results verify the correctness of the parameter 478 optimization design method proposed in Section III of this 479 paper.    Fig. 16  proposed. After that, the correctness of the above parameter 508 design method is verified by simulation and experiment, and 509 the converter performance is analyzed. The efficiency of the 510 converter reaches 96.21% at an input voltage of 1500V and 511 an output power of 15kW.  Trans. Ind. Electron., vol. 58, no. 7, pp. 2926-2934, Jul. 2011, doi: 565 10.1109/TIE.2010 [14] F. Wang, X. Wang, and X. Ruan, ''An optimal design scheme of inter-