A-Si TFT Integrated Gate Driver Workable at −40°C Using Bootstrapped Carry Signal

A thin-film transistors (TFTs) integrated gate driver which can work well at low temperature down to <inline-formula> <tex-math notation="LaTeX">$- 40\,\,^{\circ} \text{C}$ </tex-math></inline-formula> is proposed and demonstrated. The carry signal (CN) of the driver, being generated through the voltage bootstrapping approach using a CN-connected capacitor, is used to pre-charge the following stage of the driver. As the rising and falling time of CN is much shorter than that of the gate driving signal GN, the bootstrapping voltage is increased and voltage loss of the pre-charge transistor can be much reduced, to avoid the driver’s malfunction at low temperature. This structure further benefits maintaining the driving speed over long operation time at high temperature. On the other hand, the GN, instead of CN, is used to reset the gate driver to suppress the voltage feed-through effects. One single stage of the driver consists of 11 TFTs and 2 capacitors, driven by 4 clock signals with the duty ratio of 25%. An a-Si:H TFTs implemented single stage circuit of the driver occupies an area of 250 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}\times 1099\,\,\mu \text{m}$ </tex-math></inline-formula>. Measurements show that the output voltage magnitude can be maintained well when temperature varies from <inline-formula> <tex-math notation="LaTeX">$- 40\,\,^{\circ} \text{C}$ </tex-math></inline-formula> to 80 °C. Moreover, the rising-time and falling-time increase of the output pulse are both less than <inline-formula> <tex-math notation="LaTeX">$3~\mu \text{s}$ </tex-math></inline-formula> after 240 hours of the accelerated high temperature aging operations.

increasingly challenging [5], [6], [7]. This is because the 23 effective addressing time of gate-lines is limited and pixel 24 charging ratio is insufficient due to the increase of load- 25 ing resistance and capacitance at gate driver's output elec-26 trodes [8]. In addition, at lower temperature, the effective 27 gate addressing time is further reduced due to the serious 28 degradation of circuit speed, and even malfunction of gate 29 The associate editor coordinating the review of this manuscript and approving it for publication was Yen-Lin Chen . driver circuit, especially for vehicle or mobile displays [9]. 30 On the other hand, at high temperature, there are relia-31 bility issues after gate drivers experience long operation 32 time. 33 Up to date, hydrogenated amorphous silicon (a-Si:H) TFTs 34 are still playing important roles in the flat panel display indus-35 try, thanks to the mature manufacturing process, low fabrica-36 tion cost, and good electrical uniformity over large substrate 37 area, [11], [12], [13]. However, the workable temperature 38 range for a-Si:H TFT based gate driver is a critical issue as 39 the speed and stability are seriously degraded at low and high 40 temperature, respectively [14], [15]. This is because there is 41 conduction current decrease at lower temperature, while the 42 threshold voltage shift with fast speed for long operation time 43 at high temperature, [16], [17], [18]. Therefore, new circuit 44 schematic with increased circuit speed is of great importance, 45 to extend applications of a-Si:H TFT circuits in vehicle and 46 mobile display panels. displays [19], [20], [21], [22], [23].   electrode of T2, is connected to G N+2 , namely the reset signal 103 (i.e. RST) for the pulling-down period. For the conventional 104 gate driver circuits, RST is usually connected with C N+2 105 or C N+1 .

106
For a complete display frame, there are four successive 107 operation periods, viz. (1) the pre-charging period, (2) the 108 bootstrapping period, (3) the pulling-down period, and (4) 109 the low-level-holding period. The operating principles will be 110 described in details as follows.
In the P1 period, T1 is turned on as both C N−1 and G N−1 113 are with V H . Then through T1, charges are accumulated at 114 the Q node, until the level of Q node reaches V H -V TH1 by 115 the end of P1 period, where V TH1 is the threshold voltage of 116 T1. Consequently, the driving TFTs (T3a and T3b) are turned 117 on in prior to the bootstrapping period. As the level of CLK is 118 V L , C N and G N are expected to maintain with the low voltage 119 level. In addition, T5 and T7 are turned on to pull down the 120 gate electrode of T6 and Q B . Then T8, T9 and T10 are turned 121 off, and the possible charge loss of Q node can be mitigated. 122

123
In P2 period, node Q is floating as T1 is turned off due to 124 the falling of C N−1 and G N−1 from V H to V L . In addition, 125 the other TFTs associating with Q node are also turned off.  According to the charge conservation law, the level of Q node 130 can be bootstrapped to V QH2 , which helps keeping T3a and 131 T3b with high conductance. Here, the value of C2 is much 132 larger than C1 (C2>C1), thus the bootstrapping voltage of 133 node Q can approximately be expressed by On the other hand, the bootstrapping capacitor is connected 136 to G N for conventional designs [3], [12], [14], and then the 137 bootstrapping voltage of node Q can be expressed by  In the first half of P3 period, due to the bootstrapping princi-150 pal [21] again, the level of Q node is pulled down to V QH3 . 151 As node Q is still floating, the value of V QH3 is approx-152 imately equaling to V QH1 . This means, T3a and T3b are 153 maintained on and can be reused to discharge C N and G N , 154 respectively.

155
While in the second half of P3 period, the level of G N+2 and 156 C N+2 are raised up. Then charges of node Q can be removed 157 and T3a and T3b are turned off in prior to the secondary CK 158 pulse to suppress the possible feedthrough voltage. In the P4 period, node Q B can be charged with V H through 161 T6 following the rising of CK from V L to V H . Then, T8, T9 162 and T10 are turned on to maintain the low level of node Q, 163 C N and G N , respectively. On the other hand, if the level of 164 CK is turned to V L , node Q B is discharged through T6, and 165 then T8, T9 and T10 are turned off. For the presented gate 166 driver circuit, the duty ratio of low-level-holding transistors 167 can be reduced to 25%. As being avoided from stressing of 168 constant direct voltage, the low-level-holding transistors will 169 have improved stability with reduced V TH shift ( V TH ).

171
The proposed gate driver is manufactured with the standard 172 5-mask a-Si:H TFT process. That is to say, both the gate 173 driver and the display pixel array were implemented using 174 a-Si:H TFT process. The channel length of all TFTs is 5 µm. 175 VOLUME 10, 2022  The overlap between gate-to-source electrodes and gate-to-176 drain electrodes is 3 µm. Then the parasitic gate-to-drain 177 capacitance (i.e. C GD0 ) and gate-to-source capacitance (i.e.  Table 1. were explained and modelled in [24] and [25]. 205 The gate driver samples were cooled down using a closed 206 incubator, while being connected to the external timing 207 and voltage sources through flexible printed circuit (FPC). 208    with C N+2 . These serious distortions in the waveforms of 227 G1 and G2 are caused by the ripple waveforms of C3 and 228 C4, which are sensitive to voltage feed-through effects due to 229 smaller loading capacitance of carry signals.Aging measure-230 ments for the conventional [3] and the proposed gate drivers 231 were conducted and compared at the high temperature of 232 80 • C. To accelerate the aging test, the frame period time is 233 reduced to 620 µs, while the conventional frame period time 234 is 16 ms. Fig. 7 (a) and (b) show the transient response of 235 the conventional and the proposed gate driver, respectively. 236 While Fig.7 (c) and (d) presents the extracted rising and 237 falling time for the conventional and the proposed gate driver, 238 respectively. After aging test of 240 hours, the magnitude of 239 output waveforms of the conventional gate driver is decreased 240 by 5 V, and rising and falling time are increased by 7.5 µs, 241 and 3 µs, respectively. While for the proposed circuit, there 242 is almost no voltage magnitude loss and both the increasing 243 of rising and falling time are less than 3 µs. This can be 244 attributed to the better driving ability of the proposed driver 245 circuit, as the over-drive voltage of T3a and T3b is increased 246 as shown in eq. (1) and (2). These differences become obvious 247 when Vth shift of T3a and T3b are large after long operating 248 time.

IV. RELIABILITY MEASUREMENT RESULTS
249 Table 2 lists the performances comparison among this work 250 and other related one, in terms of circuit structure, signal 251 numbers, and reliability. With a compact circuit topology, the 252 proposed gate driver is effective to suppress the driving ability 253 degradations over long operation time. The presented gate 254 driver is also promising to be implemented using oxide TFTs, 255 then driving ability of the integrated gate driver can be further 256 improved for high-resolution and high frame-rate displays.

258
A TFT integrated gate driver using voltage bootstrapped car-259 rying signal (C N ) was demonstrated to increase the driving 260 ability for wilder operating temperature. Operating princi-261 ples of the proposed gate driver were detailed. Transient 262 VOLUME 10, 2022 time were measured using cascaded gate driver samples,