Solar PV-Fed Multilevel Inverter With Series Compensator for Power Quality Improvement in Grid-Connected Systems

Power quality difﬁculties arise as a result of Renewable Energy Sources (RES) integrating with the grid. Voltage swell, sag, and harmonic distortion occur on the grid due to power quality issues, which have an impact on customers. An inexpensive series compensator, like the Dynamic Voltage Restorer (DVR), is the best solution for overcoming the aforementioned problems. In this article, a solar PV integrated DVR with a novel multilevel inverter is introduced to address the power quality issues in the grid. The main objective of the proposed work is to develop a DVR integrated with a 23-level multilevel inverter to enhance the power quality. In addition, an improved INC-MPPT technique is designed for the boost converter for maximum energy extraction from the solar PV modules. Despite numerous beneﬁts of multilevel inverters, there exist several reliability challenges such as fewer component counts and reduced THD. The suggested topology can able to generate 23 levels of output voltage with asymmetrical DC sources. The MLI has several advantages such as a reduction in the overall component count, cost and size of the inverter. Additionally, a detailed mathematical analysis is presented for the rotating dq reference frame control. The dynamic performance of the DVR is evaluated with a balanced load and implemented experimentally. Simulation results of the proposed system are carried out using MATLAB/Simulink. The proposed system is implemented using a dSPACE controller with a laboratory hardware prototype and OPAL-RT real-time simulator setup as well. The results show that the design of the proposed system is more effective at compensating for voltage sag and improves the power quality signiﬁcantly. The THD obtained at the grid side is lower, which is under IEEE standards

In the smart era, microprocessor-controlled devices, or digital, electronic, and non-linear devices, are extensively used in all sectors of the industry. Nearly all of these devices are sensitive to electrical supply disruptions at any minute and cannot be operated properly. Problems that happen because of inadequate power quality are data errors, automatic resets, memory loss, UPS alarms, equipment failure, software corruption, circuit board failure, power supply problems, and overheating of electrical distribution systems. Considering these realities, PQ has become progressively more critical [1]. The use of sensitive loads such as diagnostic apparatus in health centers, educational institutions, detention centers, etc. over several years has been fourfold, which has led to a concern with the quality of power of sensitive loads [2]. The essential power quality issues include voltage swells, sags, harmonics, transients, flickers, fluctuations, and interruptions [3]. The sensitive and critical loads must prevent these issues in terms of power quality and voltage disturbances. In this regard, a wide range of solutions has been introduced, including the best and most efficient solution for the compensation and mitigation of voltage disturbances known as Custom Power Devices (CPDs). The DVR is the best CPD since it has low cost, is small in size, and can respond quickly to voltage disturbances [4], [5].
In grid-connected networks, dynamic voltage restorers (DVR) play a significant role in minimizing voltage disruptions. The grid voltage changes are controlled in grid systems by an energy-efficient photovoltaic (PV)-based DVR with a proportional controller and a new boost converter [6]. Renewable energy sources, as well as DC-DC converters in various topologies accessible today, are very essential for energizing electronics [7]. PV integration helps to generate clean, renewable energy while also lowering pollution levels. It can support important loads in the event of a grid outage, boosting reliability while simultaneously addressing energy issues. Furthermore, integrating PV and DVR while fulfilling energy demands reduces harmonics, voltage dips, and improves power factor. In many industrial applications, MLIs have found their extensive influence such as UPFC, drives with high power and medium voltage, DSTATCOM, electric vehicles (EV), active power filters, DVR, micro-grid, grid integrated or stand-alone PV systems, and other fields [8]. Half-bridge inverter [9] and H-Bridge (full-Bridge) inverter [10] are familiar inverter topologies in single-phase DVR. Besides that numerous multilevel inverters, matrix converters, and Impedance-fed inverters [11] are used for both single and three-phase DVRs. AC-AC converter-based DVRs [12] are used to enhance the power quality in the absence of a dc-link capacitor. However, during voltage sag AC-AC converters draw huge current from the grid. Thus, these are not suitable for long-duration voltage sag mitigation in weak grids. For deep voltage sag, Z-source converterbased DVR with less dc-link voltage was presented [13], though it needs storage as well as a risk of shoot-through. Typical three-phase DVR inverter topologies include the fullbridge, four-leg six-switch, and six-switch split capacitor configurations.
However for higher power voltage source inverters with two-level are not suitable because the switches will block large voltage, and more dv/dt creates electromagnetic interference to overcome these problems multilevel inverter (MLI) is the best solution. The benefits of MLIs are lower output voltage step, high power quality, fewer switching losses, minimum harmonics, and better electromagnetic compatibility. Capacitor voltage balancing is difficult when the voltage level increases in the case of diode-clamped MLI, hence these are restricted to three levels. Even though most of the industries are used three-level NPC Inverter. Flying Capacitor MLI requires more dc capacitors for higher voltage levels. However, there is flexibility to set the switching combinations and feasible for DC capacitor voltage balance [14]. Due to its modularity characteristic, CHB MLI topology becomes more reliable and popular. However, each bridge needs an isolated DC source and for higher levels, the requirement for switches also increases [15]. Hybrid topologies, most of which are developed from conventional topologies, have been proposed by researchers as a cost-effective means of addressing power quality issues and achieving high grid code standards [8]. Analysis and comparison of the 49level modular asymmetrical 49-level inverter were proposed in [16].
The authors in [17] Presented a new DVR topology based on a buck-boost ac/ac converter. It contains an inductor, capacitor, and five switches, and the most prominent characteristic of the topology is the lack of an injection transformer, which allows for a direct connection to the grid without the use of storage devices. As a result, this topology has less physical volume, mass, and cost than traditional topologies. A DVR with a cascaded H-Bridge multilevel converter [15] was connected directly to the MV network without the use of an injection transformer. The voltage restoration is achieved by the capacitors as energy storage using the zero active power compensation technique.
DVR with five-level reduced power components TCHB inverter [18] was used to mitigate the voltage sag using two voltage compensation schemes. In [19] proposed an S4L inverter-based DVR with a single DC power source and reduced switch count, thus it is cost-effective, furthermore, it generates seven levels, which significantly supports in reduction of the system harmonic problem. Interline DVR with CHB multilevel inverter was proposed in [20] to mitigate the voltage sag with better THD. An adjustable dc-link connected MLI-based DVR [21] is suitable for compensation of both long and short period sag. DVR with an openend winding transformer having reduced inverter loss and lower harmonics was proposed in [22]. Cascaded OEW transformer-based DVR was reported in [23] with better voltage levels, and reduced THD even though it does not require extra clamping diodes. T-type MLI-based DVR was proposed for medium and high-power applications [24]. A new asymmetrical multilevel inverter that combines an E-type clamped X-type DVR with a reliable fractional-order super-twisting sliding mode control was proposed. In [25] for a definite voltage level, these topologies require a high number of switches thus, the required driver circuits, size, and cost are increased. It was suggested in [26] to use an ''odd-nary'' cascading asymmetric multi-level inverter, which produces staircase output at higher levels while using fewer switches. To compensate for any voltage disturbances, a novel HCMLI coupled to a photovoltaic power source is proposed as an AC-voltage synthesizer for DVR [27]. A selective harmonic feedback control strategy was proposed in [28] and is implemented in MV DVR to provide voltage harmonic compensation without affecting sag compensation. H infinity voltage controller-based DVR proposed in [29] is effectively compensated the voltage sags in MV applications.
In this work, asymmetrical 23-level MLI is proposed to overcome all the limitations. The recommended 23-level MLI is implemented in a PV-fed DVR using a rotating dq reference frame controller. From the comparative analysis, the recommended 23-level MLI requires less component count factor and is cost-effective. The proposed PV-fed MLI-DVR efficiently minimizes the voltage sags, and swells and improves the power quality. The following are the most crucial features of the proposed topology: • The recommended 23-level MLI uses only three DC sources and twelve switches among them seven are unidirectional switches and five bidirectional switches.
• Most switches have reduced voltage stress, allowing them to operate at medium voltages.
• The proposed PV-fed MLI-DVR efficiently minimizes the voltage sags, and swells and improves the power quality.
• The proposed PV-fed MLI-DVR harmonic profile is superior to traditional VSIDVR, and under the IEEE standard. The remainder of the article is prepared accordingly. Section 2 describes the proposed solar PV integrated MLI-DVR. Section 3 describes the functioning and control of a PV-fed MLI-DVR. The proposed solar PV-fed MLI-DVR results were reported in Section 4 and the conclusions were made in Section 5.

II. SOLAR PV FED MLI-DVR CONFIGURATION
The system is configured using a 3-phase, 3-wire DVR, solar PV, a boost converter, and a load as shown in Figure. 1. DVR is the primary part, made up of a voltage source MLI, a DC link capacitor, an LC filter, and a coupling transformer. The solar PV system is the second part, which includes a PV array, an MPPT controller, and a boost converter.
The equivalent circuit of DVR is obtained by connecting a voltage source (V Comp ) in between source (V S ) and load (V L ) with their respective impedances, Z S and Z L , as shown in Figure 2. At the PCC source, current I S is divided into I L and I OT . Where I L is sensitive load current and I OT is another load current. The voltage at PCC is represented by V G and the voltage compensated by DVR is V DVR . Resistance R and inductance L are obtained from the impedance Z of the filter and injection transformer, the values of R DVR and X DVR are related to V DVR . The impedance of the source, load, and DVR are Z S , Z L , and Z DVR respectively. P S is real power and Q S is reactive power of supply. P L is real power and Q L is the reactive power of the load. P DVR is real power and Q DVR is reactive power supplied by the DVR.
The voltage across sensitive load V L is given by For higher power applications, voltage source inverters with two-level are not suitable because the switches will block large voltage, more dv/dt creates electromagnetic interference, and hence recently MLIs are used in DVR configuration. The article proposed a 23-level multilevel inverter supplied by a solar PV array.

A. PROPOSED 23-LEVEL INVERTER
The proposed configuration comprises three dc sources namely V a , V b , and V c , and seven unidirectional switches and five bidirectional switches. Four bidirectional switches are connected in a crisscross structure [30] as depicted in Figure 3. For asymmetric operation, the magnitudes of DC voltage sources are fixed as The required DC sources N DC in terms of levels N Lev is given by: The number of switches N SW required in terms of levels N Lev is given by:  The suggested topology uses unidirectional power switches for all of the switches. As a result, the required gate driver circuits N GDK equals the number of N SW , and is written as V L,max is the maximum voltage output and is given by The proposed configuration produces an output voltage of 23 levels with magnitudes of zero, positive (+V dc to +11 V dc ), and negative (−V dc to −11V dc ). Total maximum blocking voltage is one of the most important qualitative characteristics, which is referred to as the algebraic sum of the maximum voltage stress on each switch. MBV of particular switches are calculated as follows: The term TSV is stated as the algebraic sum of MBV across individual switches and is expressed in equation 7, equation 8 provides the TSV PU .
For the proposed topology TSV Prop is calculated as   As a consequence, the recommended MLI topology optimizes the utilization of DC sources with minimum TSV and switches, hence the volume and price will be reduced. TABLE 2 shows the current path to the load, as well as the maximum blocking voltage (MBV) and the voltage stress on the switches. It has been found that some operating voltage levels include redundant switches.
A comparison is made between the recommended topology and other recent topologies to evaluate the benefits and capabilities of the recommended 23-level MLI topology. Table 3 shows a comparison of the required driver circuits, DC sources, switches, component count factor (CCF), the maximum number of conducting devices per level, TSV PU , and the cost factor [31] for each level.   solar PV is shown in Figure 4. D is the diode and R P , R S are the resistances of parallel n p and series n s connected cells, respectively.
From an ideal PV circuit, the diode current is where γ is the ideality constant, saturation current is I o and thermal voltage V T = ( kT c q ) is depends on the charge of electron q, cell temperature T c , and Boltzmann's constant k.
Output power P PV = V PV * I PV (12) Output current is Short circuit current I S The values of coefficient of temperature β, reference temperature T R , and corresponding short circuit current I S(TR) are provided in PV datasheets.  Considering the intensity of irradiance then G n is the normal value of irradiation Saturation current I 0 is calculated at I PV = 0, then I 0 at T R is given by The fundamental problem of employing renewable energy sources to generate electricity is low voltage output.
To enhance the voltage level, the RES output is sent to a DC-DC boost converter. The boost converter output voltage is regulated by the duty cycle of the control switch. Hence, by adjusting the switch-ON time, one can alter the output voltage. The formula used to calculate the average output voltage over the duty cycle 'α' is The value of inductor and capacitors are calculated using The input current and output voltage ripple factors are I L and V dc , respectively, and the switching frequency is f s . For a realistic estimation of inductor and capacitor values, I L should be restricted to 30%, and V dc is commonly assumed at 5%.   Figure 5 shows a single-input multi-output (SIMO) circuit that receives the output of the DC-DC boost converter [38]. Boost converter output is fed into the primary winding of a transformer and secondary of multi winding transformer gives three output ports with tur's ratio of 11:1:3:7. At the output terminal of each DC-DC converter output port, a diode and a capacitor are connected. The diode is positioned to prevent the capacitor's reverse current from flowing into the transformer windings. The operation of the boost converter is regulated by the MPPT controller depending on inputs such as environmental parameters (solar radiation and temperature), PV array parameters (V oc and I sc ), and outputs like DC link voltage. The operational performance of traditional incremental and conductance MPPT algorithms is lower if the operating point is fluctuating around the MPP and under rapidly changing irradiance conditions. To address these issues, an enhanced INC MPPT is employed [39]. The circuit diagram of the PV-fed MLI-DVR connected to the grid is shown in Figure 6.

III. OPERATION AND CONTROL OF PV-FED MLI-DVR
Depending on the type of load and voltage sag, the DVR compensating technique differs. This is because only a few loads respond to fluctuations in voltage magnitude, while others are sensitive to deviations in phase angle, and still, others are sensitive to both. As a result, the load characteristics dictate which control approach to employ. The pre-sag compensation (PSC) method is used to compensate for both the magnitude and phase angle of the voltage sag [40].
In this strategy load voltage is maintained with the pre-sag voltage, therefore no voltage disturbance is sensed by the load because the load voltage is having the same magnitude and phase angle, hence it is also known as the voltage quality optimized technique. The vector representation of PSC is shown in Figure. 7. During sag, the DVR is controlled by adding more real power, which affects the rating of direct energy storage or energy received from the grid hence the requirement of energy source to supply active power will increase apart from reactive power injected by the inverter. It is acceptable for both balanced and unbalanced sensitive loads heaving phase jump or not.
where V DVR is the DVR injected voltage, is the phase angle between V L and I L , V Sag G is the grid voltage at sag, δ is the corresponding angle of phase jump to V Sag G , p is the corresponding phase of the supply voltage (R, Y, or B).

A. CONTROL SCHEME OF THE DVR
A voltage disturbance duration (both start and end), phase jump, and depth depend on the type of voltage disturbance. Various methods for sensing voltage disturbances are presented in [41]. The Park transformation is utilized to transform the three-phase load voltages V L RYB and reference voltages V ref, RYB into vectorized dq0 voltage components V L,dq0 , and V ref,dq0 . The following formula is used to compute the three-phase reference voltage: Then, using the Park transformation, it is changed from RYB to dq0 components (24), as shown at the bottom of the next page.
Once the load and reference voltages change into the dq0 frame, the error signal e r will be obtained in terms of magnitude and phase shift of voltage, as shown in figure 8b.
The change in the dq0 components will result from variations in magnitude and phase shift of voltage. Changes in the  state of the supply are detected and responded to swiftly by the suggested control. In this work, the synchronous reference frame the phase-locked loop (PLL) is used as a synchronization method. It maintains frequency and phase synchronization between the controller output signal and a reference input signal. The DVR control presented in this article is a PI controller driven by an error signal, resulting in a low level of cos ωt − 120 0 cos ωt + 120 0 −sin(ωt) −sin ωt − 120 0 −sin ωt + 120 0 0.5 0.5 0.5   complexity. The controller function is to reduce the error signal on the distribution grid as much as possible. In the time domain, the contribution signal of the PWM in dq0 frame for the PI controller is Vp, given as Finally, the output of PI control is fed back into abc frame to regulate the PWM that generates the VSI gating pulses, given as  cos ωt − 120 0 1 sin ωt + 120 0 cos ωt + 120 0 1 According to Equation (25), the error signals er of dq voltages are given to the PI controller, as The error e rd signal is fed into the D-axis of the PI controller, whereas the error e rq is fed into the Q-axis of the PI controller, as shown in Figure 8. The signal provided to the controller is the change in voltage between V ref and V d . The error equation is given as 81212 VOLUME 10, 2022   Figure 8 represents the control strategy of the proposed MLI-based DVR. A rotating dq reference frame controller is used to generate the reference signal shown in Figure 8b. The error signal and error rate drives the PI controller, it analyzes the input and produces controller output. The controller output is given as a reference voltage to the PWM. The pulses generated by the PWM pulse generator control the operation of the multilevel inverter. The systematic procedure of the control system is presented in Figure 8a. The magnitude and phase angle of the reference voltage is produced by using the pre-sag compensation technique and injected through the multilevel inverter. This information is computed by using the synchronous reference frame Phase-Locked Loops (PLL). The parameters of PI controller are obtained as K pd = 7.401, K id = 189.014 in case of D-axis, K pq = 69.31, K iq = 192.412 in case of Q-axis.

B. PULSE WIDTH MODULATION
The nearest level control (NLC) or round method [20] is a low switching frequency control technique used to generate the nearest voltage level by converting it to the desired reference output voltage. Using the switching table, the closest level of voltage to the reference voltage is chosen by selecting the switching combination that corresponds to that level as depicted in Figure 9. The nearest output voltage level for voltage reference V ref and the modulation index 'm' is The limits of the reference voltage and active switches of the selected voltage level of the NLC technique are represented in Table 5. The switching angles are calculated from equation (34) and tabulated in Table 5 θ The dq control structure in this technique comprises of two PI controllers, but using and adjusting a single PID controller simplifies the implementation, however tracking of non-DC values using PID controllers is inaccurate. In this method, it is necessary to calculate the real and imaginary components of the output, which adds to the computing burden, even though it can only compute a finite number of points in a frequency spectrum. In order to make computations as simple, the rotating dq reference frame approach is employed in this work. The dq control structure in this technique comprises of two PI controllers because of their efficient reaction for regulating the DC characteristics. It allows the system to independently control the reactive (Q-axis) and active (D-axis) components. Because a PI controller has infinite DC gain and only requires two PI controller structures in the D and Q axis, this technique can achieve zero steady-state  error. The mutual inductance is also constant in the dq-frame.
Since the inductance dependent variables are constant, hence it allows the system to obtain the desired output.

A. SIMULATION RESULTS
The proposed multilevel inverter solar PV fed DVR is evaluated in terms of improving voltage profile. The results are shown using the MATLAB/Simulink platform. Table 7 lists the parameters of DVR. The DVR is connected to the system through a 10 KVA, 400V (1:1) injection transformer.
The output voltage of a PV array are increased to 400V with a boost converter. To keep the DC link voltage constant, a 500Ah battery with a 400V normal voltage is used and an 8 kW, 0.85 lagging PF linear load (RL Load) is considered. The simulation results of PV and boost converter with EINC MPPT are shown in Figure. 10. PV at MPP generates 112.8 volts and by using a boost converter it is boosted to 400 volts which are appeared at the DC link. Figure 11 represents the R phase voltage waveform of an asymmetrical 23-level MLI. Voltage sag mode is created by applying overload at time intervals ranging from 0.2 sec to 0.285 sec.
In this test, 0.5pu of sag is applied in comparison to load point reference voltage. The proposed DVR injects the appropriate voltage and maintains the load voltage profile, and is shown in Figure 12 and Figure 14. Figure 12 represents the voltage profile of DVR at 0.5pu of sag condition only in one phase, whereas Figure 14 shows a three-phase voltage profile of DVR. Figure 13 depicts the voltage THD at the load side with DVR in sag mode. A double voltage sag mode is created by applying overload at time intervals ranging from 0.2 sec to 0.285 sec with 0.7pu and from 0.315 sec to 0.385 sec with 0.5pu of sag is applied in comparison to load point reference voltage. The proposed DVR injects the appropriate voltages and maintains the load voltage profile, as shown in Figure 15. In this test, a swell mode is created at time intervals from 0.3 sec to 0.365 sec. 1.2 pu of swell is applied in comparison to load point reference voltage. The proposed DVR compensates for the appropriate voltage and maintains the load voltage profile, and is shown in Figure 16.

B. EXPERIMENTAL RESULTS
The suggested topology of 23-level MLI is tested using a single-phase prototype built in the lab. A dual dc supply supplies the input dc sources and a 100-ohm resistive load is used. The prototype consists of 12 IGBT switches that are activated by using optocouplers (MCT2E). The real-time controller dSPACE1104 is used to build the switching control system, and DSO is used to monitor the voltage and current waveforms. The experimental setup is shown in Figure 17 and the findings with a resistive load are shown in Figure 18, at steady-state output voltages of 400V (282.84 V rms ) and the load current of 4A (2.82 I rms ).

C. REAL-TIME ANALYSIS
For high-power applications, it is not feasible to test experimentally the simulation results achieved with MAT-LAB/Simulink. To verify their accuracy hardware in-loop testing (HIL) was developed. This platform scales down testing time, cost and also provides test features in any situation and enables test system change. The setup of the  HIL simulator is shown in Figure 19. It consists of an Opal-RT OP5600 simulator, as well as a host computer and a digital storage oscilloscope. It is entirely digital, supported by an FPGA processor, a real-time simulator that runs Simulink in real-time using a fixed-step solver. For viewing and editing the block diagram graphical model in the frontend, it uses MATLAB/Simulink, from which real-time simulation code is generated, updated, and downloaded.    Figure 20 illustrates the performance of an EINC MPPT controlled boost converter using OPAL-RT and Figure 21 shows the output of PV fed MLI-DVR at 0.5pu sag condition of one phase, which includes source voltage, compensation voltage, and load voltage information. Figure 22 shows the output voltage profile of PV fed MLI-DVR at 0.5pu sag condition, which includes source voltage, compensation voltage, and load voltage information.  The THD of the proposed PV-fed DVR is reduced from 17.09 percent (without DVR) to 1.28 percent (with MLI-DVR) at sag condition and is represented in Figure 24. The proposed DVR architectures are compared with existing MLI DVR architectures in terms of switches required, output  voltage levels and THD and are tabulated in Table 8. From Table 8 it is found that the proposed topology requires only  12 switches per phase to produce 23 levels and the required switches per level is less as compared to other topologies and the THD of the proposed topology is considerably less compared to other topologies. Figure 25 represents the comparison of the required number of switches per phase to produce expected levels in the output voltage waveform from this the proposed MLI-DVR topology produces higher voltage levels with reduced switches hence the sag voltage is effectively compensated by implementing this topology with lesser THD.

V. CONCLUSION
A PV-fed MLI-DVR using a rotating dq reference frame controller with an asymmetrical 23-level MLI is proposed in this article. A novel multilevel inverter is designed and implemented experimentally with a laboratory prototype. A synthesized output voltage of the proposed MLI is obtained with a low THD utilizing fewer circuit components. There exits various outstanding features of the proposed MLI such as the TSV PU is 2.4 whereas the cost function (CF/L) values for 'α' are 1.07 and 1.15 respectively, therefore the proposed MLI is cost-effective and superior than the existing topologies. The results of the proposed PV-fed MLI-DVR are verified with the OPAL-RT real time simulator testing platform. The proposed system efficiently minimizes the voltage sag and preserves the DC link voltage to be stable.
The maximum power can be extracted from the PV modules using INC MPPT technique. A detailed comparison of the proposed MLI-DVR is presented with the existing topologies and it is found that the proposed system performs efficiently during the compensation of voltage sag. A lower THD of 1.28% is obtained in the process of compensation of voltage at the grid and satisfies the IEEE standards. The proposed system is significantly performs well henceforth it can be further implemented in HVDC and FACTS devices.