A Pencil Shaped 9-Level Multilevel Inverter With Voltage Boosting Ability: Configuration and Experimental Investigation

A comprehensive study of a minimized component pencil shaped (PS) 9-level inverter constructed with just two DC supplies is presented in this research. Many of the suggested low component multilevel inverters (MLIs) use DC supplies that are not being used appropriately along with additional conducting switches. Since this proposed MLI has a reduced quantity of power electronic switches, it is more efficient. The architecture may be expanded to a modular higher voltage level inverter, which uses less DC supplies and uses them correctly without the need of an extra H-bridge circuit. To determine their optimum capabilities, the proposed inverter parameters’ simplified formulas are constructed. Furthermore, the extended model of the proposed architecture is used to generate an optimum PSMLI design for lowering the total standing voltage (TSV) of the inverter. To demonstrate its advantages over recent MLIs of similar types, comparison studies are given to justify the proposed inverter. Through proper simulation and laboratory experiment, the MLI obtained a higher efficiency of 95.54%. On the other hand, the optimized 17-level version of PSMLI obtained total harmonic distortions (THD) of only 5.15% which successfully attained IEEE 519 standard performance.


I. INTRODUCTION
Multilevel inverters offer a consistent and precise output voltage. In the realm of power electronics, researchers find MLIs that have different shapes to be very interesting. Recently, a large diversity of configurations has developed in power systems, with variety of applications. In medium and high-power systems, including power grid, electrical vehicles [1], drive systems [2], active power filters [3], [4], The associate editor coordinating the review of this manuscript and approving it for publication was Ton Duc Do .
wind turbines [5], solar systems [6], and HVDC for transmission lines [7], MLIs are the preferred inverter above standard two-level inverters. Since MLIs generate multilayer voltage, they feature minimal harmonic profile and ripplefree output voltage. The cascade connection capabilities of MLIs confirms that the switches have minimal stress and electromagnetic interference, resulting in high efficacy for the system.
Multilevel inverters come in a variety of modules, for instance, Neutral Point Clamped (NPC), Flying Capacitor (FC), and Cascade H-bridge (CHB). Large capacitor voltage dips are observed in FC and NPC, resulting in imbalanced DC links and high voltage stress on the switches. CHB topologies, on the other hand, are suggested by researchers as a way to design configurations with fewer components. The fundamental disadvantage of typical CHB-MLIs is that they need a large number of separate DC sources and conductor switches to generate multilevel voltage. According to [8], MLIs can be divided into three different types depending on the structure and the magnitude of the DC supplies: which are asymmetrical, symmetrical, and hybrid MLIs. In the unipolar MLI topologies proposed in [9]- [12], H-bridge circuits with polarity generating capacity are necessary to acquire negative and positive voltage levels at the output provided by the level generating (LG) section. Although the LG section generated voltage become approximately double by the H-bridge, the power electronic switches of the H-bridge need to endure the highest voltage stress equivalent to the total DC-link voltage [13]. Switched-battery boost (SBB) MLI as reported in [14] reduces the switch count by using two DC supplies with one diode and a switch to generate just two voltage levels. However, to generate higher voltages, this MLI needs a greater number of DC supplies, and the levels can only be attained by combining the multiple sources. As an alternative, crisscross switched based inverters are proposed to generate greater voltage with fewer components The MLI using crisscross switched configuration as shown in [15] included the semi-half-bridge cell that employed a moderate number of DC sources and semiconductor switches to achieve a certain voltage level. Although these MLIs employ minimal DC sources, an extra H-bridge circuit is utilized that has high voltage stress and therefore, raised their total standing voltage (TSV).
Bipolar configurations are more appealing because of their intrinsic ability to create negative voltage stages without H-bridge circuit, which helps to reduce high TSV. A square shaped MLI module was proposed in [16] utilizing 4 DC sources and 12 switches to produce 17 voltage levels. Even though the MLI's structure has been established utilizing low rated switches, it uses asymmetrical DC sources. Thus, the TSV of this MLI is very high. Because of using 4 DC sources, it will require 4 transformers to provide galvanic isolation, that may increase the overall cost of the system significantly. Moreover, because of using asymmetric DC sources, it needs precise voltage balancing to maintain the constant voltage ratio among the DC sources which can induce control complexity. In comparison, the proposed MLI only used 2 symmetric DC sources and 10 switches to produce 9-level voltage. Thus, it has overcome all the issues associated with the MLI of [16]. A similar envelope type (E-type) topology can be observed in [17] where 10 switches and again 4 asymmetrical DC sources are used to generate 13-level. This topology has similar issues like the MLI in [16]. The configuration is redesigned by putting two capacitors in place of two DC supplies in the kite shaped MLI [18]. This MLI can produce 13-level voltage utilizing 2 more switches than the proposed MLI. However, it again utilized asymmetrical DC sources which has increased its TSV and induced voltage balancing issues. In [19], an inverter with 5 symmetric DC supplies and bidirectional switches is presented that couples two generic T-type inverter sub-modules with 4 cross connected switches and 4 DC supplies. Although this configuration solved the issue of asymmetrical DC sources of previous configurations, it still requires higher number of DC supplies. Additionally, this device has comparatively high TSV than the proposed MLI because of using the cross connected switches which bear the entire voltage stress of each T-type sub module. Ref [20], [21] present another two symmetrical configuration that makes extensive use of DC sources while prohibiting the use of asymmetric DC supplies. However, the cost of these devices is elevated because of using high number of isolated DC sources.
By implementing switched capacitors instead of DC sources, a new group of MLIs known as switched capacitor MLI (SCMLI) aims to reduce the number of components while also lowering the switching stress. This particular MLI group uses a blend of DC supplies and capacitors to produce sinusoidal voltage. Furthermore, higher voltage steps or voltage boosting can be obtained using the same DC sources. According to [22]- [27], SCMLI designs aim to substitute several DC supplies with capacitors. However, the increased number of switching devices are required in these MLIs to maintain capacitor voltages complicating the circuit configuration.
The study presented a novel MLI module using a clever combination of DC source, capacitors and switches. With the goal of achieving maximum voltage steps, switching devices and DC sources are implemented with enhanced power quality and cost-effectiveness in mind. Using only 2 switched capacitors and 2 DC supplies, this module can generate 9 levels output. To synthesize negative output levels, the suggested module doesn't need any extra circuit. As a result, the TSV of the MLI is greatly reduced.
The principal contributions of the manuscript can be stated as follows: 1. Thus, it has further optimized and simplified the structure making it cost effective. The entire structure of manuscript is organized by dividing it into seven major sections. Section 2 discusses the state of the art, features, modularity, TSV, efficiency and power losses of PSMLI. The third section demonstrates the optimized structure of PSMLI and its advantages. Following that the next section presents a comprehensive comparative analysis with other MLIs. Section 5 presents results and discussions which includes simulation and experimental results. Finally, section 6 discusses the conclusions of the manuscript.

II. PSMLI AND ITS CONFIGURATION
The proposed module is built using a proper configuration of power electronic components to achieve maximum number of voltage levels using the DC sources and switched capacitors.
This topology uses the basic operation of switched capacitors to further increase and boost the voltage levels. Another challenge in this type of MLI would be to maintain the voltage of the capacitors without needing any additional circuit.

A. CONFIGURATION AND WORKING PRINCIPLE OF PSMLI
The pencil shaped MLI (PSMLI) is build following the edifice of a pencil as depicted in Fig. 1. It has 3 principal segments which are represented using 3 color schemes. The first part is called the head (brown color), the 2 nd segment is referred as the body (yellow color) and eraser is the final part (pink color).
The first section includes 2 unidirectional switches (S 1 , S 2 ,). These serve as directional switches and the module's current path is determined by them. PSMLI, for example, will only produce positive voltage levels, if S 1 is switched on. However, when S 2 is turned on, it can typically generate negative voltage levels. The body part consists of 4 unidirectional switches (S 3 , S 4 , S 6 , S 7 ) and 1 bidirectional switch (S 5 ), 2 DC source (V DC1 , V DC2 ) and 2 switched capacitors (V C1 , V C2 ). The switches S 3 and S 7 is utilized to avoid the short-circuit of capacitor V C1 and V C2 . The body part performs as the channel between the head and the eraser. The reverse current is blocked by the bidirectional switch S 5 . The bottom part of PSMLI is an eraser shaped part that consists of 2 unidirectional switches (S 8 , S 10 ) and 1 bidirectional switch (S 9 ). It structurally looks like a T-type inverter and thus can generate negative levels without needing additional H-bridge unit. The MLI can produce  9 levels voltage (±4 levels, and 0 level) using the DC-links. PSMLI's power switches are cleverly implemented so that the capacitors and DC supplies are coupled through different current channels, requiring no additional circuit to balance out the voltage of the capacitors. Table 1 shows the switching pattern while Fig. 2 illustrates the current routes of PSMLI. In addition, Fig. 3 shows the  behave of the power switching components of the proposed PSMLI using the nearest level control (NLC) technique. It can be observed that zero voltage level is used to charge the DC capacitors. Table 1 also shows the number of times each switch turns on during one complete cycle of operation. The switching sequences of Table 1 confirm that switches (S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 10 ) are turning with low frequency which has significantly reduced the TSV of the PSMLI. For each voltage level of PSMLI, a graphical depiction of the TSV of each switch for every voltage level is presented in Fig. 4. Thus, the TSV of the PSMLI is calculated to be 16 V DC .

B. BMODULARITY OF SYMMETRIC MODULE
The proposed PSMLI's flexibility is verified in this section by showcasing its ability to generate higher number of voltage levels. This is done by extending the structure of the 9-level PSMLI inverter which is depicted in Fig. 5. Here, the ratio between the DC sources and the capacitors is unity. The extended structure is developed by extending the body part of PSMLI and which is then connected with another similar structure using cascaded connection as depicted in Fig. 5. The polarity is converted using 2 conduit switches which are placed between the main body and extended body of the PSMLI. These 2 switches will also function as the polarity converter similar to the directional switches used in the head section of the PSMLI. The cascaded connection is established with z th module to double the voltage producing ability. The x th sub-modules incorporate 6 unidirectional switches, 1 bidirectional switch, 2 switched capacitors, and 2 DC sources. For a specific number of x th module and z th module, the number of voltage sources (N DC ), number of capacitors (N C ), number of power switches (N P ), and the voltage levels (N V ), TSV (N TSV ) can be determined as: Considering Fig. 5 and at constant z, for a specific number of DC sources, the other parameters of PSMLI can be determined as: Since power switches of the symmetrical cascaded z th module have same TSV as the original module (n = 1), the TSV can be realized by: Considering a constant number of cascaded modules, the voltage stress of the switches of the symmetrical submodules can be determined by:

C. MODULARITY OF ASYMMETRIC MODULE
Although asymmetrical MLI structures induces superfluous voltage stress and imbalance into the system, it is one of the simplest methods of boosting voltage levels without introducing any structural complexity or usage of higher number of power electric components. The proposed PSMLI can also be extended using asymmetrical module. In order to maximize the voltage level, the second submodule or of the PSMLI is designed with voltage sources with tertiary voltage capability (i.e.,  (2) and (6). However, the TSV of the entire PSMLI would increase to 69V DC . The relation between the voltage levels and voltage stress are shown in Fig. 6 for further comprehension. Similar to the symmetrical extension of PSMLI, the equations for the asymmetrical extension can be realized by: Considering a constant number of cascaded modules, the voltage stress of the switches of the asymmetrical submodules can be determined by:

D. EFFICIENCY AND LOSS PROFILE OF PSMLI
The suggested MLI configuration's efficiency and power loss are assessed using the PLECS software. The power loss evaluation on all heat sinks is done in the steady-state condition maintaining an ambient temperature of 25 • C. Heat is distributed evenly across the heat sinks. By using the data sheets, thermal profiles of diodes and IGBTs are computed automatically by PLECS software. The power loss of the PSMLI is predicted to be 900W under nominal working conditions. The efficiency is calculated by taking into account the conduction and switching losses of switching devices, as well as the power losses of switched capacitors. The capacitor generated losses are calculated as follows: The resistive and dielectric losses are represented by P R and P D , respectively. Furthermore, the maximum DC voltage of a capacitor is denoted by µ DC , f represents the fundamental frequency, which is 50 Hz, C symbolizes the capacitance, dissipation factor is depicted by tan δ 0 that is 0.15. Utilizing (18) -(20), the capacitor losses are 11.8 W. The diodes' switching and conduction losses at steady state are 0.012 W and 0.871 W, respectively, while the total IGBTs' switching, and conduction losses are 0.193 W and 9.187 W. The overall efficiency is 94.5%, with a total power loss of 22.063 W.

E. VOLTAGE RIPPLE CALCULATION OF PSMLI
For a high-quality AC output, a constant total DC-link voltage is necessary. In order to avoid a significant amount of voltage ripple, a switchable capacitor must have a voltage ripple of no more than 5%. The following calculation can be used to calculate the voltage ripples of both capacitors: Using PSMLI's basic output current, this may be figured out further as follows: Here, ϕ indicates the angular shift between voltage and current, ω indicates the angular frequency of the multilevel AC voltage, ripple voltage end angle is indicated by θ off , ripple voltage starting angle is indicated by θ on , capacitance of capacitors is indicated by C. Using the following equations, the ripple angle can be calculated as: where, the quality factor is indicated by Q and modulation index is indicated by m. The capacitor voltage ripple level is indicated by N VR . Both capacitors' voltage ripples are computed, and the computed value is 3.23 V. This determines that low ripples exist in the capacitor voltage, and the proposed MLI can be implemented effectively.

III. OPTIMIZED PSMLI TOPOLOGY
By choosing an optimum structure for each module, the TSV of the extended symmetrical PSMLI can be reduced. Here, the asymmetric PSMLI is not considered because of drawbacks associated with those modules such as high TSV and voltage imbalance which can cause serious problems specially in renewable energy applications. A specific combination of x (submodules) and z (cascaded modules) must be chosen to develop the proposed PSMLI's extended structure having minimum voltage stress. This optimum configuration also ensures that a reduced number of power electric components are fully utilized. Thus, the voltage levels (N V ) and corresponding TSV for two alternative configurations of PSMLI under different values of x and z can be plotted to find the optimal configuration.
A. CONFIGURATION 1 The PSMLI can be designed with any number of cascaded or z th modules, each having one cross connected submodule (x = 1). Under this configuration with the number of voltage levels that can be produced by the proposed inverter is found using (3) which is 8z + 17. On the other hand, the TSV of the whole inverter can be determined by utilizing (4).

B. CONFIGURATION 2
The PSMLI can be designed with only cascaded module (z) and several submodules (x > 1) in this configuration. Under these circumstances (configuration-1 and configuration-2), the number of voltage levels (N V ) and TSV of the novel MLI can be again determined using (3) and (4) respectively. The graphical representation of N V vs TSV is illustrated Fig. 7. It is visible from Fig. 7 that in terms of TSV configuration-2 is more feasible than configuration-1. The higher THD of configuration-1 is due to the utilization of 4 extra switches while adding several cascaded modules. Thus, the overall cost of configuration-1 will be much higher than configuration-2 since switches with high voltage ratings are highly expensive [28]. However, in terms of simplicity and switching control, configuration-1 is preferable since it can be built with similar cascaded modules and same switching sequences. In terms of power switches, configuration-2 is more costeffective since it requires a smaller number of power switches for generating higher voltage levels. Configuration-2 can generate 81-level voltage utilizing 84 power switches while configuration-1 requires 112 power switches for generating same voltage level. Considering all these advantageous aspects, this manuscript gives more emphasis on configuration 2.

IV. COMPARATIVE ANALYSIS
In order to justify PSMLI's superiority in terms of usage of lesser number power electronic components, a comprehensive comparative analysis is presented in this section with classical and other recently proposed MLIs. For comparison, the symmetrical version is selected for each MLI. Configuration-2 of PSMLI is selected for this analysis since it is more optimized than configuration-1. The parameters that are chosen to conduct this comparison: number of DC sources (N DC ), number of power switches (N P ), number of voltage levels (N V ), maximum voltage (N Vmax ), TSV, boosting factor and requirement of H-bridge circuit. The generalized equations of the MLIs are shown in Table 2.
In comparison with the classical MLIs it can be observed that the proposed MLI has used low number of power switches. The classical NPC inverters require a smaller number of DC sources compared to PSMLI. However, it requires huge number of switches [refer to Fig. 8(a)], clamping diodes and capacitors to generate greater voltage levels. Thus, it has serious voltage imbalance issues which requires the application of complex modulation techniques VOLUME 10, 2022 to be resolved. FC MLIs also requires small number of DC sources but has the characteristics of using large number of capacitors and power switches as shown in Fig. 8(a) which can greatly hamper the efficiency of the MLI by inducing capacitor losses in the system. CHB MLI requires large number of switches and DC sources compare to the proposed MLI as illustrated in Fig. 8(a) and 8(b) respectively. Symmetric CCMLI [15] requires 14 switches and 5 DC sources to generate 9-level output which is more than the proposed MLI. In addition, the TSV of the CCMLI is 42V DC as shown in Fig. 8(c) which is substantially greater than PSMLI.
A similar attribute can be observed in the MLIs proposed in [16]- [20] where, large number of switches and DC sources are required compared to PSMLI. The proposed MLI in [17], [19] require same number of switches as PSMLI for the basic configuration (n = 1). However, as the voltage level increases, they require a greater number of DC sources and switches evidential from Fig. 7(c). On the other hand, the MLIs proposed in [16]- [20], [22]- [24], [27] avoided the use of H-bridge. However, they require high number of power switches.
The proposed MLI is also compared with similar class of switched capacitors MLIs (SCMLI) proposed in [22]- [27]. It can be observed from Fig. 8(b) that although these MLIs utilized a single DC source, they tend to have higher TSV [refer to Fig. 8(c)] and uses increased number of switching devices [refer to Fig. 8(a)] compared to the proposed MLI.
It is further noticeable that the boosting factor is only present for the MLIs that are comprised of switched capacitors units. This provides an added advantage to these MLIs since they do not require high number of isolated DC sources and transformers. The highest boosting factor is provided by the MLIs proposed in [24] and [26] as shown in Table 2. Both of these modules used single DC source to produce 9-level output at n = 1. On the contrary, the SCMLIs proposed in [22], [23], [25], and [27] have a triple boosting ability. Although, these MLIs have higher boosting ability than the proposed MLI, they have utilized high number of power switches and also induced high TSV which is evident from Fig. 8(a) and Fig. 8(c), respectively. Thus, it can be stated that the proposed PSMLI has created a balance among the utilization of power electronic components such as switch and DC sources, voltage boosting ability, and TSV.
PSMLI's superiority is further validated by comparing it with other MLIs in terms power losses and efficiencies. The power losses and efficiencies are obtained using PLECS software. The MLIs are built with similar model of power electronic switches, DC sources, diodes and capacitors to justify the comparison. Furthermore, a maximum DC-link voltage of 200 V is considered for the MLIs with an operating power of 900 W. The efficiencies (η) of each MLI are determined by considering three types of losses which are conduction losses (P con ), switching losses (P sw ) and capacitor losses (P cap ). The power loss data obtained from PLECS software is then added to determine the total power losses (P total ) of each MLI as demonstrated in Table 3. It can be observed from Table 3 that PSMLI's efficiency is less than the MLIs proposed in [16]- [20]. It is due to the fact that these MLIs does not incorporates any capacitors and hence, there is no capacitor loss. Nevertheless, all these MLIs use several DC sources which can massively increase their building costs. It should be addressed that the SCMLIs' efficiency is calculated for generating 7-level voltage. Yet, the proposed MLI has higher efficiency than all SCMLIs.

V. RESULTS AND DISCUSSIONS
The operation of the proposed PSMLI is validated in this section by presenting the simulation and experimental results. Similar parameter settings are selected for both simulation and experimental setup to justify and compare the results.

A. SIMULATION RESULTS
MATLAB Simulink is used to simulate the proposed PSMLI. The 9-levels (n = 1) output voltage of PSMLI is illustrated in Fig. 9(a) using the NLC modulation technique. Here, each voltage level is 10 V to create a 50 Hz multilevel staircase output voltage of 40 V. The harmonic spectrum of the 9-levels output voltage is depicted in Fig. 9(b). Furthermore, the 17-levels (n = 2) output voltage and   harmonic spectrum of the cascaded PSMLI are shown in Fig. 10(a) and Fig. 10(b) respectively. Having the same individual voltage level of 10 V, this cascaded module is able to generate 80 V output. It can be noticed that in terms of THD, the extended configuration performed much better than the basic configuration since it produced almost double amount of voltage level. Therefore, the THD of this module has effectively fulfilled the IEEE 519 standard. The   THD of 9-level PSMLI can be improved by implementing selective harmonic elimination (SHE) control where the switching angle of each power switch is individually optimized [28].

B. EXPERIMENTAL RESULTS
The parameters and the model of the components used to build the hardware model is shown in Table 4. The hardware setup is shown in Fig. 11 which include all the power components.
The experimental results of the 9-level (n = 1) and 17-level (n = 2) symmetrical PSMLI's voltage waveforms are presented in Fig. 12 and Fig. 13, subsequently along with VOLUME 10, 2022  the harmonic spectrums in Fig. 14(a) and Fig. 14(b). The results are obtained with a fundamental frequency of f = 50, modulation index m = 1, and inductive load of (40 -5 mH). It can be noticed that the basic configuration of PSMLI has synthesized 9-level voltage with a peak magnitude of 43.04 V. In contrast, the extended PSMLI has produced 17-level voltage with a magnitude of 81.16 V. In terms of THD the extended module performed better than the basic module since it produced higher voltage level. Thus, the THD of 17-level module has met the IEEE 519 2014 voltage harmonics standard (i.e., THD < 8%). Moreover, the voltage and current waveform of the asymmetrical 33-level PSMLI is shown in Fig. 15. It is clearly observable that the voltage waveform has become nearly identical to a pure sine wave. Thus, the THD in this case has further decreased to only 2.58% while the voltage has increased to 162.59 V. Finally, it can be seen from Fig. 16 that the capacitor voltages for both capacitors are balanced and stable while the prototype of the PSMLI module is operating at nominal condition. It further indicates that the hardware model of the proposed PSMLI is performing without any major issue.
The performance of the PSMLI is tested in 3 different transient conditions and results are shown in Fig. 17. In 1st case, the input DC voltage is altered from 10 V to 5 V. As a result, it is noticeable from Fig. 17(a) that the output voltage is decreased from 43.04 V to 20.22 V while the current decreased from 1.34 A to 0.65 A. Nevertheless, the MLI is  working without any issue. In 2nd case, the modulation index is varied from m = 1 → 0.5 → 0.3 and thus, the voltage is decreased from 9-level → 5-level → 3-level as shown in Fig. 17(b). Although, the MLI is performing properly the THD of the output voltage increased from 9.7% → 18.2% → 29.1% since the MLI's voltage level is reduced. In the 3rd and final case, the load is varied gradually from 100 to 160 . Thus, the current is gradually decreased as illustrated in Fig. 17(c).
The capacitor voltages of the PSMLI are also observed under the transient conditions mentioned above. It can be observed from Fig. 18(a) that during the voltage fluctuations the capacitor voltages are also reduced to 5 V as the total voltage become 20.22 V. Nevertheless, it can be seen that the proposed PSMLI is functioning without any issues and the capacitor voltages are balanced even after the voltage fluctuation has occurred. During the change in modulation index and load from Fig. 18(b) and Fig. 18(c) respectively, it is noticeable that there is no change in the capacitor voltages. Therefore, it can be stated that the change in modulation index or the load does not have any impact on the capacitors' performance.
Finally, the performance of PSMLI is investigated under non-linear load conditions where the output of the MLI is connected with a single-phase bridge rectifier and inductive load (40 -5 mH). The 9-level output voltage can be observed to be completely similar to the previous case studies as shown in Fig. 19. However, the current of the PSMLI has slight distortions which is due to the fact the non-linear load   has induced current harmonics into the system. This issue can be effectively dealt with custom power devices such as shunt active power filters [3], [4].

VI. CONCLUSION
This manuscript presents a novel multilevel inverter unit that employs 2 DC sources and 2 switched capacitors to produce 9 voltage levels. The PSMLI is built utilizing a T-type inverter and a directional module that are put together back-to-back and encircled by extra switches. It can be extended effectively or can be designed using both symmetric and asymmetric DC-links to achieve higher output voltage. Additionally, it has comparatively reduced TSV and power electric components since it is a self-balanced MLI i.e., it does not require any additional power components to balance the capacitor voltages. PSMLI's another advantage is its ability to generate negative voltage without the need of an additional H-bridge unit. This has also contributed to its lower TSV and structural simplicity. The PSMLI unit is simulated and experimentally assessed, and it shows good results on both occasions. There is a high similarity between the simulated and experimental results which validates its accurate operation. A high efficiency of 95.54% is obtained which is better than most of the recently proposed MLIs as demonstrated in the comparative analysis section. PSMLI also achieved a low THD of 6.4% and 2.58% for 17level module and 33-level module, respectively and have successfully followed IEEE 519 2014 standard. The results also showed that the capacitor voltages of PSMLI are balanced with a very low voltage ripple of 3.23 V. These results indicate the industrial suitability of the proposed module. He has been a Professor of intelligent systems with the Department of Electrical Power Engineering, College of Engineering, Universiti Tenaga Nasional, Malaysia, since September 2016. He has more than 28 years of industrial and academic experience and an author or a coauthor of over 300 papers published in international journals and conference proceedings. His research interests include intelligent controllers, power electronics, hybrid vehicles, energy storage systems, image and signal processing, and artificial intelligence. He is an Editorial Board Member of many journals. He has been received several IEEE best paper awards. He received numbers of gold awards for his innovative research in ITEX, MTE, INNOFEST, SIIF, and PERINTIS. He is the Organizing Chair of many conferences e.g., ICEE 2019 and PEAE 2019. He is the Editor-in-Chief of the journal Energy and Environment and an Associate Editor of IEEE ACCESS and IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS. VOLUME 10, 2022