Combined Optimizer for Automatic Design of Machine Learning-Based Fault Classifier for Multilevel Inverters

Fault detection and classification are fundamental requirements of multilevel inverters (MLIs) to ensure constant operation and improved reliability. Nowadays, the machine learning (ML) technique is utilized for fault diagnosis in MLIs due to its inherent features such as high accuracy, reduced computation time, and complexity. However, the rich availability of parts and classifiers in ML techniques demands a tedious investigation of every combination to design an optimal fault classifier. To overcome this problem, a combined optimiser is proposed to automate the ML-based classifier design, which involves selecting optimal features and classifier. Mean, total harmonic distortion, root mean square, and different harmonic orders (upto 12th order) of the output voltage of MLI are considered as features and four different ML techniques like K-nearest neighborhood, decision tree, Naive Bayesian classifier, and support vector machines are considered. Ant Colony Optimization (ACO) is used to formulate a combinatorial optimization routine to maximize classification accuracy by optimal selection of features and classifier. The proposed technique is used to design a fault classifier for two different MLIs, such as Cascaded H-bridge MLI (CHBMLI) and Packed U cell inverter (PUC), during the fault conditions (open circuit and short circuit) to check the feasibility. Simulation results illustrate classification accuracy of 97.84% and 98.61% for CHBMLI and PUC, respectively. Experimental validation of the designed classifier on the inverter prototype is also carried out and illustrates 95.56% and 94.28% classification accuracy for CHBMLI and PUC, respectively.


I. INTRODUCTION
Multilevel inverters (MLIs) have been utilized in high-power renewable energy sources [1] like windmills, photovoltaic [2]- [4] and fuel cells. Easy integration and fewer harmonics encourage their applications in many industries [5]. Among several topologies of MLIs, the cascaded H-bridge Multilevel inverter (CHBMLI) exhibits reliable performance in variable speed applications [6], [7] and renewable energy source integration [8]. Harmonic reduction in CHBMLI is achieved by increasing the levels, which leads to an increase The associate editor coordinating the review of this manuscript and approving it for publication was Joey Tianyi Zhou. in power semiconductor switches [9]. It increases the complexity and reduces reliability [10].
In CHBMLI, 38% of faults are occurred due to the malfunction of power semiconductor devices like IGBTs or MOSFETs [11]. Open circuits, short circuits, and gate misfires are common failures in power semiconductor devices that occur due to excess thermal and electric stress. Continuous operation of CHBMLI under such failure conditions leads to additional failures and causes serious effects [12].
For instance, failures in switching devices of CHBMLI supplying a traction motor in a hybrid electric vehicle will affect the speed control operation [13]. Downtime associated with inverter failures in industries affects the production cycle and causes a massive loss of cost per hour. Shielding circuits have been used in inverters to safeguard and decrease the impact of power semiconductor device failures. However, they may fail due to abnormal use, complicated circuit arrangement, disturbance in load, power system disturbance, and electromagnetic interference [14]. In recent times, a Packed U-Cell (PUC) type inverter has been preferred [15], which integrates the merits of a flying capacitor (F.C.) and CHBMLI inverter. PUC topology contains the minimum number of switches compared to the CHBMLI, making the system compact, more efficient, and cost-effective [16]. The compact PUC inverters have been utilized in critical applications like motor control, grid interfaces, and Flexible A.C. transmission system (FACTS). In variable speed drive, the fault occurs often owing to power semiconductor device failure. Therefore, the detection and classification of faults are essential. Reduction in switching components demands more reliability [17], and it necessitates fault diagnosis and tolerant strategies. Hence, a combined optimizer is developed in the proposed work to automate the design of ML-based classifier by selecting the optimal features and classification technique for both CHBMLI and PUC inverters.
Fault diagnosis technique based on output voltage or current is widely used and reliable for inverters. It enables the detection of fault location and identification of fault type [18]. Type of faults and its location are essential to plan mitigation procedures to overcome the failure [19]. Three types of fault diagnostics techniques, namely (i) model-based [20], (ii) knowledge-based [21], and (iii) data-driven based, have been discussed in the literature. An exact mathematical model has been required for defining the fault mechanisms in a model-based approach. Developing such a mathematical model for the complex structured inverter circuit is a tedious task. Moreover, these mathematical models are limited in solving particular fault problems [22].
Unlike the model-based method, the knowledge-based approach is widely applied in complex inverters, which does not depend on a precise mathematical model. It needs a complete knowledge (fault type and location) and interference engine. This method depends highly on the practical knowledge of the professionals, and the diagnosis accuracy relies on the significant amount of professional expertise available in the knowledge base [23]. Fuzzy-based support vector machine (SVM) has been reported [24] for higher accuracy than other approaches. However, this method takes more computing time to diagnose the fault and requires expert knowledge to tune the rules manually.
The availability of rich data encourages the usage of data-driven methods like machine learning (ML) approaches. Predominant of the ML techniques, namely Support vector machine (SVM) [8], Artificial Neural Network (ANN) [25], and K-nearest neighbor (KNN) [26], belong to the datadriven approach. Fault diagnosis using intelligent data-driven algorithms has turned out to be a research hotspot in recent years [27], [28]. Fault diagnosis technique fundamentally demands in-depth knowledge about the operations of the inverters to understand its working under normal conditions. Any deviations from its normal operations have to be analyzed to determine the fault type and severity. Hence, the inverter design-specific nature of fault detection systems demands significant effort and expert knowledge. ML technique emerges as the mitigation strategy to automatically learn the correlation between the features and faults. ML tends to eliminate the need for expert knowledge on inverter operations.
These ML techniques have been incorporated into feature extraction procedures to increase fault diagnosis performances. Statistical techniques, Fast Fourier Transform (FFT),wavelet transforms [29], [30], and Principal Component Analysis (PCA) has been used to extract the features for fault detection. The number of fault classes may increase depending on the number of switches utilized in developed multilevel inverter for generating the required output voltage level. Due to the increase in fault classes, more features may require for fault classification.
A complex neural network with 40 input (features) neurons has been utilized to detect open circuit fault in MLI using FFT signals [31]. Genetic algorithm (GA) and PCA has been used to reduce the required features and complexity of the classifiers. A fault diagnosis approach based on the FFT-PCAmulticlass relevance vector machine has been developed to diagnose the open circuit faults in CHBMLI [32]. Operator knowledge has also been used to select the required features using PCA [31], [32]. Limiting the number of fault classes is another approach to reducing the classifier complexity. Open and short circuit faults were classified using FFT-based features [33].
The availability of vast features and classifiers in ML enables a large number of combinations which need to be investigated to design the best fault classifier. Though techniques like GA., PCA, and random forest algorithm have been used for optimal feature selection, the choice of classifiers remains biased. The lesser training time of shallow ML-based classifiers like SVM, KNN, NBC, and decision trees allows the use of an optimization routine for the combined selection of features and classifier. Hence, a combined optimizer is proposed in this work to simultaneously select both the features and classifier, which is required to design a fault classification method for CHBMLI and PUC. A search space comprising static and harmonic features extracted from the output voltage along with several ML-based classifiers is formulated. Ant colony optimization (ACO) is also used to select the unique combination of features and classifier from the search space to maximize the classification accuracy.
Major contributions of the proposed work are as follows (i) Design of combined optimizer using ACO to select the optimal features and classifier without manual interventions.
(ii) Formulate the cost function to provide better classification accuracy.
(iii) The proposed method is suitable for fault diagnosis in open circuit and short circuit fault conditions to any MLI configuration. VOLUME 10, 2022 (iv) Simulation has been carried out during healthy and faulty conditions (open circuit and short circuit) of CHBMLI and PUC.
(v) Experimental validation of the proposed design procedure to design a classifier for fault classification in CHBMLI and PUC type inverter.
The rest of the paper is organized as follows: Section 2 describes the related background required for problem formulation. It explains the operation and fault characteristics of CHBMLI and PUC inverters. Section 3 provides a brief introduction to feature extraction and the classifier considered in this study. Section 4 explains the proposed design of an ACO-based combined optimizer for selecting features and classifiers. Section 5 shows the experimental results and comparative analysis, and Section 6 concludes this work with future direction.

II. RELATED BACKGROUND
Multilevel inverters are widely used in A.C. drives, nonpollutant renewable energy integration, and active power filters. In Multilevel inverter families, cascaded H-bridge Multilevel inverters have gained significant attention because they satisfy the medium voltage and high-power requirements in industries but require more semiconductor devices. This drawback is overcome in the PUC inverter. PUC inverters need lesser semiconductor switches to attain the same voltage level as CHBMLI. CHBMLI and PUC inverters are chosen in the proposed work due to their distinct features.

A. ARCHITECTURE OF CHBMLI
A single-phase CHBMLI is connected to the motor load, as illustrated in Figure 1. It generates a five-level output voltage by combining the two H-bridge inverter modules in series with the separate D.C. source in symmetric conditions. Each H-bridge inverter module consists of 4 IGBT switches marked as T 1 , T 2 , T 3 , T 4, and T 5 , T 6 , T 7 , and T 8 . The output voltage of CHBMLI is produced by the combination of voltage generated in the two modules.
The switching pulses necessary for IGBT switches are generated by using the Alternative Phase Opposition Disposition (APOD) technique, as shown in Figure 2. The carrier frequency and modulation index of a sinusoidal signal are set as 3 kHz and 0.8, respectively. In this technique, each triangular waveform is out of phase by 180 o with its alternate waveform, and a sinusoidal signal is kept as a reference. To generate an output voltage with x levels, the MLI uses x − 1 triangular waveforms. The switching scheme of the CHBMLI is shown in Table 1. The number of H-bridge (N H ) used in the MLI determines the output voltage level (L v ) as in (1), which in turn describes the smoothness of the generated A.C. voltage. The increase in the number of H-bridge and their associated switching components necessitates the need for fault-tolerant systems in MLI.   The operating modes of the CHBMLI are discussed in [34]. Initially, switches T 1 , T 2 , T 5, and T 6 are turned ON and the other four switches T 3 , T 4, T 7, and T 8 are turned OFF, to get an output voltage level of +2V dc . To get the +V dc level at output voltage, the switches T 1 , T 2 , T 8, and T 6 are turned ON and the other switches namely T 3 , T 4 , T 7, and T 5 are set to OFF. Finally, switches T 2, T 4 , T 6 , and T 8 are turned ON and all the other switches are turned OFF. So that no current will flow in the power circuit creating a level of zero output voltage. Thus, all the switches in the CHBMLI play a vital role in determining the waveshape of the output voltage. It necessitates a need to diagnose and ensure the health of these switches for reliable power delivery using the CHBMLI.

B. ARCHITECTURE OF PUC INVERTER
The main merits of the PUC inverter are the minimum number of active switches and the minimum requirement of gate drivers. The component count of the PUC inverter is compared with other popular inverters like CHB, NPC, and F.C., and the component count comparison is shown in Table 2 [35].
A single-phase 5-level PUC inverter is shown in figure 3. It consists of two dc sources in symmetric condition and 6 power semiconductor switches. It is worth mentioning that T 4 , T 5 and T 6 are the complementary switches of T 1 , T 2 and T 3, respectively. The operating modes and the advantage of this topology are discussed in [36]. The switching states of this topology for generating the five-level output voltage are shown in table 3.  PUC inverter turns ON the switches T 1 , T 5, and T 6, and switches T 2 , T 3 , T 4, and T 8 are turned OFF to get an output voltage level of +2V dc . A +V dc is obtained by turning ON the switches T 1 , T 5 , and T 3, and all the other switches like T 2 , T 4, and T 6 are set to be OFF. The current in the power circuit is made as zero by turning ON switches T 1 , T 2 , and, T 3, and all the other switches T 4, T 5 , and T 6 are turned OFF. It enables to have the output voltage at level zero. The structure of the generalized fault diagnosis approach [32] for inverters is illustrated in Figure 4. MLI tends to provide a smooth sinusoidal waveform using multiple D.C. sources by generating a periodic switching pattern. In a fault diagnosis approach, the output voltage signal of MLI is measured because these signals consist of reliable information and are independent of load variations. The measured signals are preprocessed and the required features are extracted. Statistical features like % THD, RMS, Mean, and frequency domain features like harmonic distortions are extracted from the measured voltage signal. These features are extracted from MLI and given as input to the fault classifier. A fault classifier uses these extracted features to determine the fault class.

III. METHODOLOGY
The design of an ML-based fault classifier involves various steps, as described in Figure 5. The ML-based classifier requires a data set describing various fault conditions in the inverter. Hence, various faults are induced into the inverter, and the corresponding output voltages are acquired. Features are extracted from the acquired output voltage signal, and VOLUME 10, 2022 the data set is prepared with the corresponding fault class. A training dataset is used to train the ML-classifier, and another set of datasets are used to test the trained classifier. The testing performance is evaluated using standard performance metrics and deployed. The choice of features and classifier plays a vital role in designing an efficient fault classifier, which has been investigated in this work.

A. DATASET PREPARATION
The output voltage waveform is considered a diagnostic parameter to diagnose the fault in the proposed technique, whereas the output current changes with respect to the different loads. Faults are induced in each switch of the inverter and its corresponding output voltage waveform is acquired. Healthy condition, open-circuit, and short-circuit faults are induced with varying modulation indexes. For instance, at a certain value of modulation index (m = 0.8), the output voltage waveforms for healthy conditions, open-circuit faults of switches T 1 to T 4 and short-circuit faults of T 5 to T 8 in CHBMLI are observed as in Figure 6. A distinctive pattern of the output voltage waveforms is observed for different switch fault conditions, which serve as a reliable marker for fault classification. Similarly, the open-circuit and short circuit faults are created in each switch of the PUC topology, and the corresponding output voltage waveforms are observed as in Figure 7. The voltage waveforms observed during healthy and faulty conditions of each switch have unique characteristics that provide a reliable marker for fault classification. It is observed that the positive half cycle and the negative half cycle are completely diminished due to the open circuit fault of T 1 and T 3 respectively. Hence the failure in these switches greatly affects the performance of the PUC which needs to be diagnosed quickly to avoid serious failures.  All the switches in the CHBMLI (8 switches) and PUC (6 switches) are considered in the proposed work. Each switch is subjected to O.C. and S.C. conditions to simulate various fault classes along with normal operating conditions as one class, as in Table 4 for CHBMLI and Table 5 for PUC.

C. FEATURE EXTRACTION
Any ML-based classification consists of two steps, namely, feature extraction and classification. In the feature extraction step, the feature required for classification is extracted from the measurement signal. Features define the abstraction of the measurement signal and convey reliable information used for classification. A unique combination of features for a particular class is often preferred, which enables an accurate classification. Hence, the choice of features plays a vital role in determining the classification performance of the ML-based fault classifier.
In this work, three static features (Mean, % THD, VRMS) and eleven harmonic features (individual harmonic order up to 12th order) are extracted from the output voltage as described in Table 6. These features have a higher degree of detectable variations during the faulty conditions and contain reliable markers on the fault type. Mean value provides a D.C. shift encountered and loss of symmetrical pattern during the faulty conditions of MLI. The RMS value detects the peak value of distortions in the output voltage. Noise introduced by the switching faults provides significant variations in % THD. The first 11 harmonic orders ( H 2−12 ) of the output voltage are also extracted using FFT analysis and used as features. If the dominant harmonics are present in the lower order, it affects the system performance and also, the designing of filters is difficult. Therefore, the individual harmonic orders up to the 12 th order are considered in this work.

D. ML-BASED CLASSIFIER
In the proposed work, four different classifiers, namely, decision tree (D.T.), K-nearest neighbor (KNN), Naive Bayesian classifier (NBC), and support vector machines (SVM) are considered in this work. The choice of these classifiers is strongly encouraged by the literature for fault classification applications.
KNN is a supervised learning algorithm widely used for regression and classification applications. This algorithm tends to cluster the identical data that are near in proximity. During learning, the rule for partition of the whole training data is carried out and allots a particular label for the cluster. For unknown data, the distance between the unknown and the training data set is computed. The unknown data is classified using the minimum distance criterion. KNN exhibits a higher level of accuracy and excellent stability [37]. It is used to identify the O.C. faults in a cascaded Multilevel inverter [26]. It tends to select features that are close neighbors and forms a cluster corresponding to the fault type. Its non-parametric approach makes it a preferred choice for data-driven classifier design. VOLUME 10, 2022 The decision tree (D.T.) algorithm has a top to bottom approach that searches the features to decide on the fault type. It has a tree-like structure, where the features of the data set are represented by an internal node, decision rules are represented by branches, and the outcome is represented by a leaf node. This tree is mainly preferred for resolving classification problems. D.T. has a successive model that unites a sequence of the basic test proficiently and cohesively [38]. An optimal classification tree is constructed to detect and diagnose the fault. It is similar to a flowchart but has a tree-like structure.
SVM uses statistical learning theory to construct classifiers. It tends to divide the features in a hyperplane to understand their fault specific characteristics. Hyperplane is created with extreme vectors, which describes the variations across features. It is a supervised learning model with accompanying learning algorithms that are used to examine features and recognize patterns across each fault type. It is widely used in applications like classification, regression models, and pattern recognition. It can overcome the limitations in data dimensionality and inadequate samples. This makes it ideal for fault classification in inverters, where wider range of fault class is encountered. SVM is use to diagnose the O.C. faults in cascaded Multilevel inverters [8].
Naïve Bayesian classifier (NBC) is one of the quickest learning algorithms and able to handle larger number of classes. Simple in construction, efficient classification and immune to noise in data sets are some of the metrics that encourages the used of NBC for fault classification. It is a supervised probabilistic classifier predominantly used for classification [39]. Knowledge-based nature of NBC encourages its usage for both binary and multiclass pattern classification. It estimates the fault class based on the likelihood of the features. It is used to decide the possibility of a premise with previous information extracted from the training set. It relies on conditional probability estimated using the Bayes theorem is given as in (2). P(A|B) = P(A|B)P(A))/P(B) NBC is used for image classification in [40] due to its greater classification accuracy and fast computing time, which makes it dependable in real-time applications [41], [42].

E. PROPOSED COMBINED OPTIMIZER FOR ML-BASED FAULT CLASSIFIER DESIGN
The design of an ML-based fault classifier involves the selection of optimal features and classification technique, which has been investigated in this work using a combined optimizer as in Figure 8. The combined optimizer tends to select the optimal features from the set of features described in Section C. These features are extracted from the output measured voltage (V m ) acquired from the faulty inverter. It also selects one ML classifier from the given set of classifiers as described in Section D. The optimal selection of features and classifier is governed by evaluating the classification accuracy using confusion matrix analysis. The proposed combined optimizer is designed using ACO based combinatorial optimization technique. ACO is one of the popular and reliable techniques for solving combinatorial optimization problems [43]. It is a metaheuristic technique that was inspired by the communicative and navigation behavior of ants to solve their path planning problems. Ants tend to define an optimal path that can be traced to bring in the food to their nest. They define the shortest path by avoiding obstacles through their collaborative nature. Ants deposits pheromone (a scented chemical substance) on their navigation path, which leaves traces for other ants to recognize. This deposited pheromone is used by the ants to determine the optimal path by their foraging behavior. This natural-inspired technique is mathematically formulated as ACO for solving various applications.
In the proposed work, an ACO-based combinatorial optimization problem is used to determine the optimal selector ant, which can minimize the cost function. The cost function is formulated in terms of classification accuracy, which is evaluated using a confusion matrix and as a function of selector ant, as illustrated in Figure 9.
The selector ant has information to select the optimal features (F S ) and classifier (c S ) from the given set of features (F) and classifiers (C), respectively. In the proposed work, about fourteen features (M = 14) and five classifiers (N = 5) are considered as in (3) and (4), respectively. Each selector ant (A S ) has the mask formulated using '1s' and '0s' of length (N + m) as in (5). It is used as a gating signal for feature and classifier selection. For feature selection, a '1' indicates the closure of the gate, which allows the particular feature to be used for training the classifier, and a '0' opens the gate restricting the features as in (6). Unlike features, only one classifier is selected using the (m) gating signals from the selector ant. The classifier gating signals (m = log 2 M ) is used by the decimal decoder to select one classifier from the available classifier set (M ). The decimal decoder tends to convert the binary gating signal into a corresponding decimal to select the classifier as in (7). The selected classifier (c s ) is trained using the training data of the selected features (F tr S ) to design an ML-based fault classifier (Fc) as in (8).
The classification performance of the trained classifier is evaluated in terms of classification accuracy to formulate the cost function. The predicted fault class (Cl i P ) for the given feature set is determined using the trained classifier as in (9). Then, the predicted class is compared with the actual fault class (Cl i A ) to determine the classification accuracy (CA t ) in percentage as in (10). The classification accuracy for training (CA tr ) and testing data (CA te ) are calculated, and weights added. The weights provide the importance of each classification accuracy in evaluating the cost function (CF) as in (11). Thus, the objective of the proposed combined optimizer is to determine the selector ant (A f ), which can minimize the cost function with the choice of features and classifier as in (12).

IV. RESULTS AND DISCUSSION
The proposed work aims to formulate an automated technique to design an ML-based fault classifier. It majorly involves the choice of features and the classifier, which are determined using a multi-objective ACO algorithm. It tends to choose the optimal features and the ML classifier that maximizes the classification accuracy for fault classification. The performance of the proposed design technique is evaluated using two types of Multilevel inverters (CHBMLI and PUC). The switches in the Multilevel inverter are subjected to O.C. and S.C. faults, which need to be identified to provide proper mitigation. Features like Mean value, RMS value, Harmonic order, and %THD of the output voltage signal under healthy, O.C., and S.C. faulty circumstances are extracted. The extracted features are labeled to create the data set required for training the ML classifier. The data set is segregated to have 80% of data for training and 20% of data for testing the classifier, as in Table 7. Four widely used ML-based classifiers, namely D.T., KNN, NBC, and SVM, are considered in this study, and the ACO is responsible for choosing any one optimal classifier out of them. The choice in features and classifier across various iterations of the proposed combined optimizer are acquired as in Figures 10 to 13, respectively. The actual choice of features and classifier of all the ants and choice of best ant is observed. It is indicated that the fault classifier of CHBMLI uses a higher number of features at initial iterations and settles at seven optimal features. Similarly, among the four classifiers, a close competition exists between the choice of NBC and KNN classifiers. However, KNN is chosen to be the optimal classifier to detect faults in CHBMLI.
During the automatic design of the fault classifier for PUC, a minimal number of features are selected during initial VOLUME 10, 2022  iterations, and features are increased to maximize the classification accuracy. Finally, optimal eight features are selected. NBC is selected as the fault classifier, which provides maximum classification accuracy.
The designed ML-based classifier with optimal selected features is evaluated using a confusion matrix at various levels. Initially, the fault classes are grouped as no faults indicating a health inverter, O.C. faults, and S.C. faults. It is observed that the KNN-based fault classifier used in CHBMLI is capable of classifying the fault type accurately without any error, as indicated by the confusion matrix in Table 8. Whereas in PUC, the NBC-based fault classifier misclassifies one O.C. fault as an S.C. fault leading to the classification accuracy of 98.6%, for testing data, as indicated by the confusion matrix in Table 9.
The switch-specific fault classification performance is also evaluated in Tables 10 and 11, which tend to identify the type of fault and the corresponding faulty switch. The data   responsible for the misclassification and its classification accuracy is also tabulated. It is observed that in one instance, the S.C. fault occurred in T 9 switch of PUC is predicted as it occurred in T 10 . Similarly, in three instances of testing data, the fault classifier failed to detect the faulty switch in the CHBMLI inverter.

A. COMPARISON WITH CONVENTIONAL TECHNIQUE
The performance of the ML-based classifier designed using the proposed combined optimizer is compared with the   conventional classifier designed with no feature and classifier selection. With no feature selection procedure available, all features are used to design the conventional classifier. Four ML classifiers considered in this study are used individually to design the fault classifier for both the inverters as described in Tables 12 & 13. The training and testing classification accuracy is evaluated and is considered as performance metrics. It is observed that the proposed combined optimizer is capable of selecting optimal features and a classifier that can significantly improve the classification accuracy as compared with the conventional classifier design.
It is observed that the D.T. and SVM have a lesser level of classification accuracy with the use of conventional design techniques. KNN suffers overfitting with higher classification accuracy on the training dataset. But fails to classify the testing dataset accurately. NBC provides higher performance to detect the fault in CHBMLI. However, with the use of optimal features selected by the proposed design, NBC exhibits a significantly higher performance as compared with other conventional techniques as described in Table 12. Similarly, KNN is capable of detecting the fault in the PUC inverter accurately with the use of all features in conventional design. The proposed design tends to select KNN with eight optimal features enabling it to have a higher level of accurate fault detection as described in Table 13.

B. EXPERIMENTAL ANALYSIS
A laboratory-scaled prototype is developed for the selected MLIs such as CHBMLI and PUC separately, as in Figure 14. The MLIs are constructed using IGBT switches, a TPL350 driver, and two D.C. sources. These MLIs are capable of generating a five-level output voltage. The switching signals are generated using a real-time controller (FPGA) by incorporating the APOD PWM technique. The prototype is equipped with a voltage sensor to acquire the output voltage for the various modulation indices. It also has a 3196-power quality analyzer to extract the features from the acquired output voltage.
In the experimental setup, healthy and O.C. faults are only investigated due to the practical difficulties in realizing S.C. faults. The O.C. fault is created by disconnecting the gate signal from the corresponding switch and the output voltage is measured at various modulation indices ranging from 0.6 to 1. The output voltage acquired from the experimental setup during healthy and O.C. faulty conditions indicates observable changes as in Figure 15 for the modulation index 0.8. The O.C. fault in the switch T 1 causes the voltage to lose its positive peak value making it biased towards the negative cycle and vice versa during O.C. fault at the switch T 2 of CHBMLI. A similar change in output voltage is observed in the PUC inverter also, as in Figure 16. Table 14 represents the accuracy of experimental dataset values for CHBMLI and PUC using a confusion matrix. The experimental results illustrate a reliable classification accuracy of 95.56% and 94.31% for CHBMLI and PUC respectively.
Further, the experimental setup is compared with the simulation studies in terms of feature extraction and fault classification. The quality of voltage measurement and the VOLUME 10, 2022   corresponding features extracted during experimental implementation are evaluated by comparing with simulation. Mean absolute error (MAE) as described in (13) is used as a performance metric for comparison. It tends to calculate the deviation between the features extracted from the simulated    Table 15. It is observed that the THD and RMS feature have lesser deviations. The harmonic order will have increased deviations at higher orders. The classification accuracy for the experimental setup is compared with the simulation as described in Table 16. Minor deviation in classification accuracy is observed due to the noise associated with the measurement signal and features extracted from the experimental setup. Analysis indicates a significant detection accuracy making the proposed design ideal for real-time implementation.

V. CONCLUSION
In this paper, a fully automated methodology to design a machine learning-based classifier is proposed using a combined optimizer. A combined optimizer tends to select optimal features and classifiers using the ACO-based Combinatorial optimization technique. A multi-objective ACO is formulated using classification accuracy as the performance metric. The different features such as mean, % THD, RMS, and harmonic orders (upto 12 th order) from the output voltage of the selected MLI have been considered as features for the proposed ML technique. The proposed combined optimizer is used to design a fault classifier for Multilevel inverters. Two widely used inverters, namely CHBMLI and PUC, are selected. Open circuit and short circuit faults are detected based on the features extracted from the output voltage of the selected MLI. About 7 features with the KNN classifier are selected to design an optimal fault classifier for CHBMLI. Similarly, NBC with 8 features is selected for PUC. The proposed fault diagnosis technique has improved accuracy which will decrease the operating time of electrical equipment's and also increase the working life span of equipment under abnormal circumstances. The experimental results have been taken for CHBMLI and PUC with the implementation of proposed technique to corroborate their performance. Simulation results illustrate a reliable classification accuracy of 97.84% and 98.56% for CHBMLI and PUC inverters, respectively. In addition, the designed classifiers are also subjected to detect the fault in the laboratory-scale prototype of MLIs with the classification accuracy 95.56% and 94.28% for CHBMLI and PUC respectively. Reliable performance with significant classification accuracy is observed to make the proposed combined optimizer a reliable tool for designing ML-based classifiers.
The proposed automated design methodology can be used to design classifiers for other power converters. The designed classifier can be integrated with fault isolation and mitigation systems to ensure operational continuity.
V. SUDHA is currently pursuing the Ph.D. degree with SASTRA Deemed to be University, Thanjavur, India. Her current research interests include power electronics and fault diagnosis in multilevel inverters.
K. VIJAYAREKHA received the bachelor's degree in electrical and electronics engineering from the Alagappa Chettiar College of Engineering and Technology, Karaikudi, in 1990, the M.E. degree in power systems from the NIT, Trichy, in 1992, and the Ph.D. degree from SASTRA University, in 2008. She has teaching experience of 26 years. She has published more than 72 research papers in reputed national and international journals and conferences in the area of image processing, power converters, non destructive testing, interharmonics, and FACTS. Under her guidance three candidates completed and six are doing their Ph.D. in SASTRA Deemed to be University.
RAKESH KUMAR SIDHARTHAN received the Ph.D. degree in autonomous navigation for mobile robots. He is currently working as a Technical Manager with the ERS Division, HCL Technologies Ltd. He has been working on the development of AI and ML-based solutions for robotics and automation applications. He has also developed a vision-enabled robot control framework for automated device testing applications. He has also published more than 50 research papers in various peer-reviewed journals and conferences. His research interests include robotics, deep learning, and MPC.