A Low-Power Wide-Load-Range Output-Capacitorless Low-Dropout Voltage Regulator With Indirect-Direct Nested Miller Compensation

This paper presents the design of an output-capacitorless low-dropout voltage regulator (OCL-LDO) capable of driving a wide range of load capacitance and supplying a wide range of load current while maintaining excellent load and line regulations, thanks to the combined indirect-direct nested Miller compensation which ensures stability and maintains a high loop gain over the whole range of load condition. Fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process and consuming 14 <inline-formula> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> of quiescent current, the OCL-LDO, while supplying the load current between 0 mA to 100 mA, is capable of driving the load capacitance in the range of 0–1 nF; with a minimum load current of 1 mA, however, the OCL-LDO can drive up to 10 nF of load capacitance. Over such wide load-current and load-capacitance ranges, the OCL-LDO achieves DC load and line regulations of 0.025 mV/mA and 0.5 mV/V, respectively.


I. INTRODUCTION
In the past several decades, the world has witnessed technological revolution at a rate unparalleled in the previous history of mankind, thanks to the advent of system-on-chips (SoCs) that provides ubiquitous computing power to almost all aspects of human life. Integrated with many functionalities in a very small footprint, SoCs make possible various computing tasks ranging from high-speed number crunching in mainframe computers down to sensing, processing, and communication normally performed in wireless low-power sensor interfaces [1]- [4].
In low-power sensor interfaces, supplying power to the SoC's core is normally performed by a low-dropout voltage regulator (LDO) generating a clean power supply from rippled DC voltage produced by a switching DC-DC converter. In applications requiring very small footprint such The associate editor coordinating the review of this manuscript and approving it for publication was Venkata Rajesh Pamula . as radio-frequency identification (RF-ID) tags [5]- [7] or wirelessly-powered medical implants [8]- [11], LDO, especially the ones requiring no off-chip capacitor to stabilize its operation (output-capacitorless LDO or OCL-LDO in short), may often be the sole component providing power to the SoC's core as it eliminates off-chip passive components normally required in most switching DC-DC converters. In recent years, research on OCL-LDO has gained increasing popularity, with a major emphasis on improving the OCL-LDO's response to fast changes in the load current [12]- [16], especially from high-speed on-chip digital and RF circuits-in other words, making the OCL-LDO behave more like an ideal voltage source over as high a bandwidth as possible. As OCL-LDO employs feedback to regulate its output voltage to a certain reference, a fast-response OCL-LDO normally requires a very large loop bandwidth, which leads to higher quiescent power. However, employing a highspeed OCL-LDO can be an overkill in some low-power SoC's architectures in which the high-speed circuits are powered off most of the time to save power, and powered on only briefly to perform necessary tasks. In addition, it might not be practical in such applications to leave the supply regulation of the high-speed circuits solely to the OCL-LDO since, no matter how ideal is the OCL-LDO, significant voltage spikes can still develop from the IR drop across parasitic resistance and inductance in the supply lines and also across the ON resistances of the power-gating transistors. Hence, in practical SoCs housing high-speed circuits, supply decoupling capacitors, mostly in the form of MOS capacitor due to its high-density capacitance, are normally placed in close proximity and connected to the supply nodes of these circuits to help smooth out their supply voltages.
To appreciate this, consider a scenario depicted in Fig. 1 in which an OCL-LDO is to power a low-power SoC's core that consists of many modules-sensitive low-power analog frontend, high-speed digital processor, and radio-frequency (RF) communication module. The main task of this SoC is to continuously but slowly senses the input data from the environment, store it in a local memory, and then process and wirelessly transmit the stored data to a receiver outside. To save power from the leakage and standby current, the digital and RF modules may be powered down most of the time-with the power-gating transistors M PG1 and M PG2 to help minimize leakage current--and powered up only briefly to quickly process and transmit data to an off-chip receiver. Each block has its own local capacitor, C 1 -C 3 , close by to help smooth out its supply voltage. Due to the fast switching nature of the digital processor and the speed of the RF module, their on-chip supply-decoupling capacitors are normally much larger-often in the nanofarad range [17], [18]-compared to that of the analog frontend. We can now envision that-most of the time when the digital and RF modules are powered down and cut off from the OCL-LDO by M PG1 and M PG2 -the OCL-LDO will see only the small C 1 (possibly around tens of pF) and needs to supply only small load current (possibly around tens of µA). However, during the brief periods when both the digital and RF modules are powered up and connected to the OCL-LDO's output via M PG1 and M PG2 , the OCL-LDO will see very large capacitive load from C 2 and C 3 (possibly from hundreds of pF's to a few nF's) and may need to supply a very large load current (tens of milliamps). Therefore, the OCL-LDO designed for such applications should be guaranteed stable over the load current ranging from a few µA's to several tens of mA's and a load capacitance ranging from a few pF's to a few nF's. Furthermore, in applications such as the RF-ID tag, the input voltage into the OCL-LDO may vary appreciably depending on the state of its power source-e.g., the distance between an RF-ID tag and its reader. Hence, the OCL-LDO not only needs to provide a very accurate output voltage across a wide load current range (good DC load regulation), it also does for a wide input voltage range (good DC line regulation).
To achieve good DC load and line regulations, conventional LDOs are usually implemented as three-stage feedback circuits-two-stage error amplifier (EA) followed by an output stage comprising a power transistor-to provide very large loop gain. The wide load current and load capacitance ranges make stabilization of a three-stage LDO very challenging. Hence, most conventional LDOs employ a very large off-chip capacitor (normally in the µF's range) at the output to make the output pole dominant regardless of the load current and load capacitance; the equivalent series resistance (ESR) within the off-chip capacitor also helps improve stability by creating a left-half-plane (LHP) zero that helps cancel the effect of the first non-dominant pole within the LDO [19]- [25]. However, such a large off-chip output capacitor is not available for an OCL-LDO. Therefore, stabilization of an OCL-LDO often requires creating the dominant pole out of an internal node within the circuit.
There are many realizations of this principle. The simplest category is the class of OCL-LDOs that employ only two gain stages in feedback for ease of compensation. Stabilization of such topology is achieved by ensuring that the dominant pole is associated with the internal node (i.e., the gate of the power MOSFET, which normally exhibits large capacitance) and not the output node (i.e., by requiring minimum load current and/or maximum load capacitance). The popular flippedvoltage-follower-based (FVF-based) OCL-LDOs [26]- [30] can be categorized in this class along with those employing differential opamp-based error amplifiers (EA) [15], [31], [32]. Lacking an explicit frequency-compensation scheme, the FVF-based OCL-LDOs in [26]- [30] often require a certain minimum load currents or maximum load capacitances to ensure that the output pole is beyond the unity-gain bandwidth to guarantee stability, thus, making the load current and capacitance ranges quite narrow. Also, due to their meager loop gains, these two-stage OCL-LDOs normally exhibit inferior DC load/line regulations compared to other topologies with higher loop gain.
Improving the load/line regulations can be achieved by an addition of another gain stage within the LDO's feedback loop, making it a three-stage feedback circuit. The FVF-based OCL-LDO in [33] and differential EA-based OCL-LDOs in [34]- [36] are some examples. With three gain stages in their feedback loops, these OCL-LDOs often employ a Miller compensation approach to ensure stability as in the design of three-stage opamps. However, compensation of a three-stage OCL-LDO is much more difficult than that of a three-stage opamp due to the OCL-LDO's output pole occupying a very wide range as the load condition changes: if not prudently compensated, the LDO may exhibit closed-loop poles that are nicely damped at a certain load conditions but become very underdamped (have a high Q-factor) at other load conditions. Many methods were proposed to limit the Q-factor in threestage LDOs-e.g., [34] employs a damping-factor control circuit to create a dominant pole at the output of the first gain stage; [12] proposes a current feedback scheme to reposition an internal pole based on the load current; [37] proposes a topology that is automatically configured as a two-stage or three-stage feedback depending on the load current; and [14], [36], [38] use some forms of the nested Miller compensation to progressively reposition the open-loop poles/zeros without degrading the DC loop gain. However, the aforementioned LDOs are still not quite suitable for our application because they: i) still require quite a sizable minimum load current which often increases as the load capacitance increases ( [14], [34]); ii) sacrifice the loop gains at a certain ranges of the load current ( [12], [37]) to ensure stability, which hurts the load/line regulations; iii) require a very large on-chip compensation capacitance to ensure stability ( [36]).
In this work, we propose the design of a three-stage OCL-LDO capable of operating over wide ranges of load current (0-100 mA) and load capacitance (0-1 nF under zero load current), while providing very good DC load and line regulations over the entire range of the load current. To stabilize the OCL-LDO while keeping the Q-factor of the complex poles low at all the load conditions, we employ a nested Miller compensation consisting of both the direct and indirect (cascode) feedback paths [39]; the indirect paths are responsible for the normal pole-splitting operation while the direct path helps constrain the Q-factor of the complex poles. In addition, the analysis of three-stage OCL-LDOs employing nested Miller compensation is often very complicated, especially for OCL-LDOs with very wide load-current and load-capacitance ranges. The analyses presented in the literature usually involve solving for the overall closed-loop transfer functions, which are very complicated and lacking the design insights into the roles different circuit components play in stabilizing the OCL-LDO. Hence, in this work, we employ a graphical feedback viewpoint in compensating the OCL-LDO, with the hope of shedding some lights into how to best attempt the design to ensure stability over all the load conditions of interest.
The paper is organized as follow: Section II and III provide an overview of the proposed OCL-LDO's architecture and the detailed mathematical analysis of the indirect-direct nested Miller compensation method; Section IV then applies the result from Section III to graphically visualize the effects of the compensation at various load conditions. Section V then presents the detailed implementation of the OCL-LDO while Section VI and VII validate the proposed design with simulation and experimental results. Finally, Section VIII concludes the paper.

II. OVERVIEW OF THE PROPOSED OCL-LDO
Unlike conventional LDOs with large off-chip capacitors to help stabilize the output voltage during large changes in the load current, OCL-LDOs rely solely on their internal feedback mechanisms to regulate their output voltages. Thus, for fast response to change in the load current, an OCL-LDO is normally designed with a much higher loop bandwidth than those of the conventional LDOs. However, to avoid severe degradation in the loop gain at very high load current while still preserving low dropout voltage, a wide-load-range OCL-LDO normally employs a large power transistor to ensure its operation in the saturation region. Even then, the loop gain still depends quite strongly on the load current as the power transistor's g m r o product, which determines the gain of the output stage, is inversely proportional to the load current. Hence, to achieve a good load/line regulations, it's important to ensure that the EA's gain remains high over the entire load-current range to compensate for the drop in gain of the output stage at high load current. Fig. 2 shows the conceptual diagram of our proposed OCL-LDO. Instead of sacrificing the EA's gain through the current-feedback mechanism [12] or switching between the two and three-stage topologies as the load current changes [37], we choose to keep the proposed OCL-LDO as a three-stage feedback circuit and the gain of its EA high throughout the entire load-current range; as will be explained in Section V, the EA is implemented as a two-stage amplifier, the first gain stage (A 1 ) employing a folded-cascode topology to provide a very high gain while the second gain stage (A 2 ) employing a common-source topology to provide an additional gain. Using the common-source topology with a moderate gain as a second stage also helps separate the very high-impedance output node of the first gain stage from the large parasitic capacitance at the gate of the power transistor, thus extending the OCL-LDO's unity-gain bandwidth. To stabilize the OCL-LDO over the entire load-current and load-capacitance ranges, we employ a nested Miller compensation seen as the minor loop and the major loop in Fig. 2, with the major loop consisting of both an indirect capacitive-feedback path and a direct capacitive feedback path while the minor loop consisting only of an indirect capacitive-feedback path. The details on how such combined feedback scheme helps stabilize the OCL-LDO over the whole load ranges will be provided in Section IV. To help speed up the OCL-LDO's response to abrupt change in the load current without wasting static power, we also incorporate an overshoot reduction circuit, which detects the change of the power transistor's gate voltage to appropriately increase the bias current of the EA, thus temporarily extending the OCL-LDO's overall bandwidth.

III. THE COMBINED INDIRECT-DIRECT FREQUENCY-COMPENSATION METHOD
To achieve a high loop gain over wide load-current and input-voltage ranges, we propose a frequency-compensation scheme shown in Fig. 3-with the overshoot reduction circuit removed to simplify our analysis-in which the three gain stages are explicitly displayed. The error amplifier comprises the first two gain stages, represented as the operational transconductance amplifiers (OTAs) g m1 and g m2 , respectively. The power transistor M p in Fig. 2 comprises the third gain stage, denoted as the OTA g mp in Fig. 3. Shown in Fig. 3 are also two compensation feedback loops: the major loop consisting of the capacitors C c2 and C m and the minor loop consisting of the capacitor C c1 . As will be discussed in Section V, the capacitors C c1 and C c2 form cascode compensation networks, in which their left plates feed to the source terminals of two PMOS transistors within the error amplifier, which help buffer the feedback currents to the output node of the first gain stage-i.e., node V o1 in Fig. 3. We then model the PMOS cascode buffers as the OTAs labelled b 1 g f1 and b 2 g f2 in Fig. 3; each OTA exhibits an effective transconductance of b i g fi and an input resistance of 1/g fi , i ∈ {1, 2}-intuitively, g fi is the source conductance of the respective PMOS transistor while b i , a positive value less than unity, represents the fraction of the fed-back current through C ci that is buffered by the PMOS transistor to the node V o1 . The capacitor C m in the major feedback path is a traditional Miller compensation capacitance whose purpose is to limit the Q-factor of the complex poles resulting from the cascode compensation [40]. Providing a direct feedthrough path from V o1 to V out , the capacitor C m , if its value is too large, may introduce a right-half-plane (RHP) zero in the OCL-LDO's loop transfer function, thus degrading its stability. Therefore, it is important to appropriately choose the value of C m to ensure low Q-factor while avoiding the RHP zero. We will explain using a graphical method how to intuitively determine the values of various circuit components to stabilize the OCL-LDO across the entire load ranges in Section IV.

A. SMALL-SIGNAL MODELLING
Before we develop a small-signal feedback diagram for analyzing the operation of the proposed OCL-LDO in Fig. 3, let's define as the impedances seen into the two current buffers through C c1 and C c2 , respectively, and as the output impedances of the first, second, and third gain stages, respectively. Then, applying the Kirchoff's current law (KCL) at the nodes V o1 , V o2 , and V out yields and respectively. The expressions in (3)-(5) can be directly translated to the block diagram in Fig. 4(a) in which the minor feedback loop is nested inside the major feedback loop. Here, let's make a few simplifications to transform this diagram into a form suitable for our graphical analysis. First, let's consider the effect of VOLUME 10, 2022 the compensation capacitance C m connecting between the node V o1 and V out in Fig. 3. This compensation capacitance introduces the feedthrough current path, with an admittance of sC m , from the node V o1 to the output node V out . Normally, as intuited from the block diagram in Fig. 4(a), such feedthrough path often introduces a right-half-plane (RHP) zero at the frequency at which the magnitude of the sC m term is equal to that of the g m2 (Z o2 Z A1 )g mp term. However, if we make C m small enough and the loaded gain of the second gain stage (g m2 (Z o2 Z A1 )) high enough, we can push the resulting RHP zero to a high enough frequency such that it can be ignored. Our next simplification concerns the term Z L Z A2 1/sC m -i.e., the impedance seen by the output stage. Since the load capacitance C L also includes the parasitic drain capacitance of the large power MOSFET, its value, even with the OCL-LDO's explicit load capacitance excluded, is much larger than the compensation capacitance C c2 (which is a part of Z A2 ). Hence, we can safely conclude that the magnitude of the Z L 1/sC m term is much smaller than that of Z A2 , thus allowing us to approximate Z L Z A2 1/sC m as just Z L 1/sC m . Another simplification that we shall make is to move the feedback path originating from V o2 (of the minor loop) to from V out ; this manipulation requires that we divide the feedback term b 1 /(g m1 Z A1 ) in Fig. 4(a) by the gain from V o2 to V out (−g mp (Z L 1/sC m )). Finally, we denote the unity factor of the major feedback path as a standalone feedback path to arrive at the simplified block diagram in Fig. 4(b). Fig. 4(b) offers three main benefits in understanding the small-signal operation of the OCL-LDO. First, the diagram depicts how the OCL-LDO actually employs feedback to regulate its output V out : it compares V out to the reference voltage V in to produce the error voltage V e = V in − V out , which must be minimized by the high loop gain of the OCL-LDO. Second, the diagram makes evident the roles of different parts of the OCL-LDO in regulating V e : the forward-path transfer function A(s) captures the overall gain of the three gain stages including their loading effects; the feedback-path transfer functions β minor (s) and β major (s) show how the two feedback compensation networks in Fig. 3 provide feedback compensation for the overall OCL-LDO. Finally, the diagram is in a very simple feedback form in which all the feedback paths originating from the output are to be subtracted from the input. With such simple form, the overall loop transfer function of the OCL-LDO is simply To minimize the error signal V e , we must make the magnitude of L(s) large while still keeping the overall feedback loop nicely stable. However, architecting L(s) to achieve good stability margins is often made difficult due to little insights offered from the complicated expression of L(s) if solved directly from (6). Hence, in this work, we resort to the use of a graphical technique to help visualize different components of L(s) such that we can design different components to achieve a satisfactory L(s). To do so, let's start by writing (6) in a more amenable form for our graphical visualization technique: where 1/β(s) = (1/β major (s)) (1/β minor (s)). Since the stability margins of a feedback loop is mostly determined by the behavior of its loop transfer function at the unitygain crossover, our task in the frequency compensation of the OCL-LDO is to architect L(s) such that its unity-gain crossover behavior is close to being first-order. By writing L(s) as a parallel combination of two transfer functions as in (7), we can approximate L(s) by the fact that the transfer function with the lowest magnitude dominates the parallel combination. In other words, by comparing the magnitudes of A(s) and 1/β(s) on the same Bode plot, we can take the lower portions of the two curves to represent the magnitude of L(s), hence obtaining an approximated form of L(s). To proceed with such approach, let's find simple closed-form expressions of A(s) and 1/β(s) for use in our graphical approximation.

B. APPROXIMATION OF A(s) AND 1/β(s) FOR GRAPHICAL ANALYSIS
First, let's start with the forward-path transfer function of Fig. 4 Substituting the expressions of Z A1 , Z o1,2 , and Z L from (1) and (2) into (8), we can explicitly write A(s) as where From (9), A oL represents the overall low-frequency gain of the three gain stages, ω o1 the pole associated with the first gain stage (as introduced by Z o1 ), and ω oL the pole associated with the output node. The poles at ω o2,1 and ω o2,2 and the zero at g f1 /C c1 arise from the impedance Z A1 Z o2 associated with the output node of the second gain stage. In simplifying (8) into (9), we have made an assumption that the two poles of Z A1 Z o2 are real and that ω o2,1 ω o2,2 such that we can approximate ω o2,1 and ω o2,2 as in (10) (see the Appendix).
For our proposed OCL-LDO, the values of ω o1 and ω o2,1 are quite low (well below the unity-gain frequency of A(s)) while the value of ω o2,2 is quite high (often above the unity-gain frequency of A(s)). The value of ω oL , however, varies widely depending on the load condition (C L and I L ). On one extreme, at very low I L (in which R oL becomes large due to the large r o of the power transistor) and very large C L , ω oL becomes the dominant pole of A(s). Such a load condition normally places ω oL , ω o1 , and ω o2,1 below the unity-gain frequency of A(s) while placing the rest of the corner frequencies above it. As a result, A(s) behaves as a third-order transfer function at its unity-gain crossover frequency. On the other extreme, when I L becomes very large such that R oL becomes much smaller, the value of ω oL becomes so large that it is well above the unity-gain frequency of A(s). As a result, only ω o1 and ω o2,1 are below the unity-gain frequency of A(s), making A(s) a second-order transfer function at its unity-gain frequency. Such wide-ranging behavior of A(s) at its unity-gain frequency dictates that, instead of relying on A(s), we must carefully devise 1/β(s) to ensure that the loop transfer function (L(s) in (7)) behave as a first-order transfer function at its unity-gain crossover. Hence, we shall find a simple closed-form expression of 1/β(s) next.
To find 1/β(s), let's write the expressions of 1/β major (s) and 1/β minor (s) as Substituting Z A1 , Z A2 , and Z L from (1) and (2) into (11) and performing some algebraic manipulations, we obtain 1 β major (s) = K major 1 s · 1 + sC c2 /g f2 1 + s/ω major (12) and where In our design, we try to make the zero frequencies of (12) and (13) very close to each other such that we can define ω z = g f1 /C c1 = g f2 /C c2 . In practice, there is inevitably mismatch in the values of the two zeros but, as long as the two zero frequencies are close enough with each other, the errors resulting from such approximation can be thought of as introducing additional singularities at very high frequencies such that, for the purpose of our analysis, they can be ignored. Finally, with the approximation involving ω z , we can derive 1/β(s) as a parallel combination of 1/β major (s) in (12) and 1/β minor (s) in (13) as VOLUME 10, 2022 where

IV. GRAPHICAL COMPENSATION
Having obtained the expressions of A(s) and 1/β(s), we are now ready to graphically compensate L(s) to ensure good stability margins over wide load conditions. Since the load condition directly affects the value of ω oL , we will divide our discussion into three cases based on how the value of ω oL is relative to those of ω o1 and ω o2,1 . As seen from (16), the value of ω oL -along with the circuit parameters determining K major , K minor , and ω major in (14)-will determine the value of ω p relative to that of ω z of 1/β(s) in (15), which, in turn, will determine the behavior of L(s) at its unity-gain crossover frequency and, hence, the OCL-LDO's stability.
A. CASE 1: ω oL < ω o1 , ω o2,1 This case corresponds to when I L is very small while C L very large. The small I L results in a very large R oL which, together with a large C L , makes ω oL in (10) small compared to ω o1 and ω o2,1 . As ω oL , ω o1 , and ω o2,1 are concentrated at low frequencies, the resulting A(s) behaves as a third-order transfer function at its unity-gain frequency (ω cA ), making the frequency compensation of the OCL-LDO quite challenging. Fig. 5 shows the asymptotic Bode magnitude plots of A(s) and 1/β(s) to help visualize L(s) in which we have assumed that the magnitude of 1/β(s) is much lower than that of A(s) for frequencies lower than where the two curves intersect (ω ist ). Therefore, for ω < ω ist , we can assume that L(s) ≈ 1/β(s). We have also assumed, from (16), that the small ω oL results in ω p being lower than ω z , and that ω oL is so low that it makes ω p smaller than ω c , the unity-gain frequency of L(s). Ideally, to provide the OCL-LDO with a good phase margin, we should make ω p as large as possible, preferably larger than ω c , such that L(s) behaves as a first-order transfer function at its unity-gain frequency. Fortunately, despite the low ω oL imposed by the load condition, the value of ω p can be indeed much larger than ω oL , the reason of which can be explained using (16). Since ω major from (14) is itself already much larger than ω oL -as g f2 1/R oL and C m C Lwhat determines the value of ω p is usually the ω oL term of the parallel combination in (16). As low I L makes g mp R oL large, we can see from (14) that K minor should be much larger than K major . Therefore, ω oL in (16) is multiplied by 1 + K minor /K major , a factor much larger than 1, before coming in parallel with the ω major term, resulting in ω p that is much larger than ω oL . However, with a severe load condition-in which I L becomes very low and C L very large-the very low ω oL may result in ω p that is lower than ω c as depicted in Fig. 5, resulting in L(s) with a second-order unity-gain crossover behavior and a poor phase margin. In such case, the left-half-plane zero at ω z of 1/β(s) can help alleviate the degradation of the phase margin somewhat as it contributes positive phase to L(s) at ω c . With the help of such zero, the proposed OCL-LDO may still be functional even while providing a very low load current and driving a large load capacitance as will be demonstrated in Section VI-A.
B. CASE 2: ω o1 , ω o2,1 < ω oL < ω cA Now we consider the case of intermediate I L and C L , which makes the value of ω oL only a little higher than ω o1 and ω o2,1 . As I L is not very high, ω oL is still smaller than ω cA , the unity-gain frequency of A(s), making A(s) still a third-order transfer function at its unity-gain crossover. Nevertheless, since the value of ω oL in this case is much larger than that in case 1, the ω oL term in (16) is no longer a limiting factor of ω p . As a result, ω p is pushed to a frequency higher than the unity-gain frequency (ω c ) and the zero frequency (ω z ) of 1/β(s). As will be discussed next, how high ω p is relative to ω z also affects the overall stability of the OCL-LDO, which, fortunately, can be controlled by a careful choice of the capacitance value C m . To understand this aspect, let's consider the plots of |A(jω)|, |1/β(jω)|, and the resulting |L(jω)| for two cases of ω p (relative to ω ist , the frequency of intersection between |A(jω)| and |1/β(jω)|): 1) Fig. 6(a) for ω p < ω ist and 2) Fig. 6(b) for ω p > ω ist .
For both cases, the relatively high value of ω p guarantees that L(s) behaves as a first-order transfer function at its unitygain frequency, thus ensuring a good phase margin. However, for this load condition, what determines the OCL-LDO's stability is no longer the phase margin, but the gain margin as determined by the magnitude peaking due to the high-Q complex poles of L(s) near ω ist . We can intuit on this statement graphically by noticing the slopes of |A(jω)| and |1/β(jω)| at ω ist . In Fig. 6(a) in which ω p < ω ist , depending on the slope of |A(jω)| at the intersection, the slope of |L(jω)| may either change from −20 dB/decade to −40 dB/decade if ω o2,2 > ω ist , or from −20 dB/decade to −60 dB/decade if ω o2,2 < ω ist (this case is illustrated in Fig. 6(a)). In the first case, we can intuit that, as the change in the |L(jω)|'s slope at ω ist is only −20 dB/decade, there should be only one real pole there and, hence, no magnitude peaking in |L(jω)| near ω ist . In the second case, however, the change in the |L(jω)|'s slope at ω ist is −40 dB/dec, indicating that there are complex poles and, hence, there can be magnitude peaking in |L(jω)| near ω ist . However, if ω p is made much smaller than ω ist , the value of |L(jω)| at ω ist , despite the possible presence of magnitude peaking, can be made much less than 1, and a good gain margin for L(s) can be guaranteed. On the contrary, if ω p > ω ist as in Fig. 6(b), the change in the |L(jω)|'s slope is either −40 dB/decade or −60 dB/decade depending on the relative position of ω o2,2 to ω ist , hence, indicating the presence of high-Q complex poles around ω ist . What makes this case worse than when ω p < ω ist is that the value of |L(jω)| near ω ist can be quite close to unity (as it has not yet been attenuated by the pole at ω p ). As a result, any magnitude peaking near ω ist can severely degrade the gain margin of L(s) or even cause the OCL-LDO to go unstable.
To reduce the Q of the complex poles near ω ist -hence, improving the gain margin-we can incorporate the direct compensation path as provided by the capacitor C m shown in Fig. 3. To understand the effect of C m in reducing the Q, we shall resort to the root-locus technique to help visualize how the poles of L(s) arise from the open-loop transfer function of the compensation feedback loop-i.e., L fc (s) = A(s)β(s). From the expression of A(s) in (9) (with g f1 /C c1 ≡ ω z ) and β(s) as the inverse of (15), we can write We can see from (17) that L fc (s) has four left-half-plane poles and two zeros, one at the origin and the other at s = −ω p . For this intermediate I L and C L case, we shall assume that ω o1 < ω o2,1 < ω oL while ω o2,2 and ω p are above these pole frequencies.
Since the closed-loop poles of the feedback compensation loop (whose loop transfer function is L fc (s)) are the poles of the OCL-LDO's loop transfer function L(s), we can use the root-locus technique to illustrate how the position of the zero at s = −ω p , which is affected by C m , relative to that of the pole at s = −ω o2,2 affects the Q of the complex poles of L(s). First, let's consider the scenario in which C m is very small, which makes the value of ω major in (14) very large, thus allowing us to approximate ω p in (16) as ω p ≈ ω oL (1 + K minor /K major ). For this intermediate I L case, the value of g mp R oL is still much larger than 1, thus resulting in K minor K major as suggested in (14). In addition, a relatively large I L , which results in a relatively small R oL , makes ω oL quite substantial compared to ω o2,2 . These combined effects, as seen from (16), result in ω p being significantly larger than ω o2,2 -i.e., the Bode plot of Fig. 6(b). Fig. 7(a) shows the root-locus plot of L fc (s) in this case as its DC loop gain (A oL / K major K minor ) increases. We can see in this plot that the zero at the origin attracts the closed-loop pole originating from s = −ω o1 toward it while the closed-loop poles originating from s = −ω o2,1 and s = −ω oL move toward each other and break off the real axis to become complex. Also, the zero at s = −ω p , which situates at a much higher frequency than the pole at s = −ω o2,2 , attracted the closed-loop pole originating from s = −ω o2,2 toward it. Hence, from the average-distance rule of the root-locus technique, such leftward movement of the pole has an effect of pushing the two complex poles toward the right half of the complex plane. In severe circumstances in which the loop gain of L fc (s) is sufficiently high, it is possible that the complex poles be pushed into the right half of the complex plane, making the overall OCL-LDO unstable.  After seeing how the movement of the closed-loop pole originating from s = −ω o2,2 affects the complex poles' Q, we can envision that by forcing such movement to be left-toright instead of right-to-left as in the ω p > ω o2,2 case, we can thwart the rightward movement of the complex poles, thus reducing their Q. Fig. 7(b) shows the root-locus plot of L fc (s) for such concept-here, ω p < ω o2,2 , which corresponds to the Bode plot of Fig. 6(a). Instead of moving to the left as in the case of ω p > ω o2,2 , the closed-loop pole originating from s = −ω o2,2 must move rightward toward the zero at s = −ω p . From the average-distance rule of the root-locus technique, such rightward movement of the closed-loop pole helps pull the complex poles away from the jω axis, thus reducing their Q.
In summary, we can help limit the Q of the complex poles of the OCL-LDO's loop transfer function, L(s), by ensuring that ω p < ω o2,2 . This can be achieved by a selection of a sufficiently large C m such that, even in the case when ω oL term in (16) becomes very large due to a large I L , the ω major term in (16) still helps limit ω p to a value smaller than ω o2,2 . C. CASE 3: ω oL ω o1 , ω o2,1 , ω cA This case corresponds to when I L becomes very large, making R oL very small, which results in ω oL becoming so large that it can be ignored from our analysis. Fig. 8 shows the Bode magnitude plots for estimating L(s) of this load condition. Due to the large ω oL , ω p , as seen from (16), is pushed to a frequency higher than ω c , making L(s) behave as a 1 storder transfer function at its unity-gain crossover frequency, hence achieving a good phase margin. To ensure the stability of the feedback compensation loop for the load condition in Case 2, we will assume that the value of C m is chosen such that ω p < ω o2,2 .
Whether the load condition for this very high I L case risks the presence of high-Q complex poles can be seen from the behavior of L(s) at ω ist where the curves |A(jω)| and |1/β(jω)| intersect. If the difference in the slopes of both curves at ω ist is only 20 dB/decade, it can be approximated that L(s) exhibits one real pole near ω ist , without the presence of high-Q complex poles. Assuming that ω ist > ω c , we can reason from the plot in Fig. 8 that, due to both A(s) and 1/β(s) containing a zero at ω z , the difference in the slopes of |A(jω)| and |1/β(jω)| at ω = ω ist is always 20 dB/decade, regardless of where ω ist is relative to ω z . For instance, if |A(jω)| intersects with |1/β(jω)| before ω z (ω ist < ω z ), the slopes of |A(jω)| and |1/β(jω)| at ω ist are −40 dB/decade and −20 dB/decade, respectively, making the slope of |L(jω)| change by only 20 dB/decade at ω ist . On the other hand, if |A(jω)| intersects with |1/β(jω)| after ω z but before ω p (ω z < ω ist < ω p ), the slopes of |A(jω)| and |1/β(jω)| at ω ist are −20 dB/decade and 0 dB/decade, respectively. Again, the change in the slope of |L(jω)| in this case is also only 20 dB/decade. It can also be reasoned that, for ω ist > ω p , the change in the slope of |L(jω)| around ω = ω ist is also 20 dB/decade. Therefore, for this very high I L case, there are no high-Q complex poles and, thus, no magnitude peaking in |L(jω)| near ω = ω ist . The compensation feedback is thus firmly stable and the overall OCL-LDO should exhibit a good gain margin. Fig. 9 shows the transistor-level implementation of the proposed OCL-LDO. Illustrated as g m1 , R o1 , and C o1 in Fig. 3, the first gain stage is implemented as a folded-cascode operational amplifier (OTA) consisting of the transistors M 0 -M 8 , with M 1 and M 2 acting as the input differential pair. The second gain stage-illustrated as g m2 , R o2 , and C o2 in Fig. 3-is implemented as a moderate-gain common-source stage (M 11 and M 12 ) with the transistors M 9 and M 10 providing voltage inversion from the output of the first gain stage to the gate of M 11 . Finally, the power stage-g mp and R oL in Fig. 3consists of the power transistor M p to provide the required current to the load. The capacitor C c1 acts as a minor-loop compensation capacitance that senses the voltage at the drains of M 11 and M 12 (node V o2 in Fig. 3) and returns current to the source of the transistor M 5 . Hence, M 5 acts as a current buffer (the b 1 g f1 buffer in Fig. 3) to prevent the feedthrough current through C c1 from the node V o1 to the node V o2 -which otherwise might cause a low-frequency RHP zero. Similarly, the capacitor C c2 acts as a major-loop compensation capacitance, sensing the voltage at V out and returning the feedback current to the node V o1 via the source of the transistor M 6 -hence, M 6 acts as a current buffer b 2 g f2 in Fig. 3. The capacitor C m connects directly between the node V out and V o1 to help limit the Q of the L(s)'s complex poles when the load current becomes large.

V. CIRCUIT IMPLEMENTATION
To speed up the OCL-LDO's settling time when the load current undergoes abrupt changes, we have incorporated an overshoot/undershoot reduction circuit, which consists of the transistors M b1 -M b4 , M c1 -M c5 , and the passive highpass networks formed by R B1 , C B1 and R B2 , C B2 . When the load current abruptly changes, the feedback operation of the OCL-LDO results in an abrupt change in the gate voltage of the power transistor M p . The two highpass networks then sense this abrupt change and dynamically increase the bias current of the first gain stage-i.e., to increase its transconductance, g m1 -to speed up the OCL-LDO. The dynamic increase in the first gain stage's bias current is achieved through two sets of the bias transistors: i) M b1 -M b3 and ii) M c1 -M c3 , all of which biased to consume negligible drain currents during the OCL-LDO's normal operation. The first set, M b1 -M b3 , helps increase the bias current when the load current abruptly decreases while the second set, M c1 -M c3 , helps when it abruptly increases. First, let's consider the scenario when the load current abruptly decreases, which results in a sudden increase of the M p 's gate voltage to reduce its drain current to balance with the reduced load current. The sudden increase in the M p 's gate voltage couples through the highpass network formed by C B1 and R B1 , raising the gate voltage of M b4 (the node V Bx ), which, in turn, increases the drain currents of the transistors M b1 -M b3 to increase the bias current of the first gain stage. In the opposite scenario in which the load current suddenly increases, the OCL-LDO's feedback operation cause the M p 's gate voltage to drop; such sudden voltage drop couples to the gate of M c4 through the highpass network C B2 and R B2 , thus increasing the drain currents of M c4 and M c5 , which is mirrored to M c1 -M c3 to increase the bias current of the first gain stage. Table 1 summarizes the sizes and quiescent currents of all the transistors along with the sizes of the passive components used in the OCL-LDO of Fig. 9.

VI. SIMULATION RESULTS
In this section, we verify the feasibility of our theoretical analyses in Section IV with the stability analyses in SPICE for all the three load conditions. First, we extracted the relevant DC-operating-point parameters of our OCL-LDO in Fig. 9, and used them to calculate A(s) and 1/β(s) as given in (9) and (15) for different sets of I L and C L , with I L ranging from 0 mA to 100 mA and C L from 0 to 1 nF. Once obtained, A(s) and 1/β(s) were used to calculate L(s) in (7), which was then compared to that obtained from the stability analysis in SPICE. A. CASE 1: ω oL < ω o1 , ω o2,1 First, we shall focus on the loading scenarios with extremely low I L and very high C L -i.e., the most difficult condition to compensate. We shall consider two scenarios, both with I L = 0, but one with C L = 200 pF and the other with C L = 1 nF. Fig. 10(a) and Fig. 10(b) show the Bode magnitude plots of L(s) obtained from our theoretical model ( L theory (jω) , red curve) and from SPICE stability analysis (|L CAD (jω)|, blue curve) for C L = 200 pF and 1 nF, respectively. In the two figures are also shown the Bode magnitude plots of A(s) and 1/β(s) used in calculating L theory (s). All the corner frequencies are marked in Hertz-as f i = ω i /(2π)-instead of in rad/sec as in Section IV. Both Fig. 10(a) and Fig. 10(b) clearly show that L theory (jω) closely matches |L CAD (jω)| up to a frequency close to f o2,2 , which is well beyond the unity-gain frequency f c .
In Fig. 10(a) with C L = 200 pF, we have f oL = 11 kHz, which is below both f o1 (15.8 kHz) and f o2,1 (211 kHz), making A(s) a third-order transfer function at its unity-gain crossover frequency. Nevertheless, with the help of both compensation networks, 1/β(s) exhibits a first-order behavior over a wide frequency range. The 1/β(s)'s pole at f p occurs at 367 kHz, well above f oL and just slightly below the unity-gain frequency f c = 474 kHz. In theory, the left-half-plane zero at f z = 1.89 MHz helps introduce a positive phase shift of 14 • to the theoretical L(s) at f = f c , resulting in the theoretical phase margin of 39.43 • . Nevertheless, SPICE simulation indicates that the pole at f p of L CAD (s) occurs beyond its unity-gain frequency, making L CAD (s) a first-order transfer function at its unity-gain crossover. As a result, for I L = 0 and C L = 200 pF, SPICE stability analysis indicates the phase margin of 42.76 • , slightly more than predicted by our theoretical model.
To consider the stability limit of the proposed compensation method, let's turn our attention to the case of I L = 0 and C L = 1 nF, whose Bode magnitude plots are shown in Fig. 10(b). Under such severe load condition, f oL is pushed to 1.59 kHz, which is several times lower than its value when C L = 200 pF, while f o1 and f o2,1 remain the same. Nevertheless, A(s) still behaves as a third-order transfer function at its unity-gain crossover frequency. Now, let's consider how such large C L affects f p , the pole frequency of L theory (s). From the plot, we can see that f p , originally at 367 kHz when C L = 200 pF, now drops to 79.6 kHz, which is 2.92 times lower than the unity-gain frequency f c (233 kHz).
As a result, L theory (s) is now strictly second-order at its unitygain crossover frequency, indicating a poor phase margin. Even then, our theoretical model suggests that the zero at f z = 1.89 MHz introduces a positive phase shift of around 7.02 • to L theory (s) at f c , which results in a theoretical phase margin of 18.56 • . Nevertheless, comparing |L CAD (jω)| to L theory (jω) , we observe that L CAD (s) behaves as a first-order transfer function over a slightly wider frequency range, suggesting that f p of L CAD (s) is at a slightly higher frequency than that of L theory (s). As a result, SPICE stability analysis indicates a slightly better phase margin of 27.46 • for this load condition.
Though it may seem that the phase margin of 27.46 • is very low, as judged from generally acceptable criteria in circuit design, it should be noted that such large capacitive load under zero load current is very unlikely to occur in practice because a very large load capacitance is normally associated with heavy circuitry being powered by the OCL-LDO. Even if the circuitry being powered is idle, its leakage current alone should be sizeable such that I L should be significantly higher than zero. Nevertheless, we will shown in Section VII that our OCL-LDO is still stable even with I L = 0 mA and C L = 1 nF.
B. CASE 2: ω o1 , ω o2,1 < ω oL < ω cA As discussed in Section IV-B, our concern for this load condition is the possible presence of high-Q complex poles near f ist where |A(jω)| and |1/β(jω)| intersect. Hence, a capacitor C m is needed to limit the Q of the complex poles to guarantee a good gain margin for the OCL-LDO's loop transfer function L(s).
For an illustration, let's consider the scenario in which I L = 35 mA and C L = 100 pF, whose Bode magnitude plots are shown in Fig. 11. Due to the high load current and the relatively small load capacitance, f oL is now at 1.26 MHz, now higher than f o1 (16.6 kHz) and f o2,1 (222 kHz) but still lower than the unity-gain frequency of A(s), making it still a third-order transfer function at its unity-gain crossover as in Case 1. Even then, the now higher f oL pushes f p (the pole frequency of 1/β(s), which is now at 4.33 MHz) to a frequency higher than both f c (662.5 kHz) and f z (2.97 MHz). Hence, the OCL-LDO's loop transfer function-as seen in both L theory (s) and L CAD (s)-crosses over the unity-gain level in a first-order fashion, thus guaranteeing a good phase margin. Notice that even when f oL = 1.26 MHz is much higher than its value in Case 1, the value of f p = 4.33 MHz is only slightly higher than f z = 2.97 MHz, thanks to the role of C m in limiting the value of ω p as discussed in Section IV-B. Also, recall from the root-locus plot of Fig. 7(b) that making ω p < ω o2,2 has a desirable effect of directing the complex poles of L(s) leftward in the complex plane, hence reducing their Q. In this design, we have chosen C m to be 750 fF to ensure that f p is always smaller than f o2,2 for all the load conditions of interest. Fig. 11 illustrates that the SPICE-simulated loop transfer function, L CAD (s), follows our theoretical model, L theory (s), very closely over a very wide frequency range (up to f ist ), and that both transfer functions exhibit no magnitude peaking near f ist , thanks to the Q-limiting effect of C m . The SPICE-simulated phase and gain margins for this particular load condition are 84 • and 20 dB, respectively, indicating that the OCL-LDO is well stabilized. If C m is removed, however, the SPICE-simulated loop transfer function, L CAD (s) (C m = 0), exhibits a very high magnitude peaking near f ist . Please also note that the magnitude of L CAD (s) for C m = 0 is slightly higher than when C m = 750 fF as the absence of C m increases the value of K major as indicated in (14). For this particular load condition, the peaking near f ist is so high that |L CAD (jω)(C m = 0)| at its peak almost exceeds unity, indicating that the gain margin is so low and that the feedback compensation loop is close to being unstable.

VII. EXPERIMENTAL RESULTS
The proposed OCL-LDO was designed and fabricated in a 0.18-µm CMOS process from the United Microelectronic Corp. (UMC). Fig. 13 shows the die micrograph of the OCL-LDO, which occupies an area of 310 µm × 350 µm. For any load current between 0 mA to 100 mA, the OCL-LDO is stable under the load capacitance up to 1 nF, while capable of regulating the output voltage in the range of 1 V to 2.2 V and consuming a total quiescent current of 14 µA. For a larger load current of higher than 1 mA, the OCL-LDO is stable even under the load capacitance of as high as 10 nF. The OCL-LDO employs a total of 5.45 pF for all the on-chip capacitors (C c1 , C c2 , C m , C B1 , and C B2 in Fig. 9) and a total of 1 M for all the on-chip resistors (R B1 and R B2 ).
To validate the proposed OCL-LDO's performance, we have built on a printed circuit board (PCB) a testbench, whose schematic is shown in Fig. 14(a); the proposed OCL-LDO is shown as the combination of the error amplifier (EA) and the power stage (M p and the resistor R L ). To facilitate the measurements of the line regulation and power supply rejection (PSR), we have built on the PCB the supply-generation circuit-consisting of the low-noise high-output-drive opamp (THS3120ID, Texas Instruments Inc.) and a few passive components-to allow superimposing an AC signal (V in,AC ) on top of a large-signal component (V in,DC ) in generating the supply voltage V in . Measuring the PSR of the OCL-LDO can then be performed by determining the small-signal transfer function from V in,AC to the OCL-LDO's output, V out . In addition, by leaving V in,AC opened, we can perform DC sweep on or provide abrupt change to V in,DC to measure the OCL-LDO's line regulation or evaluate its transient behavior, respectively.
To evaluate the effects of the load conditions on the OCL-LDO, we have connected to its output node (V out ) an off-chip load capacitance C L and a voltage-controlled current source built from a high-speed FET-input opamp (AD8065ARZ, Analog Devices Inc.) and a bipolar-junction transistor (MMBT6428, Fairchild Semiconductor). The current source provides the load current I L to the OCL-LDO, whose value is controlled by the current source's input voltage, V cur,cont , according to the relationship I L ≈ V cur,cont /10 . Also connected to the OCL-LDO's output is a voltage buffer, built from a high-speed operational amplifier (OPA355UA, Texas Instrument Inc.), to help mitigate the loading effect while observing the transient voltage at V out .

A. TRANSIENT RESPONSES TO ABRUPT CHANGES IN THE LOAD CURRENT AND THE LINE VOLTAGE
For this part, we demonstrate the OCL-LDO's performance in handling abrupt changes in the load current. We tested the OCL-LDO under four input-voltage and capacitive-load  Fig. 15(a) shows the OCL-LDO's responses for both values of C L when V in is set to 1.2 V. At the positive transition of I L , the response exhibits voltage undershoots of 234 mV and 245 mV for C L = 0 and C L = 1 nF, respectively. Conversely, the negative transition of I L produces, for C L = 0 and C L = 1 nF, the voltage overshoots of 50 mV and 48.8 mV, respectively. Fig. 15(b) shows the OCL-LDO's responses when V in is set   The plots of Fig. 15(a) and Fig. 15(b) clearly demonstrate that the steady-state value of V out rarely changes even when the change in I L is drastic, thus indicating that the proposed OCL-LDO achieves a very good DC load regulation. These plots also demonstrate that the proposed OCL-LDO is stable with C L = 1 nF even under the zero-load-current condition. However, we shall treat this case as the very worst-case condition because, as discussed in Sections I and VI-A, a large load capacitance should correspond to a sizable load current. To see how much load capacitance our OCL-LDO can handle under a sizable load current, we performed an experiment similar to that producing Fig. 15(a) but with C L = 10 nF and I L transitioning between 1 mA and 100 mA. The result is shown in Fig. 16. Though exhibiting some ringing on both transitions, the response clearly shows that, with the load current of at least 1 mA, the OCL-LDO is stable even under a load capacitance of as high as 10 nF.
Next, we demonstrate the OCL-LDO's performance under abrupt changes in the line voltage V in . For these experiments, we set V ref to 1 V while altering V in between 1.2 V and 2.4 V with the edge times of 10 µs for both the positive and negative transitions. The value of C L is set to 0 F as this capacitive-load condition provides the worst line-transient performance as there is no C L to help attenuate the coupling from V in . The middle and bottom panes of Fig. 17 show the OCL-LDO's response when I L is set to 0 mA and 1 mA, respectively. We can see from these responses that the OCL-LDO exhibits similar voltage overshoots and undershoots under both values of I L . However, under I L = 0 mA, the OCL-LDO's response exhibits higher amount of ringing when V in makes the negative transition, probably due to the OCL-LDO's smaller phase margin at very low load current.
In summary, the transient responses of Fig. 15(a), Fig. 15(b), and Fig. 17 confirm that the OCL-LDO is well stabilized across the entire ranges of input voltage (1.2-2.4 V), load current (0-100 mA), and load capacitance (0-1 nF)-and Fig. 16 shows that it is also stable even under C L = 10 nF if I L remains higher than 1 mA-without the need for adapting the topology of the gain stages to sacrifice the loop gain. As a result, the OCL-LDO's loop gain can be preserved across all the load/input-voltage conditions, which would contribute to excellent load/line regulation performances as will be demonstrated next.

B. LOAD/LINE REGULATIONS AND POWER SUPPLY REJECTION
In this part, we demonstrate the load/line regulation and power-supply-rejection performances of the proposed OCL-LDO. Fig. 18(a) shows, at the two extremes of the input  voltage V in , the deviation of the OCL-LDO's output voltage from the no-load value (V out (I L ) − V out (I L = 0)) as the load current varies from 0 mA to 100 mA-for both curves, V ref is set 200 mV below V in to provide a dropout voltage of 200 mV across the power transistor. The load regulations for both values of V in appear to be quite similar, but the worst-case value over the entire load-current range happens to be 0.025 mV/mA as calculated from the curve with V in = 2.4 V. For the line regulation, Fig. 18(b) shows the deviation of the OCL-LDO's output voltage as we varied V in from 1.2 V to 2.4 V (V out (V in ) − V out (V in = 1.2 V)). For this curve, we set I L to 100 mA to achieve the worst-case line regulation performance as large I L drives the power transistor into the linear region such that V in has maximal effect on V out . As V in varies, the reference voltage V ref remains at 1 V. Calculating the line regulation from this curve over the entire range of V in yields the value of 0.5 mV/V. Fig. 19 shows the power supply rejection (PSR) of the proposed OCL-LDO at various load currents I L . For most values of I L , the PSR at 1 kHz ranges from −50 dB to −55 dB. At I L = 100 mA, however, the PSR at 1 kHz drops to −43 dB due to the power transistor being forced to operate in the linear region. Table 2 summarizes the performance of the proposed OCL-LDO compared to those of the previous works. Though implemented in a much larger technology node while utilizing approximately the same quiescent current, the proposed OCL-LDO exhibits the settling time on the same order as those in [13], [37], [41]. Those achieving much better settling times are mostly regulators implemented in smaller technology nodes which also utilizes significantly higher quiescent currents ( [12], [14], [16]), except for the work in [15] which is also implemented in a 0.18-µm CMOS process while utilizing a smaller quiescent current. However, compared to the OCL-LDO in [15], which requires a minimum load current of 1 mA to be stable and is capable of driving capacitive load only in the range of 0-100 pF, the proposed OCL-LDO is stable under a much wider capacitive load range (0-1 nF) even with the load current being zero; the OCL-LDO is also stable while driving capacitive load of up to 10 nF for a guaranteed minimum load current of at least 1 mA. In addition, thanks to the proposed compensation methodology, which maintains the high loop gain over a very wide load-current range, the proposed OCL-LDO achieves the best DC load and line regulations compared to the previous works.

VIII. CONCLUSION
In this paper, we have presented the design of an OCL-LDO capable of driving a very wide range of load capacitance and supplying a wide range of load current while maintaining excellent DC load and line regulations. Good DC regulation performances are achieved through the combined indirect-direct nested Miller compensation method which allows the preservation of the loop gain throughout the entire load-capacitance and load-current ranges. To provide insights into the working of the proposed compensation scheme, we employ a graphical feedback technique to help visualize how stability is achieved at various load conditions. Due to its low quiescent current, good DC regulation performance, and wide load-current and load-capacitance ranges, the OCL-LDO is suitable for SoCs whose loads undergo drastic changes throughout their entire operations such as those employing wakeup and power-gating schemes.