Fully-Integrated Timers for Ultra-Low-Power Internet-of-Things Nodes – Fundamentals and Design Techniques

Driven by the momentum toward compact and low-power Internet-of-Things (IoT) systems, the research on fully-integrated and energy-efficient kHz-to-MHz timers increased explosively. This article examines recent publications on timers and classifies them into two major categories: open-loop-based and close-loop-based timers. Upon introducing the basic parameters for characterizing a timer, we perform an extensive investigation to gain insights into recent state-of-the-art works. We also discuss in detail the comparison between the two classes of timers. With the aid of the state-of-the-art, we present a comprehensive review from multiple perspectives, such as Energy Efficiency, Temperature Coefficient, Temperature Range, Figure-of-Merit, etc.


I. INTRODUCTION
Compact wireless systems experienced massive growth in emerging microsystems that benefit many applications, such as healthcare monitoring, environmental investigation, and smart sensors [1,2]. Lifetime and power consumptions constraints of the different blocks within the System-on-Chip (SoC) solution are the major bottlenecks to further promote the deployment of wireless systems [3]. The well-known duty-cycling technique minimizes the power consumption of the power-hungry radio. Allowing the system to alternate between sleep and active mode periodically, significantly reduces the total power consumption. Therefore, an accurate timer to precisely wake up the radio is compulsory. As there is no synchronization between the radio and the master device in the idle state, the frequency accuracy of the timer amid environmental variations (e.g., supply voltage and temperature variation) is decisive. Also, since the timer is oscillator and ring oscillator) and close-loop-based timer (e.g., frequency-locked loop, FLL), as depicted in Fig. 1. For an open-loop-based timer, the oscillator operates in a freerunning mode. The closed-loop-based timer also consists of an oscillator to generate the oscillation signals, however, it has its frequency locked by another timing element (e.g., RCnetwork in the FLL). Theoretically, the periods of the oscillations for both type of timers solely depend on the desired circuit elements (i.e. resistor, capacitor, voltage reference, etc.). Yet, Process, Voltage, and Temperature (PVT) variation influence the frequency stability of the oscillator. For instance, considering the relaxation oscillator illustrated in Fig. 1(a), ideally, the output signal OUT ought to toggle once VIN > VREF. Yet, the delay of the comparator and the logic gates contributes in prolonging the clock period. In addition, as the delay changes amid PVT variation, it aggravates the frequency stability of the timer. This article reviews the fundamentals of designing the fully-integrated timers as wakeup timer for ULP IoT nodes, particularly in a CMOS process. Section II introduces the essential parameters to characterize the timer. Section III describes a review of recent architectures based on two types of design topology: open-loop-based and close-loop-based timers. Section IV compares the design of open-loop-based and close-loop-based timers from different perspectives, performance summary and tradeoffs with recently reported publications. Section V concludes this review.

II. ESSENTIAL PARAMETERS OF TIMERS
It is crucial to discuss the parameters to characterize the performance of the timer. In this section, several common performance parameters in benchmarking the timers are elaborated.

A. JITTER AND PHASE NOISE
The goal of a timer is to generate a stable reference timing. Ideally, the timer provides the oscillating signals with identical periods in every cycle. Due to the presence of noise  ωo ω ω ωo from the circuits, the period deviates from its ideal value. As shown in Fig. 2, the signal's period exhibits a perturbation every cycle (ΔT1, ΔT2, ΔT3, etc.). This perturbation is known as absolute jitter, which is the difference between the ideal period and the measured period of a clock cycle. Practically, it is improbable to obtain the ideal period as it is unknown. As such, the parameter Period jitter can be utilized, which portrays the difference in the measured period of a clock cycle and the average period of multiple clock cycles. The period jitter can be characterized by root-mean-square or peak-to-peak value to manifest the clock's performance.
On the other hand, the clock's jitter incurs phase diffusion to the signal. Hence, the spectrum of the clock spreads around ωo, as shown in Fig. 3 [15]. Such perturbation is known as phase noise. To understand phase noise, we must observe the Power Spectral Density (PSD) of the timer around the oscillating frequency (fo) (Fig. 4). Interestingly, the PSD of the timer correlates to the PSD of the jitter. The PSD of jitter can be determined as [16] where f is the offset from fo. With (1), we can obtain the phase noise of the timer where n is the number of harmonics. The relationship between the RMS absolute jitter and the phase noise is expressed as where σa is the RMS absolute jitter. Note that the upper limit of the integration is 2 ⁄ to prevent double count of the phase noise around the 2 nd harmonic, whereas the lower limit fmin is usually determined by the observation time.

B. ALLAN DEVIATION
For duty-cycling purposes, the timer is turned on for a relatively long period. The timer output will be counted continuously. Hence, the period jitter of each individual cycle is averaged out and it is inadequate to show the performance of the timer over an extended integration time. In this regard, the Allan deviation, which measures the longterm stability of the oscillator, is a more appropriate indicator. The Allan deviation characterizes the frequency stability of the oscillator over a timespan of τ. It depicts the expected timing deviation between two subsequent sleeping periods of the duration τ [17].
To understand Allan deviation, we must first define y(t) as a normalized, fractional frequency of the timer from the nominal frequency fo. It can be expressed as [18] where f(t) is the oscillating frequency at time t and ( ) is the instantaneous phase fluctuation. From [19], the Allan variance is determined as . Relation between voltage spectrum and PSD of timer [16] Phase Noise Phase Noise Integration Limit [16] Averaging Time (s) Allan Deviation (ppm) 1/2 Allan Floor This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.
Note that, τo is the data sampling or measurement interval for the timer, while τ (also known as observation interval) is the analysis or average time taken for the measurement and is commonly expressed as a multiple of τo ( = , where n is the averaging factor). Finally, the definition of Allan deviation is expressed as the square root of Allan variance ( ) = ( ). Fig. 6 exemplifies the typical profile of Allan deviation of a timer. For a short gating time, the Allan deviation decreases at a rate of √ as the period jitter is averaged out. Subsequently, the Allan deviation will reach a minimum due to the presence of the 1/f-noise. As the power of the 1/f-noise increases with decreasing frequency, extending τ ceases to improve the Allan deviation. This lower bound is called Allan noise floor. If we keep increasing τ, the Allan deviation increases due to temperature and environmental effects as part of the drift process [13].

C. FREQUENCY DEVIATION
Apart from the noise, the oscillator's frequency is also affected by the PVT-variation. While the process variation can be trimmed and calibrated after fabrication, the variations due to voltage and temperature exist throughout the operation.
The perturbation in the supply voltage affects the frequency stability of the timer. For instance, for the circuit in Fig. 1(a), ideally, the output will be flipped once VIN > VREF. Section I highlights that the delay from the comparators and logic gates extends the periods. Normally, the delay of the logic gates is inversely proportional to its supply voltage. Hence, the frequency of the timer tends to shift with the supply voltage. The frequency deviation caused by the voltage variation is characterized as line sensitivity, which is defined as the fraction of frequency variation per volt.
Similarly, the frequency of the timer deviates amid temperature variations [20]. Primarily, the deviation is due to the temperature dependence of resistors and transistors. Consider the circuit in Fig. 1(a) again, where the resistance R changes with temperature. Hence, even with an ideal IREF, VREF = R·IREF drifts, thereby affecting the frequency accuracy. The frequency deviation caused by temperature variation is characterized as temperature coefficient (TC), which depicts the ratio of fractional change in frequency to the temperature range. Usually, the TC is reported in the unit of part per million per degree Celsius, or ppm/°C.

D. FIGURE-OF-MERIT (FoM)
Figure-of-Merit (FoM) is a numerical indicator for any system to express its performance and efficiency. There are several FoM for timer benchmarking. One of the most commonly used FoM in regards to the phase noise and power consumption is expressed as [21]: where Δf is the offset frequency and P is power consumption. However, FoM1 does not consider the timer's stability within the operating temperature range. Hence, an alternative FoM is proposed as [12] = 10 where Trange is the temperature range of the timer. FoM2 considers the tradeoff between frequency, temperature, power, and TC and subsequently expresses the performance in numerical value. Another indicator that is commonly used is the energy efficiency of the timer, which is expressed as As the dynamic power of circuits generally is proportionate to its operating frequency, the energy efficiency is a simple yet powerful indicator to depict the energy consumption of the timer in each cycle, which perfectly suits the performance evaluation for low-frequency oscillators [9].

III. RECENT STATE-OF-THE-ART TIMERS
In this section, a review of recent state-of-the-art timers is provided. Based on the architecture, we can generally classify the timer into open-loop-based and close-loop-based timers. For an open-loop-based timer, the oscillating signal is generated by a free-running oscillator, which can be a relaxation oscillator or ring oscillator. For instance, consider a relaxation oscillator, the output signal is generated by alternately (dis-)charging the capacitor. Although there might be certain error compensation components to ameliorate the frequency accuracy [22], the frequency of the oscillator's output merely depends on its timing element.
Here, we shall stress that although we used the term openloop, the core oscillator itself (i.e. relaxation oscillator and ring oscillator) is still constructed in a loop. The term openloop only refers to whether an auxiliary loop regulates the oscillator's output frequency. Alternatively, for the closed-loop-based timer, a voltagecontrolled oscillator (VCO) is integrated within a feedback loop. The output of the VCO is fed to a frequency-to-voltage (F-V) converter (e.g., RC network), which senses the output frequency and converts it to a voltage signal. Then, an amplifier/comparator compares this voltage to a reference voltage signal and provides a corresponding output. After filtering out the out-of-band noise by a low-pass filter, the output signal is fed to the VCO to tune its frequency. Provided that the loop gain is sufficient, the output frequency will only be affected by the reference voltage signal and the conversion gain of the F-V converter. If the VCO's output frequency deviates amid VT-variations, the F-V converter tracks this deviation via the loop and makes an appropriate adjustment. As such, the frequency of the timer is being "locked" and kept constant.
In terms of architecture, the closed-loop-based timer has a more complicated pattern than the open-loop-based counterpart as it is constructed with a continuous feedback path using multiple blocks. Comparatively, the design process of the open-loop-based timer is much more straightforward. In the subsequent subsections, we will elaborate on the recent open-loop-based and close-loopbased timers respective to their performance parameters.

A. OPEN-LOOP-BASED TIMERS
The open-loop-based timer is primarily implemented using a free-running oscillator acting as a frequency generator. Both the ring oscillators and relaxation oscillators (RxO) can be categorized as an open-loop-based timer. RxO is preferred as kHz-to-MHz range timer, as the ring oscillator is usually designed for higher frequency applications [23][24][25]. Fig. 1 shows the general architecture of the RxO [26,27]. Two matched current source are utilized; one injects the current into a resistor to generate a reference voltage VREF = IREFR, and the other charges/discharges the capacitor. The voltage on the capacitor (VIN) is compared with VREF through a comparator. Initially, the capacitor is reset to the ground. Then, it is charged by IREF, where VIN can be formulated as IREFt/C, assuming IREF is constant with time. Once VIN > VREF, the output of the comparator changes, and a reset signal will be sent out and discharges the capacitor [11]. The process iterates for every cycle. The ideal period of the timer is thus RC.
Ideally, the capacitor starts to discharge once VIN > VREF, and the discharge process will be completed instantly. Yet, the actual period is affected by the delay of the comparator and logic gates and thus subjected to PVT variations [28][29][30][31]. Such waveform is depicted in Fig. 7, where there is an additional delay of td (comparator delay, buffer delay, etc.) and treset (capacitor discharging time) in a cycle on top of the desired capacitor charging time. To minimize td, a high-speed comparator is required, which implies high power consumption and contradicts to low power design preference for IoT devices.
To eliminate unnecessary discharging time of the capacitor, an improvised architecture using two sets of charging capacitors with respective comparators has been implemented [32][33][34]. This RxO has an additional capacitor path for charging/discharging process and comparator to compare VREF and VIN1(2) [ Fig. 8(a)]. Although the charging/discharging processes are the same, this architecture eliminates treset by alternating the charging process between two capacitors [ Fig. 8(b)]. Hence, this RxO has higher immunity against PVT variations since fewer components contribute to the cycle period, thereby improving the frequency stability.
As aforementioned, the thermal noise and 1/f-noise induce jitter on the timers. For the RxO, by using "first-crossing approximation", the jitter due to thermal noise can be determined as [21] ∆ ∝ (10), where is the noise variance referred to the input of the comparator and is the slope of VIN in proximity to the threshold. To improve the jitter performance, we can either minimize or maximize . The former implies that a low-noise comparator must be used. In maximizing , a higher IREF and VREF are required provided that the oscillation period is unchanged. Both approaches increase the power consumption and impose a tradeoff between jitter and power.

1) SWING-BOOSTING
Swing-boosting technique proves effective in improving the jitter performance of the RxO. Several works adopting swing-boosting RC networks have been reported in the literature in the past few years [12,21,[35][36][37]. Zhou et al. [35] introduced a swing-boosting capacitor charging/discharging method that allows the capacitor voltage swing to exceed VDD. The RC network is shown in Fig. 9(a), while its corresponding waveform is shown in Fig.  9(b). It is assumed an initial condition for all switches Q are open, while all switches QB are closed. C22 and C21 are disconnected and charged to VDD and 0.5 VDD, respectively. Concurrently, C11 and C12, which are initially charged to 0.5 VDD and VDD respectively, are connected in series and start to discharge from 1.5 VDD (explained below) to the ground via R. Once VCAP1 drops below VREF, the output switches to the next half-cycle, where all switches are flipped. As the charges stored in C21 and C22 are conserved and the bottom plate of C22 is connected to C21, which was previously charged to 0.5 VDD, VCAP2 is boosted to 1.5 VDD and discharges to the ground via R. Meanwhile, C11 and C12 will be charged to 0.5 VDD and VDD respectively. The operation repeats itself after another cycle. As the swings at the capacitors increases to 1.1 VDD, the jitter of the RxO can be improved [38]. This improvement inevitably comes at the penalty of higher capacitor count and larger chip area, incurring higher manufacturing cost.
With the same initiative, Lee et al. [21] proposed the differential swing-boosting technique with fewer component counts and a higher boosting range. The proposed RxO is shown in Fig. 10(a), where Fig. 10(b) displays the corresponding waveform. As opposed to [35], the bottom plates of the capacitors alternate between VDD and ground in different phases of the cycles by the chopper, while the top plates are connected to the input of the comparator. With the differential operation, the peak-to-peak swing across the comparator increases to 2 VDD, further improving the jitter of the RxO. Benefitting from the differential operation, this architecture avoids the voltage reference, which is subjected to VT-variation. It scores a jitter performance of 9.86 psrms  This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/ACCESS.2022.3183995 (0.01% of its period). The large swing is achieved at the expense of high power consumption. In addition, as the voltage swing is higher than VDD at the input of the comparator, it may cause long-term reliability issues to the transistors, particularly for advanced deep-submicron process with breakdown voltage < 1 V. The VDD of the RxO could be reduced to pursue ultra-lowpower operation. Lei et al. introduced an ultra-low-voltage RxO with an asymmetric swing-boosted RC network (Fig.  11) [12]. It operates with sub-0.5V supply voltage to be compatible with the low output voltage of energy harvesters [39,40] while maintaining the overall performance. The proposed work has a similar architecture to [21], except that the resistance in two RC branches of the RC-network are unequal.
This arrangement leads to different charging/discharging rates of the capacitor. As such, the common-mode voltages where VIN1 crosses VIN2 alternate between VCM,U and VCM,D instead of 0.5 VDD as in [21]. It eases the low-voltage operation since VCM,U and VCM,D can be maneuvered to fit the operation of the subsequent dual-path comparator (NMOS-input and PMOS-input). It achieves the state-of-the-art energy efficiency of 667 fJ/cycle and FoM2 of 181 dB.

2) TEMPERATURE-DEVIATION COMPENSATION
Various compensation methods have been reported to alleviate the frequency deviation of the RxO due to temperature variation [12,13,[41][42][43][44]. The techniques can be mainly characterized into two groups. The first is to compensate through the resistors of the RC network. By adapting series resistors with positive and negative TC (e.g., silicide/non-silicide poly and diffusion resistor), a composite resistor with specific TC can be obtained and providing firstorder TC compensation [13,41,42,45]. As the delay from the comparator and logic gates is also temperature-sensitive, a non-zero TC of the resistor can be utilized to nullify the overall TC [43].
The second compensation method is active tracking of the delay by the comparator and logic gates. For instance, a delay generator is introduced in [12] to track and compensate for the delay by modifying the time constant of the RC-network. The delay generator is biased with the same current as the comparators. If the bias current decreases (e.g., temperature decreases), the delay increases, so the width from the output of the delay generator also increases. At the same time, the time constant of the RC-network is halved to compensate for this delay. A replica of the comparator and logic gates can also be used to track the delay, as proposed in [44]. It replicates the main branch to measure the delay and compensate for it by halving the time constant at the same time.

3) DESIGN CONSIDERATION
For designers, it is important to determine the design priority based on different applications, as most parameters exhibit tradeoff in performance. With the same FoM, reducing the power would result in an increase in phase noise (7) and temperature coefficient TC (8). One of the persistent goals of the research on IoT timer is to reduce the power consumption. This can be realised by minimizing either the supply voltage VDD or total current consumption [46]. For such ultra-low-voltage applications, swing-boosting technique proves to be a promising solution [12]. Apart from reducing the power consumption by achieving state-of-theart energy efficiency, the work also exhibits a promising frequency stability against PVT variation. A total current reduction can be realised by implementing duty-cycled dynamic components that only turn on when required. The toggling is achieved through the use of logic gates. In comparing [12] and [43], both works achieve ultra-lowvoltage supply compatibility of 0.35 V and 0.4 V, respectively. The work [12] implemented a dual-path comparator to suit the low voltage operation, while [43] adopted a two-stage comparator with the first stage reusing part of the reference circuits and the second stage is heavily duty-cycled with sub-threshold operation.
Note that, by reducing the supply voltage, usually it comes with a tradeoff with other parameters such as jitter performance. As referred to (10), the input noise of the comparator is inversely proportional to the voltage swing slope. With reduced VDD, the allowable voltage swing would reduce and exhibits a lower slope, resulting in an increment in noise. For instance, with an identical swing boosted technique, [12] achieved the lowest voltage supply and an outstanding energy efficiency with a penalty in jitter performance of 800 psrms, while [21] exhibits jitter performance of 9.86 psrms using 4× higher supply voltage, with 31× larger energy per cycle. The designers are recommended to modify the components accordingly based on their design constraints.

B. CLOSE-LOOP-BASED TIMERS
In a basic RxO, one cycle period contains multiple uncertain delays, mainly due to dynamic comparator, buffers and charging reset. Few techniques have been reported to increase the frequency stability by delay elimination This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.  [12,13,[41][42][43][44]47]. Alternatively, close-loop-based timer such as FLL, has better immunity against the VTvariations of the system. In principle, the output frequency of the FLL is only governed by the timing element such as the RC-network and the VCO is only used to provide an oscillation signals, which the frequency is locked by the loop [48]. The basic structure is shown in Fig. 1(b).
In contrast to RxO, FLL is constructed with multiple components connected in a feedback loop. Although different methodologies have been developed based on design priorities, the FLL share similar architecture as described in [49]. The output of the VCO is fed into an optional frequency divider. The purpose of this frequency divider is to step down the frequency and reduce the operating speed of other blocks and thus the power consumption [50,51]. Another compulsory component block for FLL is the Frequency-to-Voltage (F-V) Converter or Frequency Detector (FD), which is implemented through RC network. The F-V converter should be resilient against PVT deviation and provide a stable frequency reference point to the FLL for locking purpose. A comparator/amplifier will then be used to detect and correct the frequency shifting.

1) POWER REDUCTION TECHNIQUES
In RxO, the dynamic comparator contributes most of the delay, hence affecting the frequency performance of the timer as it is sensitive to temperature and supply [52]. In order the reduce its delay, the power consumption must be increased, thereby burdening the power budget. In this regard, the work [11] adopts the FLL structure and uses a low power amplifier for signal comparison (Fig. 12). By using FLL, frequency stabilityimproves due to the feedback and lock mechanism. Together with the low power amplifier, not only the total dynamic power is reduced significantly, the FLL structure also shows superior long-term stability compared to the open-loop-based timer [11].
Following the FLL architecture, Ding et al. [53] proposed a digital-intensive FLL that exploits the advantage of advance CMOS technology nodes. It allows the implementation of a low area, low power, and low supply voltage timer (Fig. 13). In this topology, the signal generated by the digitally-controlled oscillator CLK is fed into multiphase divider, which steps down the frequency from fosc to fosc/16. The step-down frequency is then sent to the nonoverlap clock generator to distribute the corresponding signals into different components. The frequency of the FLL is governed by a differential Frequency Detector (FD) formed by RC network as aforementioned. Such differential topology ensures the stability of performance respective to the supply and temperature variation. The resistor of FD is implemented with a series combination of non-silicided ppoly and n-poly resistors with opposite temperature  This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. coefficients (TC). Such implementation provides first-order compensation in temperature variation [53]. A dynamic comparator compares the output of the FD, which is then fed to a digital filter and locks the frequency of the digitallycontrolled oscillator. The power consumption of the comparator is suppressed by reducing its operating frequency by 256×. It achieves an outstanding energy efficiency of 0.43 pJ/cycle, with a TC of 106 ppm/ºC. Truesdell et al. [50] also report a digital FLL, which locks the Digitally Controllable Oscillator (DCO) to a stable reference voltage VREF (Fig. 14). The frequency generated by the DCO is divided and fed to the F-V converter, generating VCAP to compare with VREF. For this DFLL, a comparator bank is implemented and a dead-zone (DZ) around VREF is established. When the DCO operates within this DZ, it indicates that the frequency generated by the DCO is stable and the feedback path would be broken such that the DCO will be free-running. As such, the power consumption is minimized as other blocks will be powered down. Certainly, the DCO will be subjected to supply and temperature variation if the feedback loop is broken. Hence, the timer is being designed to periodically turn on to lock the frequency by the duty-cycling mechanism. Such approach effectively reduced the power consumption by only consuming 18.8 fJ/cycle. However, this scheme penalizes the frequency accuracy by exhibiting an Allan Deviation of 450 ppm, which is considered high among timers.

2) HIGH PRECISION METHODOLOGIES
With the design preference on frequency stability for FLL, works focusing on high precision have achieved an inaccuracy as low as ±200 ppm across the industrial temperature range. In 2018, Gürleyük et al. [54] proposed a Dual-RC Frequency Reference that uses an FLL for high precision signal generation. The FLL features two independent low-pass-filter (LPF), implemented using Wien Bridge filter, to detect their temperature-dependent phase shifts and locks the frequency of DCO (Fig. 15(a)). One of the Wien Bridge filters employed silicided p-poly resistors to demonstrate positive temperature phase shift, while the other used non-silicided n-poly resistors. With proper calibration, a temperature-independent frequency signal can be realized, resulting in an extraordinary TC of 2.5 ppm/ºC. It is worth noting that instead of using a LPF and temperature sensor for phase shift detection, [54] uses two independent LPF and complex temperature-compensation schemes to achive low TC, which leads to a high energy consumption of 110 pJ/cycle. On top of that, it also consumes a chip area of 2.528 mm 2 , which is critical for SoCs.   [57] This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/ACCESS.2022 In the effort to relax calibration complexity, [55] proposed another RC-based frequency reference in which the FLL features only one Wien-Bridge (WB) filter, while the temperature phase shift is detected by a Wheatstone-Bridge (WhB) temperature sensor (Fig. 15(b)). In this work, both WB and WhB exhibit similar non-linearity of temperature dependencies, achieving good accuracy using a 2-point trim. Such effort led to a massive decrement in power consumption to 25 pJ/cycle and reduced the area consumption by 8.4×. Although the temperature inaccuracy has been increased to ±400 ppm across the industrial temperature range, it still shows an outstanding TC of 6.15 ppm/ºC.
Recently, similar inaccuracy of ±400 ppm has been achieved with a single room-temperature trim [56]. Similar to [55], the FLL also constructed based on a WB filter and a WhB temperature sensor. Instead of a separate implementation, [56] combined both WB and WhB into single architecture (Fig. 15(c)). Therefore, not only the number of components are reduced for smaller chip usage, the temperature-compensated phase shift has also been suppressed since p-poly resistors were being shared by both WB and WhB. By reducing both number of trimming points and counts, it exhibits an energy efficiency of 9.9 pJ/cycle (2.5× improvement) and chip area reduction of 2×, with the state-of-the-art TC of 5.2 ppm/ºC. Apart from using LPF or temperature sensor for compensation, [57] has proposed a temperaturecompensated R-RC oscillator that focuses on eliminating possible temperature-caused delay. Based on the differential swing-boosted technique in [21], [57] had performed certain calibration on the RC network configuration. In common situation which relies on a single RC network, the charging/discharging rate is fully dependent on the resistance, which is highly susceptible to temperature deviation. Although it's first-order dependency is compensated using a series combination of positive and negative resistor, it's resistance still deviates due to secondorder temperature dependency. On top of that, extra reset delay is also expected with the usage of single reset transistor. In this regard, [57] has added another resistor to form a R-RC network (Fig. 16). The extra resistor can eliminate the existing second-order temperature-coefficient. As such, second-order temperature dependency is being mitigated by modifying it's initial charging point across different temperature. On top of that, in the effort of achieving temperature-independent operation, the capacitor and reset transistor has been duplicated for dual-phase operation, where transition mode and reset operation is taken in different path. This leads to a fast reset and low leakage transition operation. Although the supply voltage required is relatively high, [57] scores state-of-the-art TC of 7.93 ppm/ºC across wide temperature range of -45 ºC to 125 ºC, while consuming 3.3 pJ/cycle.

3) DESIGN CONSIDERATION
As aforementioned, with a design focus on power reduction, similar considerations can be taken for FLL in minimizing VDD and total current consumption. The reduction of current consumption can be achieved through multiple approaches. The most common one is to reduce the operation speed of the FD, as described in the beginning of this section [6,54,55,58]. Also, duty-cycling part of the modules can reduce the power consumption. For example, the comparator is to demonstrate the frequency shift and this comparison period only occurs around the transition point. Hence, by providing the appropriate clock signal, the comparator can be designed to only operate within the transition period and subsequently sustained in idle mode for the rest of the time period [3]. The same technique can be applied to other blocks, such as biasing circuits [50].

IV. COMPARISON BETWEEN OPEN-LOOP AND CLOSE-LOOP BASED TIMER
Both the open-loop-based and close-loop-based timers serve to provide an accurate frequency reference for timing purposes. A benchmark of the recent state-of-the-art kHz-to-MHz timers for both architectures is described in Table 1. Fig. 17 illustrates their energy efficiencies versus the TC, while the circle size represents timer's operating temperature range.
Intuitively, it might be perceived that the close-loop based timer will have higher power consumption compared with the open-loop-based timer due to excessive components. However, from Fig. 17, we can observe that the closed-loopbased timer in general achieves a better TC with the same energy efficiency. Despite fewer components in an openloop based timer, the comparators consume the majority of power to safeguard the TC of the timer, which leads to extra power usage and deteriorates the energy efficiency [59]. Contrarily, even the close-loop-based timer entails more components, the comparator and the logic gates have minimal impact on the frequency of the timer. Consequently, even with minimal power consumption, the closed-loopbased timer can still yield a stable output amid VT-   This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. variations, relaxing the current requirement and maximizing the energy efficiency.
Apart from the TC, one of the important parameters to be taken into consideration is the temperature range. In practice, the timer is preferred to be operated in a wide temperature range to cope with the harsh environment [60]. For instance, a common standard is the full-industrial range, which requires the electronics to work from -40 °C to 125 °C. As shown in Table 1, although some of the reported works were able to achieve a low TC, their operating temperature ranges are comparably narrow, while others managed to maintain a moderate TC over a wide temperature range. For instance, [61]   CL = Close-loop-based OL = Open-loop-based * Estimated from graph $ Deduced from the number of cycles to start, which may underestimate true startup time. # Performance cannot be fully evaluated, as it did not take settling time into consideration This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/ACCESS.2022.3183995 function across the full-industrial range but exhibits a higher TC of 7.93 ppm/ºC and 15.76 ppm/ºC, respectively. Hence, it is important to characterize a timer's ability to maintain a moderate TC within a reasonable temperature range. Such ability can be expressed using FoM2 where an overall performance can be enumerated as defined in (8). Take the open-loop-based timer as example, the work [61] shows the lowest TC among all proposed works, but exhibits poor performance in temperature range and energy efficiency, which leads to a moderate overall performance with FoM2 of 174 dB. Contrarily, although [22] shows a relatively moderate TC of 21.8 ppm/ºC, it presents the best FoM2 among all competitors with it's exceptional energy efficiency and wide operating temperature range.
One drawback of the close-loop-based timer is in its long settling time. As summarized in Table 1, the open-loopbased timer shows a significantly lower settling time compared to the close-loop-based timer. To guarantee the loop stability, the loop filter ought to have a cutoff frequency lower than the sampling rate of the comparators, which in turn limits the settling time of the loop response. On the other hand, the settling time of the open-loop-based timer is solely dependent on the settling time of the RC-network, which can be achieved in a couple of cycles.

IV. CONCLUSION
Motivated by the uprising trend of ultra-low-power timers, this review article elaborated on the characteristics of fullyintegrated timers reported in the literature. We categorized these timers into two types based on their architectures: open-loop-based and close-loop-based. We also explained in detail the basic parameters to characterize and optimize a timer. To differentiate the timers, we found out that the openloop-based timer depended on a single free-running oscillator to generate the frequency, while the closed-loopbased timer contained a feedback path to lock the output frequency. In general, the open-loop-based timer shows a faster settling time than the close-loop-based timer, but with a penalty on TC in effect to the delay from the logic gates and comparators/amplifiers. On the other hand, the closedloop-based timers show a better TC under a similar power budget, benefitting from the closed-loop operation. We recommend the designers to determine the main design priority before finalizing a suitable architecture. We envision that the development of ultra-low-power timers will continue for both types of timers, aligning with the current trend of energy harvesting for IoT nodes.