A Low-Noise Fast-Transient-Response Delta-Sigma-Modulation Buck Converter with Hysteresis-Voltage-Controlled Techniques

A low-noise fast-transient-response second-order delta-sigma-modulation buck converter with hysteresis-voltage-controlled techniques is proposed. With the proposed control approach, the transient time can be accelerated by roughly 60%. The rail-to-rail OTA generates a current ISense, which replicates the inductor current IL with K times. As ISense flows through the capacitor CSense, it will be converted into VSense. Then, the hysteresis-voltage-controlled (HVC) circuit compares the two terminal voltages of hysteresis comparator to detect the overshoot and undershoot of VSense. Once VSense is detected, the output signal of HVC circuits becomes opposite to the previous state to conduct MP and MN previously. Besides, the 2nd-order delta-sigma-modulation (DSM) circuit plays a vital role of mitigating noise-interference and elevating noise in whole circuits. The proposed converter has been fabricated in TSMC 0.18μm 1P6M CMOS processes with an active area of 1.19×1.09mm2. The measured results show the transient time are 3.5μs and 3.2μs, respectively, when the load current changes between 500mA and 100mA. On the basic of the measured results of fast-fourier-transform (FFT), the value of output-to-noise ratio (ONR) is 76.6dB at the sampling frequency of 10MHz. The peak conversion efficiency is 92.1% while the load current is 300mA.


I. INTRODUCTION
n our daily life, smart phones, aerospace industry, medical care, and e-commerce build up the chip industry chain. For the purpose of satisfying the demand from all walks of life, the integration of systems-on-chip (SoCs) seems extremely important. In recent years, the Delta-Sigma-Modulation (DSM) architecture have been applied to the field of power electronics owing to the superiority of low electromagnetic interference (EMI) and high efficiency over a wide load range. To overcome the spurious switching noise and enhance the transient response, the scheme we proposed utilizes the noise-shaping theorem and hysteresis-voltagecontrolled techniques. In the field of power management integrated circuits (PMICs), the architecture of DSM is adopted to alleviate the impact on the noise-sensitive circuits [1][2][3][4][5]. On the other hand, the drawback of DSM is inevitable. Namely, the characteristic of transient response is relatively poor compared with other architectures. Hence, a currentsensing path that can ameliorate the recovery time is needed. Figs. 1 and 2 illustrates the simplified architecture of the proposed buck converter, which is categorized as two loops, voltage and current loops. Power stage, LC filter, compensator, DSM, driver and nonoverlapping circuits constitute the voltage loop, namely the steady-state loop of proposed buck converter, and the other loop comprises the HVC circuits and rail-to-rail current-sensor. The blue line shadowed block is regarded as transient-state loop, which is designed to rapidly detect the overshoot and undershoot of the output voltage of rail-to-rail current-sensor voltage VSense. Once VSense is detected by the HVC circuits, the output voltage of SR Latch VDuty will change the state immediately. And this movement makes the switches conduct in advance so that the recovery time of output voltage improves greatly. Moreover, the current-sensing-feedback loop can move the inductor pole to high frequency and increase the phase margin of loop gain. To verify the large-signal stability of the proposed converter, we have used HSPICE to simulate the converter and obtained stable results.
The work is organized as follows. In Section Ⅱ , the proposed architecture and the operation mechanism are introduced successively. We will examine circuit implementations in more detail later in Section Ⅲ. Section Ⅳ shows the experimental results and comparison chart of the proposed converter. Finally, the conclusion is presented in SectionⅤ.

II. II. THEORY AND OPERATION MECHANISM OF THE PROPOSED CONVERTER
In this section, features related to over-sampling theorem, Nyquist-sampling theorem, noise-shaping and the quantization error will be discussed as followed. Characteristics mentioned above will also be applied to firstorder as well as second-order CT-DSM architecture. And the pros and cons between two structures are listed in the comparison chart.

A. Oversampling Theorem
Generally, the conversion of analog signals in nature into digital signals requires anti-aliasing to prevent the sampling signals from distortion. The sampling circuit will separate the analog signal to form a discontinuous signal and send it to the next circuit. The discontinuous signal after sampling is converted into the nearest segmented analog signal through the quantization circuit. A number of digital signals will form a voltage or current signal level, and this step determines the resolution of the entire converter. The digital signal is then converted into usable digital signal through the digital decoding. The more sampling points the converters sample, the higher resolution of the converter has.
f f 0 f s 2f s -f s -2f s 0

FIGURE 3. Phenomenon of aliasing signals
The Nyquist sampling theorem defines that the sampling frequency (FS) must be at least twice the signal bandwidth (FB) as formula (1) expressed. If the sampling frequency FS is less than twice the signal bandwidth FB, the sampled signal will overlap, which means that the signal aliases. In order to overcome the difficulty of the sampling, the design of antialiasing filter is essential.
The oversampling theorem is defined as the sampling frequency is much greater than twice the signal bandwidth of the sampling frequency (FB). Moreover, the oversampling ratio (OSR) can be defined by the Oversampling frequency and the Nyquist-sampling frequency as formula (2) expressed. If the sampling frequency defined by the Nyquist theorem is selected, the signal transition band on the spectrum is narrower than the sampling frequency defined by the Oversampling theorem. It makes the design of the antialiasing filter easier.

B. Quantization Error
The quantization process of Nyquist sampling frequency is that the sampled analog discontinuous signals converter into multi-segment digital signals. Ideally, analog signals will be accurately sliced into the over-sampling frequency spectrums of several discontinuous signals. And the level of each analog signal corresponds to the value of a digital signal one by one. The situation that different analog signal levels are converted into the same digital signal won't occur. However, there will be an error in signal conversion due to external factors in the circuit, which is called quantization error as shown in Fig. 5.
The quantization error signal is defined as the difference between the output signal Y(n) of the quantizer minus the input signal X(n) as shown in Fig.6. The symbol Δ represents the difference between the levels at which each analog signal is converted into a digital signal. The smaller the Δ, the better the quantization effect. The input signal of the quantizer must still be within a certain input range, so that the variation of the quantization error is limited to the range of -Δ⁄2∼+Δ⁄2, otherwise the quantizer will be overloaded and the quantization error will be boundless.

FIGURE 6. Relationship of quantizer input signal and quantization error
We can assume that the quantization error is an independent signal that is not affected by the input signal, meaning a white noise signal, as shown in Fig. 7, which is the probability density function (PDF) of the quantization error e(n). It can be seen from Fig. 7 that the quantization error range will be evenly distributed between ±∆⁄2, and the probability density function of the quantization error e(n) and the quantization error product are 1, so we infer that the total noise power PNoise is the probability density function and quantization. The area enclosed by the error can be expressed as formula (3).
Assuming that the input signal is a sine wave signal Asin(ωt), the power PS of the output signal can be expressed as equation (4). By using formula (4), we can derive the Signal-to-Noise Ratio (SNR) expressed as formula (5). As shown in formula (5), it can be seen that the SNR can be improved by 6.02 dB when the quantizer increases by one quantization bit.
= 10 log = 6.02 + 1.76 ( ) (5) Fig. 8 shows the quantization error power spectral density (PSD) graph, and the height HE of the power spectral density is shown in equations (6). As long as the value of the sampling frequency FS is increased, the height of the power spectral density will be reduced, and the distribution become evenly. At this time, the power spectral density boundary will expand from ±FN to ±FS⁄2, and the overall power sum is still consistent with the power sum of the Nyquist sampling frequency.
PSD can not only break apart the noise distribution within the bandwidth significantly, but also makes SNR a noticeable increase. As shown in formula (7), it can be derived from the results that the SNR can be improved by 3dB for every doubling of OSR. Compared to blindly increasing the number of quantization bits to ameliorate the SNR, adjusting the sampling frequency is more effective.
C. Noise Shaping In the previous paragraph, it is mentioned that the oversampling technology can be used to spread the noise distribution evenly and reduce the amount of noise in the signal bandwidth. However, there is still an upper limit for increasing the sampling frequency, which cannot be solved by simply increasing the sampling frequency. Therefore, the concept of noise shaping was introduced.
The purpose of noise shaping is to change the energy distribution of the quantization noise and move the noise to a higher frequency spectrum. This can not only obtain a highresolution signal, but also reduce the multiple of the oversampling frequency. Fig. 9 shows the interpolative architecture and linear model of the first-order delta-sigma modulator, u(n) and y(n) are the input and output signals, e(n) is the quantization error, and H(z) It is a loop filter. This architecture is similar to the concept of operational amplifier feedback, using high-gain operational amplifiers with the concept of feedback to reduce the impact of noise at the low frequency. In the light of the superposition theorem and Mason's Gain Formula (MGF), the relationship between the input and output signal of this first-order system can be derived, as shown in formula (8).
H(z) is the loop filter, and it can be expressed as formula (9) after Laplace Z conversion. With formula (8), assuming that e(z) and X(z) are zero respectively, the signal transfer function (STF) and noise transfer function (NTF) can be defined separately as formula (10) and (11). Based on the results, Z -1 can be regarded as a delay time T=1/RC, and (1-Z -1 ) can be viewed as a high-pass filter. The high-frequency signal will be filtered.
It can be found from equation (10) that the larger the gain of H(z) is designed, the more similar the output signal's frequency spectrum can be to the input signal. In order to calculate the resolution of the delta-sigma modulator, z = e jωt = e j2πf⁄Fs can be substituted into equation (10) and (11). And by taking the square, STF(z) and NTF(z) can be calculated, as shown in formulas (12) and (13). As shown in Fig.10, the signal transfer function (STF) is not affected by the frequency and is a constant. The noise transfer function (STF) can be quantized to push the noise to the high frequency, and then use a low-pass filter to filter out high-frequency noise. In order to obtain the performance of the first-order delta-sigma modulator, the noise power within the bandwidth can be calculated, as shown in equation (14).
Under the condition of oversampling, FS≫FB, it can be seen that sin(πf/FS) ≈ πf/FS, so the noise power can be rewritten as equation (15). Equation (16) is the signal-tonoise ratio (SNR).
This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.  (16), it can be obtained that for every doubling of the OSR, the SNR can be improved by about 9 dB, which means that the resolution is increased by 1.5 bits.

D. Second-Order DSM
The second-order delta-sigma-modulator is composed of two integrators (Integrator, Z -1 ) and a quantizer, and this architecture is interpolative. The transfer function of the second-order delta-sigma modulator is set to z=e jωt =e j2πf⁄Fs , which can be expressed as equation (17). After squaring both sides of the equal sign of equation (17), the signal transfer function STF(z) and the noise transfer function NTF(z) can be obtained, as shown in equations (18) and (19).
From the above conclusions, the noise power and SNR within the bandwidth can be expressed as equations (20) (21), it can be seen that for every doubling of the OSR, the SNR improves by about 15 dB, which means that the resolution increases by 2.5 bits. In contrast, the second-order architecture has better noise immunity than the first-order. So far, the chapter has focused on the theory adopted by the designer. The following section will discuss the circuit implementations. The comparison of DSM is shown in Table I.

III. CIRCUIT IMPLEMENTATIONS
The power stage, the type-Ⅲ compensator, 2 nd -order DSM, and the circuit with proposed HVC techniques make up the proposed continuous-time-delta-sigma-modulation (CT-DSM) buck converter as shown in Fig. 2. Before proceeding to examine the proposed buck converter, it will be necessary to elaborate the operation mechanism about the whole circuit. When this circuit works in steady state, the voltage VSense sensed by the inductor will fall between the upper and lower limits (V BH, VBL) of the hysteresis voltage band. This result will let the output of the comparator in the HVC architecture set to zero. In this moment, it doesn't affect the input value of SR Latch in the original circuit. Nonetheless, when the output load current is switched between the light and heavy load, the change of load current will make the signal VSense to switch at once. As the VSense is greater than the upper limit or less than the lower limit, the output VDUTY of the SR latch will change accordingly. Hence, only this situation will the transient loop be activated. In conclusion, the transient and steady-state loops won't affect each other. The detailed structure and functions of the buck converter will be indicated in the forthcoming parts.

OTA-C Current-Sensing Circuits (GM)
The OTA-C current sensing circuit is shown in Fig. 13. Thanks to the advantage of wide input voltage range, large bandwidth, and simple architecture, we adopted rail-to-rail OTA as GM of the current sensing circuit. The current flowing from the output terminal VSense of the Rail-to-Rail transconductance amplifier is the sensing current ISense. A capacitor CSense is added to the output terminal, and then the current is converted into the voltage signal VSense, which is used as the transient acceleration detection. The relationship between the transconductance of rail-to-rail transconductance amplifier and the sensing voltage VSense is expressed as equations (22), (23), (24).

Hysteresis-Voltage-Controlled (HVC) Circuits
The hysteresis voltage circuit is shown in the Fig.14. The purpose is to provide the level of the current sensing voltage VSense and generate the upper and lower limits (VBH, VBL) of the hysteresis voltage band. At the same time, the circuit detects the change of load current, and transfers a digital signal VDUTY to the following circuit. When VSENSE is between VBH and VBL, the circuit works in a steady state, as shown in the attached table II. Both points A and B, which are the output terminals of upper and lower comparators respectively, are low, so the original input of SR Latch won't be changed. At this moment, the transient acceleration circuit will not start, but when VSense is greater than VBH and VBL, points A and B are high and low, respectively. On the contrary, when VSense is less than VBH and VBL, points A and B are low and high. This result will make SR Latch input reset, so that the SR Latch output VDUTY transition, that is, the VDUTY signal is switched from high to low. Finally, the consequence turns off the conducted NMOS previously and turn on the PMOS in advance. The method we utilize is that making the pair of power MOS switches earlier to ramp up the transient response of the entire circuit.

3.Quantizer
As shown in Fig. 16, it consists of two parts: the dynamic comparator and RS Latch. By adjusting the frequency of the clock signal VCLK, the state of the signal can trigger two working modes of the quantizer, namely the hold mode and the compare mode. Furthermore, we pull out the VDUTY signal and use it as the output voltage of the quantizer. Finally, we can control the digital-to-analog converter (DAC) with the high and low voltage signals of different potentials.  Fig.17 shows the type Ⅲ compensator circuit, which is usually used in voltage mode as a compensation circuit to make the circuit stable. Compared with the type Ⅱ compensator, it provides additional high-frequency pole and zero. Therefore, it totally contains three poles and two zeros. The type III compensator can increase both the bandwidth and phase margin of a closed-loop system. Equations (25)-(28) are the simplification results of the type Ⅲ compensator transfer function. This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.

IV. EXPERIMENTAL RESULTS
The proposed converter has been implemented in TSMC 0.18µm Mixed-Signal/RF 1P6M processes with an active area of 1.26 mm 2 . And the layout and micrograph of the whole chip are shown in Fig. 19. Fig. 20 is the steady state waveform for the input voltage 3.3V and the output voltage 2V. Fig. 21 shows the experimental results of transient response of the buck converter without the proposed accelerated scheme. Additionally, Fig. 22 shows the experimental results of transient response of the buck converter with the proposed accelerated scheme. As the output load current varies from 500mA to 100mA and 100mA to 500mA, the transient response time are shortened to roughly 3.5μs and 3.2μs, which means that the transient time are improved by 60% respectively. With the objective of reducing the switching noise as well as enhancing the transient time and transient voltage, this paper proposes a fast-transient-response approach with hysteresis-voltagecontrolled techniques applying to the second order deltasigma-modulator buck converter. On the basic of the measured results of Fast-Fourier-Transform (FFT), the value of Output-to-Noise Ratio (ONR) is 76.6dB at the sampling frequency of 10MHz. As a result, it can be found that the transient time improves beyond 4μs when the load current varies with 400mA. Namely, it accelerates approximately 60% after transient-enhancement. As shown in Fig. 23, the peak conversion efficiency is 92.1% as the load current is 300mA. A comparison sheet is attached in Table Ⅲ, which compares the specification and performance of the proposed buck converter to others. The prominent point this work presented are listed as described below.
(1) With utilizing the proposed HVC techniques, we can ramp up the recovery time nearly 5µs.
(2) The second-order delta-sigma-modulator circuits and compensation circuits, which constitute the steady loop, overcome EMI problems as well as the switching noise to reduce the output harmonic tones.
(3) As seen Table Ⅲ, this work has a better FOM with the sampling frequency equal to 10MHz.

V. CONCLUSION
A low-noise fast-transient-response second-order deltasigma-modulation buck converter with hysteresis-voltagecontrolled techniques is proposed. With the proposed control approach, the transient time can be accelerated by roughly 60%. Besides, 2 nd -Order delta-sigma-modulation plays a vital role of mitigating noise-interference and elevating SNR in whole circuits. The proposed converter has been fabricated in TSMC 0.18µm 1P6M CMOS processes with an active area of 1.19×1.09mm 2 . The measured results show the transient time are 3.5µs and 3.2µs, respectively, when the load current changes between 500mA and 100mA. On the basic of the measured results of fast-fourier-transform (FFT), the value of output-to-noise ratio (ONR) is 76.6dB at the sampling frequency of 10MHz. The peak conversion efficiency is 92.1% while the load current is 300mA.