Performance Analysis of Resonant-Fin Transistors and Their Application in RF-Circuit Design

Emerging new communication standards like 5G or 6G aggravate the circuit design of radio-frequency generation systems as they constantly increase demand on high bandwidths, low latency, and high spectral purity. The utilization of high-Q oscillators, however, provides a possibility of optimisation of radio-frequency oscillators regarding their phase-noise performance in the overall system. This paper analyses one of the most promising electromechanical resonator devices, the resonant fin transistor with respect to its performance and application in oscillator circuit design. Several investigations regarding its working principle, design trade-offs and limits are carried out in this work. An oscillator circuit design is given for two variants of the resonant fin transistor device together with an outlook on its performance compared to other state-of-the-art radio-frequency oscillator designs. Following the performance analyses conducted throughout this work, the fundamental limit for the Q-factor of this resonator is investigated, challenging the validity of functionality of the resonant fin transistor and its potential for circuit applications.

RFT device for an exemplary configuration of two differential drive cells-formed by a 14-fin unit cell-with positive and negative electrical drive connections Dp and Dn and one differential sense cell with the positive and negative electrical connections Sp and Sn as well as a ground connection V SS . The gate is electrically connected via port G.
ter. Moreover, the device promises excellent performance, with a Q-factor of 49 000 while resonating at 32 GHz. It utilizes the periodic arrangement of hundreds of adjoining fin field-effect transistors (FinFETs) connected as metal-oxidesemiconductor (MOS) capacitors to create a mechanical wave inside a common gate via electromechanical coupling. The wave is picked up in the centre of the cavity as the change in FinFET current, which is caused by a modulation of the carrier mobility through the resonant mode. Several research efforts have been reported in order to take advantage of the performance of this device in an oscillatory circuit [13], [14]. This paper will carry out a more detailed theoretical evaluation of the working principle, performance and its limitations. Thus, we will give an estimate on the device's significance in RF circuit design for mobile communications and alike.
At first, the working principle of the RFT is outlined in Section II. It is followed by the geometrical explanation of the Finite-Element-Method (FEM) setups for the simulations in Section III. The mechanical anisotropy of the silicon wafer in CMOS technologies is discussed in Section IV, along with the investigated wafer orientations. After the mechanical prerequisites, the electromechanical simulation of the drive is explained in Section V. Afterwards, starting with the stress tensor and the derived pressure inside the sense FinFETs the sensing mechanism is explained in Section VI. Lastly, the FEM setups are calibrated with respect to their CMOS capacitance to measured quantities in Section VII and the Qfactor for the FEM simulation is introduced in Section VIII. Section IX presents simulation results of the conducted FEM simulation. Several impacts on the RFT performance by geometry, biasing, temperature and doping are investigated, resulting in a three orders of magnitude lower transconductance than initially reported. Despite these discrepancies, in Section X of the paper, a study on oscillator circuit design, utilizing the RFT device for frequency generation, is carried out. Furthermore, a comparison in performance to state-ofthe-art oscillator designs is given to evaluate the significance of the resonator for high-performance RF circuit design. Finally, the paper concludes with caveats and possible improvements of the FEOL resonator in Section XI. Following from insufficient performance of the resonant fin transistor found in this work, and the fundamental Q-factor limit, imposed by the Akhiezer effect and Landau-Rumer regime, the validity of the functionality in prior literature of the resonant fin transistor is challenged.

II. FINFET RFT MEMS WORKING PRINCIPLE
To verify the performance of the RFT and its possible application in circuits, for example as resonant fin oscillator (RFO), three-dimensional FEM simulations were carried out with a commercially available simulator 1 . The working principle of the RFT is based on MOS capacitor actuation, which couples to a mechanical eigenmode inside a FinFET gate with hundreds of adjacent fins [12]. The best electromechanical coupling can be achieved by driving neighbouring fins with opposite phases, thus directly coupling to the differential eigenmode of the RFT. However, common foundry design rules prevent separated contacts to adjoining fins, therefore a higher spatial harmonic of the mode is driven. This is achieved by connecting groups of three neighbouring FinFET MOS capacitors, while four intermediate fins between the electrical phases are unconnected, thereby forming a 14-fin unit cell (UC). The mode is sensed in the centre of the cavity by a differentially wired FinFET pair, biased at a constant voltage. The mechanical deformation of the FinFETs causes a modulation of the carrier mobility and consequently a modulation of the drain current in the sense transistor pair at the frequency of the eigenmode [12], [14].

III. MECHANICAL SIMULATION SETUPS
To study the feasibility of the RFT concept, three different simulation setups are considered. The first, shown in Fig. 2b, models the smallest differential UC, with two adjacent fins. The structure is assumed infinite along the channel direction (X-axis) by utilizing symmetric boundary conditions. This creates a device with an infinite number of parallel fingers. However, this simplification suppresses out-of-plane movements of the gate. Nevertheless, it is still valid, even in the presence of anisotropic materials, as the impact of this assumption on the mechanical performance is negligible, which is studied in more detail in Section IX-A. Floquet-Bloch boundary conditions are deployed along the gate direction (Y-axis), which creates an infinite periodic cavity. The vertical directions (Z-axis) are terminated by perfectly matched layers in order to mimic a thick wafer without reflections in the far distance. As noted before, this configuration cannot be manufactured due to common design rule constraints. They prevent different electric contacts to adjacent fins without shorting. Thus, a larger 14-fin UC is required to be compliant with the design rule constraints, as depicted in Fig. 2c [12]. Fin packs of three, made from fins 3-5 or 10-12, are jointly connected to the same electric potential with both phases separated by four electrically floating fins. The two electric phases are indicated by the red coloured fins and dotted box and the blue coloured ones with a dashed box, as depicted in Fig. 2b and Fig. 2c, respectively. To also quantify the impact of a finite amount of fingers and dummy fingers, a third simulation setup, shown in Fig. 2d, is used. The UC is based on the smallest 2-fin UC, however, it is now finite along the channel direction. Therefore, a certain number of active and dummy fingers can be modelled. The latter are required to control the electrical performance by creating an even surrounding for the active gates. The impact of a finite cavity on the final result is not studied in this work. The performance is expected to degrade with a shorter cavity length and badly matched termination, but further investigation is required to prove these expectations. Typical modern Back-End-of-Line (BEOL) stacks for integrated circuits (ICs) consist of a low-κ dielectric such as SiCO:H, with copper for wiring. Copper, which is a highly anisotropic material, strongly affects the acoustic band gap formation in the phononic crystal (PnC) as the compliance changes for different crystallographic orientations [15], [16]. To reduce complexity the BEOL is neglected in this study as it may vary strongly between different foundries and technology nodes. Thus, the BEOL is replaced by an SiO 2 slab in all simulations. Both the silicon wafer as well as the SiO 2 slab are able to confine the resonant mode due to index guiding for frequencies well in excess of the resonant mode's frequency [12], [17]. The higher porosity SiCO:H cannot be used for confinement as the index guiding properties are not sufficient. Hence, for modern SiCO:H based BEOL stacks a PnC mirror is obligatory, but further investigation is required.

IV. WAFER ORIENTATIONS
The FEOL was modelled to reasonable 16 nm technology node dimensions and assumed identical for n-channel metaloxide-semiconductor (NMOS) and p-channel metal-oxidesemiconductor (PMOS) devices. Several of the involved cubic materials exhibit anisotropic mechanical effects which alter the response of the MEMS [15], [18]- [21]. The mechanical properties of all materials used in this work are listed in Table 1. Consequently, as a result of the mechanical anisotropy of silicon, four common wafer orientations, depicted in Fig. 3, are investigated. For the first wafer (001) orientation, with the wafer normal pointing along [001] as shown in Fig. 3a, the crystal axes align with the spatial axes. The second configuration (001) 45 , depicted in Fig. 3b, is rotated clockwise around the wafer normal by 45°, which is the typical orientation used in foundry processes due to its beneficial electrical response to uni-axial strain along the channel direction [110] [27]- [31]. The third wafer orientation (011) was added for completeness and does not exhibit known electrical or mechanical benefits over the other orientations. The wafer normal for the last orientation, shown in Fig. 3d, is pointing along [111]. This orientation is often times deemed beneficial for MEMS designs as Young's modulus, Poisson's ratio and shear modulus are isotropic in the {111} planes [18], [20], [21].

V. ELECTROMECHANICAL SIMULATION SETUP
All depicted setups are initially simulated in an electromechanical fashion for the different wafer orientations discussed in Section IV. The drive MOS capacitors and gates are biased at a constant direct current (dc) voltage V drive = 40 mV and V gate = 800 mV for the NMOS and V drive = 760 mV and V gate = 0 V for the PMOS, respectively, as proposed in [12]. The initial stress inside the FEOL, introduced by the dc bias, is simulated with a stationary electromechanical simulation. For this pre-stressed structure, the possible mechanical eigenmodes are computed. All simulation setups support multiple resonant modes, however, not all can be coupled electromechanically for symmetry reasons. Depending on the exact configuration of the setups, a strong differential eigenmode, with regard to adjacent fins, can be found between 30-35 GHz. It is exemplarily depicted in Fig. 4 for the ideal 2-fin UC, separated in the displacements along the three principal axes. In resonance, adjacent fins expand and compress periodically around the channel. The mode causes only little deformation along the channel direction (X-axis) as shown in Fig. 4a. Along the gate direction (Y-axis), however, shown in Fig. 4b, the fins are alternately contracted and expanded. The same also applies to the vertical direction (Z-axis) illustrated in Fig. 4c. Those deformations lead to a breathing motion of adjacent fins and result in opposite stress, orthogonal to the channel direction, in neighbouring FinFETs. The overall displacement is also indicated in all three setups shown in Fig. 2.
It should be noted, that the larger the size of the UC is assumed, the more spurious modes can coexist, which in turn further degrades the performance of the device. In this work, all spurious modes are filtered out. Only the dominant mechanical eigenmode, referred to as RFT mode, depicted in Fig. 4, is investigated. The RFT mode is then used in an electro-mechanical frequency domain eigenmode simulation, considering the pre-stressed state, with an alternating current (ac) drive voltage amplitude of v drive = 30 mV [12]. The Q-factor of the mode is limited to Q = 1000 via Rayleigh damping, to offer greater numerical stability.

VI. STRESS TENSOR
The mode exerts not only stress on the drive MOS capacitor FinFET channels, but-in resonance-will also deform the sense FinFETs. Therefore, the volume-averaged stress tensor is extracted from each frequency-domain simulation: It is fitted component-wise with a Fano function [32]: with a and b being complex-valued pre-factors, f R denoting the resonant frequency, f R,BW the bandwidth of the resonance and q, the Fano parameter, describing the overall symmetry of the Fano resonance. The Q-factor of the resonance can be retrieved from Q R = f R /f R,BW , which is identical to the value derived from the Rayleigh damping. In Fig. 5, the stress tensor of an exemplary 2-fin infinite UC, fitted with (2), is shown. The stress tensor is expressed in the spatial coordinate frame with the X, Y and Z directions pointing along the channel, gate direction as well as the wafer normal direction, respectively. Fitting the stress tensor allows to reduce the frequency resolution of each simulation and thereby significantly speed up the analysis [14]. For a generalized representation of the data the pressure inside the channels [19]: can be defined as the mean of the diagonal components of the stress tensor.  Exemplarily, the pressure spectrum calculated with (3) from the data displayed in Fig. 5 is shown in Fig. 6. It exhibits a distinct peak at the frequency f R of the mechanical eigenmode. In addition to the main resonance, an antiresonance f A is observed. Together, they define an electromechanical coupling factor [33]: which describes the conversion efficiency from electrical to mechanical energy and vice versa. The coupling coefficient mainly relies on the static FinFET capacitance. It decreases for larger capacities, which leads to a strongly reduced coupling for the 14-fin UC compared to the ideal 2-fin case [14], [33], [34]. Moreover the absolute pressure in the 14fin UC is greatly reduced compared to the ideal case, which is explained in more detail in Section IX-E6.

VII. CALIBRATION OF SIMULATION
The drive MOS capacitor simulations are calibrated to the measured capacitance of typical NMOS and PMOS gate lengths. As a result of the simplified gate stack, the fin to gate capacitance is overestimated in our simulations. Thus the dielectric constant r = 25 of the high-κ HfO 2 is scaled to the effective dielectric constant required to match simulation and measurement [23], [25]. The factors are calculated to r,nmos = r /4.05 and r,pmos = r /3.2. The measured and simulated capacitance of the structure is shown in Fig. 7 for some chosen gate lengths. The single fin capacitances are obtained from de-embedded RF measurements between 25-40 GHz from a larger device with four parallel gates and 30 fins, resulting in capacitances in the pF range. The gate length values correspond to the drawn gate length, however, a constant technology dependant offset for the gate length is considered in the simulations. After calibration, the capacitance of the NMOS and PMOS FinFETs are in excellent agreement with the measured data. Both measurement and simulation are fitted by linear regression as a guide to the eye. As the electromechanical force in a capacitor, formed between gate and fin, changes linearly with the capacitance, the fin pressure p also scales linearly with the relative permittivity of the high-κ layer as shown in Fig. 8. The changed relative permittivity does not affect the frequency of the resonance. Solely the anti-resonance is affected as electromechanical coupling changes with the static capacitance of the MEMS [14], [33], [34]. With an increasing static capacitance, the coupling coefficient is reduced. Therefore, the 14 UC should perform worse as the capacitance of the drive is threefold of the 2-fin counterparts. However, this effect is neglected in the following as the geometric variation and dependence on the Q-factor are assumed more important for the performance.

VIII. QUALITY FACTOR DEPENDENCY
The working principle of the RFT MEMS strongly relies on the reported Q-factor of almost 50 000. The Q-factor is reached with the aid of a PnC mirror in the BEOL [12]. The large acoustic impedance mismatch of the different metal, liner and oxide layers can lead to the formation of a mechanical band gap. Through careful optimisation of the layer thicknesses and horizontal slotting, a wide band gapmatching the resonant frequency of the RFT MEMS-can VOLUME 4, 2016 5 This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.  possibly be created [15], [17], [35], [36]. A well-matched BEOL mirror can reduce losses and thereby increase the Qfactor. However, the copper metal layers are neither isotropic nor mono crystalline, which makes the modelling challenging [15], [16]. During fabrication, copper is crystallizing into grains with distinct orientations [16]. This effect further complicates the band gap formation as all metal layers would therefore exhibit varying mechanical properties based on the grain size and orientation. In the worst case the BEOL would not be able to form a PnC and thus provide no shielding for the RFT. Moreover, current CMOS BEOL stacks are optimized for the electrical performance of existing devices, making adaptions for the needs of a singular device challenging. However, further investigations and in-depth analysis are required. Other SAW and BAW devices achieve Q-factors in the 100-10 000 range, although at much lower frequencies.
They typically fall into the mega-to low gigahertz regime, with a few notable exemptions surpassing 100 000 [5]- [9]. Many of those designs, however, are partially released structures, which suffer mainly from anchor losses. Monolithic integration, on the other hand, requires extensive shielding in all directions. Therefore, more research is required to substantiate the-considering the results from prior art, surprisingly high-reported Q-factor of 49 000 [12]. Due to the increased complexity and the variance of the BEOL for each foundry and process node it was removed from the simulations and the Q-factor is added only via Rayleigh damping, which in turn enables the usage of arbitrary values. The RFT is thus modelled at a much lower Q-factor of 1000 for greater numerical stability, convergence and speed in the FEM simulations. Furthermore, it provides a worst-case approximation, in the case of a lower Q-factor than reported, for the circuit simulation in Section X.
The impact of a changing Q-factor on the pressure in resonance is shown in Fig. 9. It was varied between 100-500 000, however, the change in pressure at f R scales linearly over multiple orders of magnitude as a result of the employed Rayleigh damping formalism. Thus, all simulations are carried out at a Q-factor of 1000, and can be scaled with: to the desired Q-factor Q new . This is only true for the resonance frequency and can not be used to scale the full spectrum to a new Q-factor. Note that (5) is only valid under the assumption of a linear mechanical response, however, the fins displacements are small, and thus justifying this assumption.

IX. SIMULATION RESULTS
The simulations were performed on the infinite 2-fin and 14-fin UC for typical CMOS FinFET gate lengths, ranging from 16-150 nm on four different silicon wafer orientations. Each simulation was repeated for both NMOS and PMOS FinFETs. The resonant frequency was extracted from the fitted data with (2), as explained in Section VI and is shown in Fig. 10. The resonant frequency shifts from 34. 35-30.71 GHz with increasing gate lengths. Both UC configurations yield the same resonant frequency, which is to be expected as only the number of repetitions of the UC is changed. Furthermore, the different mechanical properties of each wafer result in separate resonant frequencies at the same gate length. As shown previously in Fig. 8, the choice of NMOS or PMOS devices does not influence the resonant frequency in those simulations. Choosing a different gate length also enables MEMS with individual resonant frequencies, which can coexist on the same wafer. While this is a beneficial factor for circuit  applications it is a challenge to design a mechanical BEOL band gap for a wider frequency range [15].

A. SYMMETRY SIMPLIFICATION OF FEM SIMULATIONS
In order to speed up the large scale simulations, depicted in Fig. 2c and Fig. 2d, the impact of a symmetric boundary condition on the resonance was investigated. The simulations for the 2-fin UC were compared for a simplified geometry, with only half of a gate modelled (compare Fig. 2b), and a structure with a full gate and periodic boundary conditions in all lateral directions (compare Fig. 2a). The results of the half gate UC are unfolded at the symmetric boundary, and the resonant frequencies and absolute peak pressures are compared in Fig. 11a for several selected gate lengths for an NMOS device, to the full gate UC. For all orientations, the absolute pressure increases with longer gate lengths, as shown in Fig. 11a, whereas the resonant frequency decreases at the same time. The deviation between the modelled full gate and half gate is small for the orientations (001), (001) 45 and (011) as shown in Fig. 11b. For these orientations, the symmetry plane of the simplification aligns with one of the cubic symmetry planes of the anisotropic silicon. In those instances, both simulations yield almost identical results. However, if the simplification plane of the simulation UC does not align with one of the material symmetries-as is the case for (111)-the results will deviate from each other. In the case of misalignment, the gate experiences additional lateral bending motions along the X-axis, which are caused by an antisymmetric poisons ratio, resulting in a more pronounced shift. Moreover, the structure can also support additional modes, for example with displacements normal to the X-plane, which were suppressed by the symmetric boundary condition. However, all deviations are minor for the investigated wafer directions with the largest deviation in pressure being 14 kPa and in frequency 13 MHz, which justifies the usage of the simplified geometry regardless of the wafer orientation.

B. INFLUENCE OF A FINITE FINGER COUNT
The previous simulations assume an infinite number of parallel fingers due to the symmetric boundary conditions. A real device, however, has a finite number of fingers which are supported by a variable amount of dummy fingers on both sides. Dummy fingers serve only for structural uniformity as the fins are etched away in the region indicated by the dashed green box in Fig. 2d. The UC depicted in Fig. 2d is finite along the X-axis with a perfectly matched layer after the dummy fingers and a symmetric boundary condition on the opposite side in the centre of the RFT cavity. The depicted UC has eight true fingers which are protected by three dummy fingers on each side. The simulations were repeated for a (001) 45 wafer orientation and a gate length of 24 nm. The number of fingers and dummy fingers was swept from 1-10 and 1-3 , respectively. The resulting resonant frequencies for NMOS and PMOS devices are shown in Fig. 12. For a single finger, the resonant frequency is higher when compared to the infinite case (compare Fig. 10). However, for an increasing number of fingers, the resonant frequency assimilates to the infinite case. The number of dummy fingers on the other hand does not influence the resonant frequency. The same behaviour is to be expected in the case of a semi- infinite UC with 14 fins.

C. FINITE CAVITY LENGTH
The impact of the cavity length, i.e. the number of consecutive fins also impacts the performance. All simulations were carried out for an infinite number of fins, however, for a finite cavity length, the performance of the device should degrade as cavity termination plays a more important role. A termination similar to the BEOL reflector could be used, however, many different variations are possible and all should perform worse than the infinite assumption of the cavity. Therefore the infinity cavity assumption, very likely, overestimates the final result.

D. DC-BIASING AND AC-EXCITATION
For all simulations, the common gate is biased at a constant voltage V gate = 0.8 V for NMOS and V gate = 0 V for PMOS devices. The bias conditions for the drive and sense are discussed in the following sections.

1) Drive MOS Capacitor Bias
All previous simulations were carried out for the voltages used by [12]. However, the absolute pressure inside the fin can be improved by optimizing the dc bias and ac amplitude. The results are shown in Fig. 13, for varying dc voltages V mos = V gate − V drive over the MOS capacitor and ac drive amplitude. With an increasing dc voltage |V mos | and an increasing ac voltage, the pressure inside the channel is rising. The larger the voltage difference between the channel of the MOS capacitor and gate, the higher the electro-mechanical force. This trend is limited by the breakthrough voltage of the gate oxide as well as the forward bias condition of the welldiodes. However, for both NMOS and PMOS devices the gate oxide is the limiting factor. The grey region highlights all bias combinations for V gate −(V drive +|v drive |)| > 1 V, which could potentially damage the MOS capacitors. The difference in pressures for the NMOS and PMOS devices is a factor of 1.266 which is caused by the different dielectric permittivity used for the gate oxide. When considering the gate oxide reliability, with a reduction of 50 mV for safety reasons, the optimum bias point for the highest mechanical pressure can be found. A mechanical improvement factor of approximately ten, over the values used by [12], can be achieved by moving the dc bias point to V drive = 325 mV for the NMOS and V drive = 575 mV for the PMOS with an ac amplitude for both to v drive = 475 mV. This bias point produces the largest deformation and is therefore the optimum from a mechanical perspective. For comparability, all the following simulations are carried out at V drive = 40 mV and v drive = 30 mV. The optimized condition is used in Section X for the design of an oscillator circuit.

2) Sense Transistor Bias
The differentially wired sense transistor pair is biased in the linear regime at 200 mV which ensures the opening of a conductive channel. Furthermore, in this regime, the transistor behaves like a voltage-controlled resistor with the source-drain current being linearly dependent on the carrier mobility inside the channel which is explained in the following section.

E. PIEZORESISTIVE EFFECT
For stressed silicon, the energy band structure and thereby the electronic transport properties of the carriers are altered [31], [37]- [40]. The main contribution to the change in mobilityinduced by a resistivity change-is known as the piezoresistance effect [37], [38]. This effect has revolutionized modern CMOS technology as strain engineering opened the path for better-performing transistors with enhanced channel mobility [30], [31]. Early investigations only focused on uniaxial deformation and subsequent mobility enhancements, whereas later the impact of inhomogeneous stress on mobility was studied in a generalized approach [37]- [39]. The anisotropic piezoresistance effect can be described analogously to the anisotropic mechanical properties with a 4 th -rank piezoresistance tensor or a 6 × 6 matrix using the Voigt's notation as [37]- [39]: Its components π 11 , π 12 and π 44 were originally obtained through measurements and are given in Table 2 for n-Si and p-Si.

1) Dependence on Temperature and Doping Concentration
The components in Table 2 were originally measured at 300 K, however, they depend on the channel doping concentration N and temperature T [39]: where P is the piezoresistance factor. It is given by: with the Fermi integral F s and its derivative F s as a function of the temperature and doping dependent Fermi energy E F , the Boltzmann constant k b , and temperature T [39], [41]- [43]. The doping concentration and temperature dependant Fermi energy for n-Si and p-Si is shown in Fig. 14a. At low channel doping densities around 1 × 10 15 cm −3 , which are typical for modern FinFET processes, the piezoresistive effect is enhanced with temperature for both n-Si and p-Si [44]. With larger doping densities, scattering processes increase and the overall mobility decreases [45], [46]. The absolute enhancement, however, is moderate in both cases, with an increase of only 50 % at 200 K for n-Si and p-Si.
As such temperatures are difficult to maintain in a real-world application, all following considerations are carried out at room temperature. Modern CMOS devices are initially strained along the channel direction during fabrication. By adding germanium to the epitaxial source-drain contacts the channel is compressed, effectively enhancing the mobility for PMOS devices. NMOS devices can be improved by adding a stress layer to the device, effectively putting the channel under tension and thereby increasing mobility [31]. This pre-existing strain is not considered in our simulations as only the harmonic response of the system is considered. This is possible due to the linearity of the piezoelectric model where the static part does not contribute to the final result. Using a method like k · p which is not linear at large strain the result might be different, however further analysis is required [29], [47], [48].

2) FinFET Channel Mobility
In order to derive the mobility change in the sense transistor unit-caused by the deformation of the resonant modethe piezoresistance tensor is transformed into the spatial coordinate frame for each wafer orientation with [39], [49], [50]: Here A ij = e i · e j are the direction cosines between the orthonormal bases of the crystal (primed) and the spatial (unprimed) basis with the orthonormal basis vectors e i and e j with i, j run over 1, 2, 3. The absolute direction-dependent mobility variation inside the fins in spatial coordinates can then be determined by [37], [39]: Hence the FinFET channel mobility change from source to drain, using Voigt's notation, is given by ∆µ xx in the spatial frame with the unstrained carrier mobility µ 0 [18], [37], [39]. The mobility along the channel is thus influenced by the longitudinal, transversal and shear stresses acting on the FinFET channel, which are accounted for by (10). Herein the change in channel conductance ∆µ xx is referred to as ∆µ for the rest of this work, as all other directional enhancements are not of interest.

3) Validity of the Model
For cubic semiconductors, the mobility change is linear for small stress up to 200 MPa [37]- [39], [47], [51]. For larger stress the mobility change is non-linear and the piezoresistance model is no longer valid. Since all simulations are carried out at Q = 1000 and the pressure scales linearly with the Q-factor (compare Fig. 9), the highest Q-factor for which the piezoresistance model should still yield sufficiently accurate results can be calculated. The maximum Q-factors, for an upper pressure-limit of 150 MPa, which is well below the confidence region of 200 MPa, are shown in Table 3.  . 2b).
Therefore all simulations, regardless of the device type, wafer orientation, UC and gate length, should offer good accuracy at the reported Q-factor of almost 50 000 [12]. For Q-factors exceeding those values, the stress inside the FinFET channels surpasses 150 MPa and the piezoresistance model starts to overestimate the mobility change.

4) Mobility Change for a 2-Fin UC
Although the ideal 2-fin UC is not compliant with the foundry design rules it provides a best-case approximation, if all fins could be connected individually. From the fitted stress tensor (1) the mobility variation (10) in each fin can be calculated, as depicted in Fig. 15 for an infinite 2-fin NMOS UC on (100) 45 silicon. For this wafer orientation |∆µ/µ 0 | increases steadily with increasing gate length. However, this differs for each transistor type and wafer orientation. In the following the peak values at f R are extracted and plotted for both transistor types and wafer orientations in Fig. 16. For n-Si, depicted in Fig. 16a, the mobility change at Q = 1000 is similar for all four orientations. At small gate lengths, the (001) wafer slightly outperforms all other wafers, with (001) 45 yielding a larger change at longer gate lengths. The absolute enhancement, however, is similar, regardless of the wafer orientations. For p-Si, shown in Fig. 16b, the spread is much larger, with the (001) 45 orientation being the strongest   contender and outperforming all other orientations regardless of the gate length. The mobility changes between 1.6-2.4 % from short to long gate lengths. All other orientations are well below 0.5 % with (001) and (011) offering virtually no enhancement. Hence the focus is on the (001) 45 orientation for the remainder of this work, as it offers the best mobility enhancement independent of the type and gate length. Moreover, due to its beneficial electrical properties, this orientation is most commonly used in standard foundry IC design [27]- [31].

5) Mobility Change with Finite Number of Fingers
The simulation was repeated for the semi-infinite setup (compare Fig. 2d), with a gate length of 24 nm and for the best orientation of (001) 45 . The number of fingers and dummy fingers was varied and the results are shown in Fig. 17. Interestingly the mobility change for a single finger is the same as for the infinite case, albeit at a different frequency, as shown in Fig. 12. With an increasing number of parallel fingers the mobility enhancement decreases. This can be explained as the displacement decreases with a larger number 10 VOLUME 4, 2016 This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. of fingers. As all neighbouring gates expand and contract at the same time they impede each others movement which reduces the overall displacement. The decrease in displacement with added fingers can also be observed in Fig. 2d, with the gates closer to the dummy gates showing less deformation in comparison to the centre gates. The number of dummy gates was swept from 1 to 3, which does not impact the result. The optimal mode shape would be differential between neighbouring fins and also between adjoining gates. In this constellation, they would contract and expand in a chequerboard pattern and not obstruct each other. However, there is no possibility to connect the RFT in a foundry design rule compliant fashion to be able to couple to this mode electro-mechanically.

6) Mobility Change for a 14-fin UC
For the ideal configuration, each fin is connected to a different electric potential, however, for the real 14-fin UC, groups of three fins are jointly connected to the same potential, as shown in Fig. 2c. The overall mobility change in each three fin package is calculated from the sum of the individual fins: With the subscript denoting the fin number indicated in Fig. 2c. For the second group, the mobility change can be calculated from fins 10 to 12, respectively although the absolute mobility change in both groups should be identical with opposite signs, as a result of the linearity of the piezoresistance model. For each fin, a separate stress tensor is extracted and used for the calculation. In resonance, all fins are deformed equally with a phase shift of 180°between neighbouring fins. Therefore the total mobility change in (11) is equal to the change inside a single fin as two fins in each group cancel. Using a more accurate model like the k · p perturbation method, the mobility change is not linear and saturates at different levels for opposing signs of stress which would prevent a perfect cancellation in each group [29], [47], [48]. However, the pressures are in the low MPa range and saturation is not reached. The mobility change for the 14fin UC is shown in Fig. 18. The trends are almost identical compared to the 2-fin configuration with the (001) 45 PMOS device, shown in Fig. 18b, again outperforming all other orientations. However, the absolute mobility enhancement is reduced by a factor of approximately seven compared to the 2-fin UC. This can be explained as only two fins out of the 14-fin UC are actively contributing to the driving and sensing of the resonant mode due to the previously described cancellation. Minor deviations between the 14-fin and 2fin UC can be discerned, which may be attributed to minor differences in the actual mode shape during a frequency domain simulation in the larger UC. In order to achieve the largest mobility enhancement inside the sense transistor units, the PMOS is the preferred choice over NMOS devices. Furthermore, the (001) 45 wafer is on a similar level as the other orientations when it comes to   the NMOS, but outperforms all of them for the PMOS devices. To achieve the best mobility enhancement and thus the biggest ac current, the least amount of parallel fingers is preferential. Not only due to the overall reduced mobility with each added finger, but also the increasing dc current, which increases the power consumption of the device.

F. SENSE FINFET CURRENTS
The resonant mode causes a carrier mobility change in the sense transistors channels. It modulates the current under a constant sense dc bias of V sense = 200 mV, which is shown for a single fin and finger FinFET in both types and at various gate lengths in Fig. 19 [12]. The dc current degrades with longer gate lengths as channel resistance increases. Also, the NMOS FinFET offers a higher absolute current at the same gate length compared to a PMOS device. The scaling with number of parallel fingers for a single fin transistor is shown in Fig. 20. It scales linearly for both types with the number of fingers. From the dc current, with the mobility change VOLUME 4, 2016 calculated from the piezoresistance model in Section IX-E, the ac current running through the sense transistor pair of the 2-fin UC can be calculated to: with the dc current I sense of a single fin FinFET. For the 14fin UC the ac current is analogously derived from the sum of the individual fins in each group with: with the single fin current I dc and the mobility variation from the individual fins. Again, two fins cancel as a result of the linearity at small pressures. Therefore the absolute ac current is accounted for by just one fin out of each group in the UC. From the ac voltage at the drive MOS capacitors and the ac current at the sense transistors the mechanical transconductance [12]: is calculated. Note that effects such as the stress induced shift of the silicon band gap and subsequent threshold voltage shift in the sense transistors as well as velocity saturation have not been considered in this model [52], [53]. Their impact is expected to be negligible as the simulated stress levels are small. Possible modelling approaches have been shown in [54]. It is shown for both FinFET types on the optimal wafer orientation (001) 45 for the infinite two and 14-fin UCs in Fig. 21. The transconductance is almost plateauing for gate lengths up to 40 nm. In this region the increase in mobility and the decrease in current compensate each other, however, for longer gates, the transconductance starts to decrease as the mobility enhancement cannot counteract the current decrease. Again the 2-fin configuration outperforms the 14fin UC by a factor of approximately seven. Considering all displayed configurations a 24 nm gate length is the best over all variants. Those results are scaled to Q = 50 000 with (5) and shown in Fig. 22. At a Q-factor of 50 000 the 14-fin UC achieves a mechanical transconductance in the  low µS regime. The G m can be improved by utilizing more parallel fingers, as the dc current and hereby ac current would increase. However, an important figure of merit to consider is the transconductance per dc current as it is the main contribution to the power consumption of the device. The best configuration possible, without major adjustments to the CMOS process, is the 2-fin configuration with Q = 50 000, where each fin is actively driven without sparse fins inbetween, achieves 100 µS for the NMOS and 565 µS for the PMOS, respectively.
Analogously to Section IX-D the optimal bias condition for the largest transconductance at a sense bias of 200 mV can be found as shown in Fig. 23. The transconductance for the previously optimized bias point is worse than the original bias condition, albeit the increased mobility enhancement. As the drive voltage increases so does the pressure and further the ac sense current, however the latter increases at a slower rate which worsens the transconductance. From a circuit perspective, the best bias condition must be chosen, in accordance with the circuit requirements like signal amplitude and phase-noise. It is in-between the points for the optimal transconductance and the best mechanical performance. A feasibility study for an RFO circuit with the new results at the best mechanical bias point is carried out in the next section.
A discrepancy of two orders of magnitude was found between our simulated mechanical transconductance in com- Given the reported dc currents of the sense transistor at I sense = 120 µA a mobility enhancement of 350 % is required [12]. An enhancement of this magnitude is not reported in literature for silicon. The largest enhancements possible according to prior art, require stress in the low gigapascal range for a change up to approximately 60 % [29], [31], [47], [55]- [58]. However, for all possible CMOS compatible voltage combinations (compare Fig. 13) only low megapascal pressures inside the RFT FinFETs were found. Even with an increased Q-factor of 50 000, the pressure does not surpass 700 MPa for the PMOS and therefore will suffice only for a µS transconductance. Low megapascal values for the RFT were also reported in literature, further substantiating the lower G m [13]. Thus, considering our simulations results and the material properties reported in literature, high values for G m above 1 mS seem impossible to reach by the RFT device.

X. CIRCUIT DESIGN
As already discussed in Sec. I an important application for the RFT resonator can be found in the field of RF circuit design. Therefore, in this section, despite the decreased performance as described in Sec. IX, an exemplary oscillator design is shown, using the RFT as resonator in the oscillator circuit in order to asses the significance of this device for RF circuit design. Thus, performance estimations with respect to phasenoise (PN) and power are discussed in the following sections.

A. OSCILLATOR CIRCUIT DESIGN
Due to the active 4-port nature of the RFT, common RF LC-oscillator solutions like crossed coupled CMOS coresshown e.g. in [59] and implemented e.g. in [60]-can not be instantly used as oscillator core for this type of resonator. The oscillator topology has to serve four main purposes in order to achieve a stable oscillation: 1) biasing of the RFT sense transistors, 2) transformation of the sense current into a voltage signal, 3) amplification of the sense signal to an appropriate drive voltage for the RFT input, and 4) phase correction of the fed-back sense signal. The two requirements 3) and 4) can be formulated by the well known Barkhausen's criteria [59]: with H(jω) as open-loop transfer function of the oscillator structure at a finite frequency ω 0 . Fig. 24 shows the schematic of an oscillator variant in (a) NMOS-implementation and (b) PMOS implementation using a cascode amplifier in the feedback loop to fulfil all requirements. The biasing is mainly set by the transistors M 1 , while the gain of the feedback loop is achieved by the equivalent parallel resistance R p of the inductors L 1 . The feedback capacitor C 1 is dimensioned to resonate the inductance L 1 at the resonance frequency of the RFT to ensure the correct phase of the drive signal is fed back from the sense output. The dc bias of the drive-side is set via the resistors R B . For a first dimensioning of the oscillator, the configuration of the RFT shown in Table 4 is used in accordance with the results presented in Sec. IX. Fig. 25 shows the equivalent circuit diagram of the RFT with its external circuitry corresponding to the parameters shown in Table 4. The oscillator is designed for both MOS-types.

1) Dimensioning
The transistors M 1 are dimensioned to set the drain-sourcevoltage of the RFT sense transistors to 200 mV to ensure a fully developed conducting channel as discussed in Section IX-D. The gate voltage V B2 is set to operate the M 1transistors in saturation with V B2 = 520 mV for the NMOS-RFO (NRFO) and V B2 = 270 mV for the PMOS-RFO (PRFO). The gain of the feedback is determined by the inductor L 1 , more precisely by its equivalent parallel resistance R p . With the parameters for the dc-current and the mobility variation from Table 4, an ac-sense current in the range of nA is to be expected at the output of the RFT device. Thus the gain in the feedback loop has to be quite high in order to provide 475 mV at the drive input. Therefore, the parallel resistance R p , given by [59]: This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.
Vout,n Vout,p  with Q as Q-factor of the metal inductor, L 1 the inductance and f R the fixed resonance frequency of the RFT should be maximized. With the frequency parameter fixed, the geometric properties of the inductor should be chosen in order to achieve the highest product Q · L 1 possible within a reasonable on-chip area of 100 µm x 100 µm. This area constraint is chosen to keep the area consumption of the RFO circuit within the range of common state-of-the-art RF-digitally controlled oscillator (DCO) implementations cf. [61], [62].  Table 4.  For the exemplary dimensioning of the RFO, a symmetrically shaped metal inductor with dummy metals and guard-ring as depicted in Fig. 26 was chosen. The geometric parameters for L 1 as well as its electrical properties are given in Table 5 for an implementation of L 1 on thick top-metals of an RF-metalstack.
The series capacitance in the feedback loop combines two functionalities: 1) decoupling of feedback voltage from dc potential, and 2) phase correction for feedback voltage according to (16). In order to correct the phase of the output voltage of the RFO, the capacitor C 1 has to resonate the head inductor L 1 at the resonance frequency f R of the RFT. For the dimensioning of C 1 , also the drive input capacitance given by C moscap as well as the parasitic capacitance C L of the head inductor itself have to be taken into account. Therefore the complete capacitance contributing to the resonating tank is given by: For the given RFT configuration of Table 4, the drive input capacitance for one drive port (D p or D n ) accumulates to values of C moscap = 3.55 fF for the NRFO and C moscap = 3.47 fF for the PRFO, which are extracted by simulation and proven by measurement of the transistor devices, respec- tively. The needed tank capacitance for the given inductance to hit the resonance frequency f R can be calculated to: The parasitic capacitance of the inductor can be extracted from a circuit simulation to C L = 610.0 aF. In order to achieve the needed C res,goal and therefore fulfil (18), a capacitance C p is placed in parallel to the drive input capacitance C moscap to enlarge the series circuit formed by C moscap and C 1 . The tank capacitance C res then calculates to: C p and C 1 are dimensioned in consideration of the ratio of the capacitive voltage divider formed by C moscap , C p and C 1 : as the loop-gain is degraded by k cdiv . According to this design trade-offs C p and C 1 are chosen to C p = 13.91 fF and C 1 = 321.122 fF for the NRFO and C p = 13.71 fF and C 1 = 321.122 fF for the PRFO. The value of C p is additionally optimized to account for leakage currents through the sense transistor determined by ac-simulation of the oscillator circuit.

2) Open-Loop Simulation
The loop gain of the RFO-implementation is determined by an open-loop ac-simulation of the oscillator circuit depicted in Fig. 24 with the feedback loop opened at the node between the drive input of the RFT and the feedback capacitor C 1 . With the given RFO circuit, the gain-condition for oscillation in (15) can be rewritten to: In Fig. 27  k Gain = 0.477 · 10 −3 . Thus an additional amplifier with a gain of approximately 67 dB is needed in the feedback loop in order to meet the criteria in (15). For a rough worst-case noise-and power estimation a simple inverter-based buffer chain is implemented with a total gain of k Amp = 5938 ≡ 75.5 dB. The buffer chain has a length of nine stages with accoupling and dc-biasing in-between each stage as depicted in Fig. 28. The stages are scaled in their size, starting at minimal transistor dimensioning at the first stage up to a multiplication factor of four at later stages, respectively. For the subsequent circuit analysis and simulation, the additional phase shift induced by the feedback amplifier is neglected. For a complete RFO implementation, a phase compensation has to be integrated. The noise estimation is done by calculating the input-referred noise at each stage of the amplifier using its small-signal equivalent circuit diagram [63]: with n being the stage number ranging from 1 to 9, g m,*,n representing the transconductance of the NMOS-and PMOStransistors in the buffer, k b as Boltzmann constant, T as absolute temperature in K and γ as noise coefficient. The individual noise contributions are summarized using Friis' formula [64]: For the exemplary amplifier implementation of n = 9 stages, the total noise contribution of the amplifier at the output can be calculated to V 2 out,tot = 0.734 nV 2 /Hz at the resonance frequency f R of the RFT. This noise voltage is taken as flat noise contribution over the complete frequency span of interest (1 Hz -100 GHz) for further circuit simulations, in order to get a worst-case estimation for the phase-noise contribution of the amplifier to the overall RFO phase-noise. Effects of flicker-noise in the amplifier are not taken into account by the used flat noise characteristic. For the PRFO the loop-gain can be determined to k Gain = 2.423 · 10 −3 , which enables a decreased gain-target for the feedback amplifier. For the oscillator implementation, the same amplifier is used as for the NRFO circuit. The number of stages is reduced to n = 7 resulting in a total gain of k Amp = 806 ≡ 58.1 dB and a flat noise contribution of V 2 out,tot = 0.013 nV 2 /Hz. The selection of this amplifier topology is solely motivated by its simplicity and expected small on-chip area of the layout. However, the wide noise bandwidth of this amplifier type is not optimal for the narrow-band RFT signal as it introduces superfluous noise in the output signal. Thus a tuned amplifier with reduced bandwidth would be more suitable for the feedback amplifier. This topology uses tuned LC-tanks to achieve a narrow bandwidth. The biggest drawback of these architectures is their larger layout-area because of the tank inductors. Furthermore, to ensure the needed feedback-gain of over 50 dB, multiple amplifier stages are needed. It should be also noted, that, no matter which amplifier architecture is chosen, each additional amplifier stage in the feedback loop of the RFO increases the chip-area of the oscillator device and, due to the low Q-factor of the amplifier-tank, impacts the phase-noise of the complete circuit. Therefore, both main advantages of the RFT as resonant device in the oscillator, namely small size and excellent phase-noise due to the high Q-factor, are negatively impacted by the need of additional amplifier stages in the feedback. Nevertheless, the simulations in the following section, conducted using the inverterbased feedback amplifier give a good basic estimation of the achievable performance of an RFO-implementation. Furthermore, the simulations are also carried out for an ideal noiseless amplifier in the feedback loop, to determine the fundamental limit in phase-noise of the oscillator structure.

3) Circuit Simulation
With the additional amplifier in the feedback loop a safety factor of 2.65 is achieved for closed loop operation of the RFO. In the closed loop circuit, the amplifier is implemented as ideal gain with its noise contribution added through a noise source. For correct operation of the resonator an automatic gain control (AGC) has to be employed between amplifieroutput and RFT-input, as the RFT circuit model used for the simulations does not include any limiting mechanism. The AGC is implemented as a limiter, following a tanh-shape with the upper and lower limits set according to the RFT configuration for the ac-drive voltage reported in Table 4. The RFO phase-noise is simulated with a periodic-steadystate (PSS) simulation followed by a phase-noise simulation. Fig. 29 depicts the simulation results for the phase-noise simulation of the RFO at its fixed resonance frequency f R in closed loop operation with and without the impact of the amplifier-noise. The phase-noise data for lower offsetfrequencies ∆f is approximated by a Lorentzian spectrum as presented in [65]. For the ideal implementation-without the amplifier noise-at an offset frequency of ∆f = 1 MHz from the carrier-frequency the RFO achieves a phase-noise of −67.2 dBc/Hz and −82.0 dBc/Hz, respectively for the NRFO and PRFO.
With a corresponding power consumption of 1.62 mW and 1.24 mW, respectively, the FoM of the RFO for an ideal amplifier implementation calculated by [66]: can be determined to 157 dBc/Hz for the NRFO and to 170 dBc/Hz for the PRFO. Fig. 30 shows the FoM of the RFT in comparison with other state-of-the-art oscillator implementations in the field of mobile communication. This comparison illustrates the big gap in performance between the RFO and common oscillator implementations due to the limited performance of the RFT itself. In the recent publication [13] the RFT has already been shown in combination with a CMOS circuitry in order to form a mmW-oscillator with high spectral purity. However, the pursued modelling approach is incorrect as it assumes a capacitive sensing mechanism. Following from the original publication by Bahr et al. active FinFET sensing is vital. Consequently, the modified Butterworth-Van-Dyke model may not be deployed in the classical sense, as a conversion from voltage domain at the drive to the current domain at the sense is necessary, as highlighted in this publication [14]. Since the authors of the original [12] and the erroneous modelling publication [13] FIGURE 31: Upper, average and lower AKE and LR Q · f limit for silicon MEMS. Values collected from [6], [12], [67], [68].
are affiliated, the controversy of the reported values in both publications may not be disregarded.

XI. CONCLUSION
Our study confirmed the basic working principle proposed by [12]. It was investigated with FEM simulations, which brought insights into the best device configuration from a mechanical perspective. The RFT performs best on a (001) 45 oriented silicon wafer with a gate length of 24 nm. Here the carrier mobility variation inside the sense unit is the largest, in both NMOS and PMOS type devices. Considering a multifinger device the optimum is found to be at a singular gate as mechanical displacement and hereby mobility modulation degrade with an increasing number of fingers. Considering a 14 UC with a Q-factor of 50 000 at the default bias values the device could achieve a theoretical mechanical transconductance of 15 µS for NMOS and 90 µS for PMOS devices, respectively. Although the basic functionality of the devices was confirmed by our simulations, a discrepancy to the reported value of 14 mS was found. Given the uncertainty of the reported Q-factor and the unreasonably high carrier mobility enhancements, the results reported in [12] could not be verified. Nevertheless, the transconductance of the RFT can be improved by different means: Firstly by adding more parallel fingers, which increases i sense . This comes at the expense of a higher power consumption as the gain per additional finger is decreasing while each finger contributes to the overall dc current of the device. Secondly, the G m can be slightly improved by cooling the device to sub-ambient temperatures, which is challenging in a real-world application. Thirdly, an improvement up to a factor of seven can be achieved by enabling single fin contacts without sparse fins in the UC, effectively replicating the results of the 2-fin UC. Single fin contacts also allow for a reduction of the dc current by a factor of three, thereby reducing the power consumption. However, tighter FEOL and BEOL integration on this scale requires extensive lithography evolutions, which stand in contrast to the low reported performance of the RFO especially in the presence of better performing devices. And lastly, by switching to a different technology, incorporating either piezoelectric or ferroelectric materials, the coupling coefficient and therefore the mechanical transconductance could potentially be improved [5], [8], [9], [69], [70]. Nevertheless, a functional RFO circuit concept was designed with an optimized bias condition for both NMOS-and PMOS-variant of the RFT. It was evaluated for several Q-factors, ranging from a lower more plausible Q-factor of 1000 to the reported 50 000 from [12]. The FoM of the oscillator circuit design, which is based on a cascodeamplifier with additional ideal gain in the feedback-loop, achieves values for a Q-factor of 1000 of 153 dBc/Hz for the NRFO and 170 dBc/Hz for the PRFO, which is quite low compared to other state-of-the-art RF-designs (compare Fig. 30). This makes the RFT unattractive for competitive RF-circuit design for frequency generation. Furthermore, the authors of [12] fail to substantiate the claim of the astonishingly large Q · f product of 1.57 × 10 15 . Considering all damping mechanisms, like the Akhiezer effect (AKE) and Landau-Rumer (LR) attenuation, as well as the thermoelastic dissipation (TED) and the PnC, the total Q-factor of the RFT is limited by the Matthiessen's rule [67], [68], [71]- [73] 1 to the smallest Q-factor of all involved loss mechanisms. For well designed high frequency devices the losses by TED are negligible [72], [74]. For frequencies ω τ τ l < 1, where τ l = 67.3 ps is the relaxation time of longitudinal waves in silicon along the gate direction 110 , the AKE is expected to be the dominant attenuation source [67]. It limits the Q-factor to the phonon-phonon attenuation limit [75], [76]. Here the Q · f product is given by [77], [78] Q AKE · f = ρc 2 l c 2 d 6πγ 2 kT where the Debye velocity [74], [75] is calculated from the longitudinal and transversal sound wave velocities in silicon along the gate direction 110 with c l = 9130 m s −1 and c t = 4672 m s −1 [75]. The Grüneisen parameter γ varies between 0.17-1.5 with the commonly used average γ avg = 0.51, however, it is challenging to assess this quantity accurately [67], [71], [72], [75]. Moreover k = 130-148 W K −1 m −1 is the thermal conductivity and T = 300 K the temperature [77], [78]. The AKE, as plotted in Fig. 31 for the upper and lower limit as well as the average, impose the fundamental limit of the frequency product by means of quantum mechanical phonon scattering, which solely relies on the involved materials [67], [79], [80]. High performing MEMS devices in that realm rarely exceed the average Q · f product as shown for selected silicon MEMS.
For resonators with frequencies in excess of ω τ τ l > 1, the Q · f product is limited by the LR attenuation. In this region the wavelength is smaller than the mean free phonon path causing an acoustic attenuation proportional to ω as a result of three-phonon interactions [74]. Here the Q·f product [74], [76] Q LR · f = 30ρc 5 d 3 increases linearly with frequency. Again, top performing MEMS rarely surpass the average LR attenuation. However, although the MEMS are limited by LR and may thus surpass the AKE in this frequency range, Q · f above the AKE are unreported [71]. Nevertheless the RFT approaches the upper limit, reporting the best performance to the current date [12]. This value however, is improbable as the performance of the BEOL PnC is questionable in the presence of anisotropic copper which strongly alters the band gap formation [15]. Furthermore, the RFT is built out of several different materials, including high porosity SiCO:H in close proximity to the cavity, which should worsen the theoretical upper limit of the Q·f product. Regardless of the validity of the Q-factor, our simulations, including all assumptions and considered effects shown in Sections IV to IX, could not confirm the reported transconductance. It is calculated to be three orders of magnitude lower than reported making the device ineffective for IC design.
HARALD PRETL (S'97-M'01-SM'08) received the Dipl.-Ing. degree in electrical engineering from the Graz University of Technology, Austria, in 1997 and the Dr. techn. degree from the Johannes Kepler University (JKU) in Linz, Austria, in 2001, for his work on first-generation directconversion transceivers for 3G. From 2000 to 2011 Dr. Pretl has worked at Infineon Technologies as Director and Senior Principal Engineer, and from 2011 to 2019 at Intel as Senior Principal Engineer contributing to several generations of cellular RF transceivers and mobile communications platforms, spanning from 2G to 5G, as analog circuit designer, project lead and RF systems architect. Since 2015 he is a full professor at the Institute for Integrated Circuits (IIC) at the JKU, Linz, where he is heading the Energy-Efficient Analog Circuits & Systems Group. Harald Pretl was a member of the technical program committee (TPC) of the ISSCC in 2010-2012 and has published more than 80 papers at international conferences and journals in the area of RF transceivers and analog circuits, in addition to more than 25 issued or filed patents. His current research interests are focused on cellular transceivers, wireless sensor networks, micro-power RF SoC for medical applications, and mm-wave circuits for 6G and advanced radar. He is a co-recipient of the first place in the 2015 MTT-S PAWR student paper competition, the 2019 ReSMiQ best paper award at the IEEE NEWCAS conference, the 2019 APMC student prize, and an 2021 ISCAS best paper award. He is also a co-recipient of the Intel Achievement Award in 2019. He is a member of the Austrian Electrotechnical Association (OVE). VOLUME 4, 2016 21 This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/ACCESS.2022.3182695