Impact of P/E Stress on Trap Profiles in Bandgap-engineered Tunneling Oxide of 3D NAND Flash Memory

The quantitative characteristics of traps created in the bandgap-engineered tunneling oxide (BE-TOX) layer and block layer after program/erase (P/E) stress-cycling in a 3D NAND flash memory were investigated. The trap spectroscopy by charge injection and sensing technique was used to obtain the distribution of traps in these layers. In the BE-TOX layer, significant traps were generated at 1.3 eV in the nitrogen-doped layer (N1) and increased by 48% in the fresh cell after P/E stress-cycling. The H bonds in the N1 are more likely to break during the stress-cycling and create neutral ≡ SiO● traps. In the block layer, however, trap generation was negligible after stress-cycling.


I. INTRODUCTION
The three-dimensional (3D) NAND flash memory has various applications, including consumer electronics, autonomous vehicles, and data centers, owing to its low bit cost and high storage density [1][2]. Thus, multilevel operation and cell scaling have been intensively developed for the 3D NAND flash memory to increase its density and reduce its manufacturing cost. These developments require a considerably tighter distribution of the cell threshold voltage (VTH) and high-immune and retention characteristics. A bandgap-engineered tunneling oxide (BE-TOX) layer and block layer have been introduced to enhance the program/erase (P/E) speed and retention reliability, replacing the conventional SiO2 layer [3][4].
The performance of the 3D NAND flash memory is limited by the number of P/E operations that create defects in dielectric layers [5][6]. Previous results described trap generation based on stress conditions and provided minimal information on origin of traps created in a cell [5][6]. A detailed analysis of trap generation in dielectric layers is crucial to develop a high-efficient barrier structure and enhanced memory performance.
Herein, we characterized the traps generated in the BE-TOX layer and block layer of a 3D NAND flash memory after P/E stress-cycling with the help of technology computer-aided design (TCAD) simulation and the trap spectroscopy by charging injection and sensing (TSCIS) technique [7][8][9]. First, simulation was performed to match the measured characteristics and obtain the relevant electric field for the trap spectroscopy. Second, trap profiles were qualitatively designed in terms of energy using TSCIS. Lastly, a quantitative model was applied to correlate trap generation with the stress condition and process quality. Fig. 1(a) shows a schematic of the 3D NAND flash memory consisting of a dielectric filler, a poly-Si channel (CH), BE-TOX (O1/N1/O2) layer, charge trap layer (CTL), and block layer (BOX/HK). Fig. 1(b) shows the retention characteristics of fresh and cycled cells at 25 ⁰C. For the P/E stress-cycling, the program (18 V, tPGM= 50 μs) and erase (-17 V, tERS= 1 ms) biases were repeatedly applied to the gate electrode for 1000 cycles. The threshold voltage variation (VTH, LOSS = VTH.time -VTH.0sec) was caused by the vertical and lateral charge losses. The worse retention of the cycled cell was attributed to the vertical charge loss due to trap generation in the BE-TOX layer after P/E stress-cycling [5,10]. Fig. 1(c) shows the ∆VTH, LOSS with various gate voltages in a programmed state for fresh and cycled cells. A positive gate bias preferentially accelerates the charge loss through the gate-side (GS) region, whereas a negative bias enhances the charge loss through the channel-side (CS) region. A higher ∆VTH, LOSS with a negative bias indicates that the trap generation in the BE-TOX layer is more severe than that in the block layer and the trap-assisted tunneling and detrapping toward the CS region could be the dominant mechanism. Fig. 2 shows the change of VTH as a function of program time and compares it with the TCAD simulation; the densitygradient model was included to consider the quantum effect. The doping-dependent mobility model and an incomplete ionization model were used to calibrate the simulation and measurement data. In addition, the Shockley-Read-Hall generation-recombination model was employed to explain the capture and emission of carriers. The calibrated program speed data were well matched to the measured ones. The parameters used for the simulation are listed in Table 1. TCAD simulation was performed to obtain the energy band and relevant electric field, which were used to extract the trap The trap energy level and trap depth were extracted by varying charging voltage (VCHRG) and charging time (tCHRG). The VCHRG and the tCHRG determine the trap levels from the EC of N1 and the distance from the channel interface based on Shockley-Read-Hall (SRH) statics and WKB approximation (TWKB) for tunneling probability [7][8][9]. During the TSCIS charging period, the electric field in the dielectric layer was continuously changed by the electrons captured in the trap. These trapped charges also affected the tunneling probability and capture rate of the trap. Thus, the electric fields in the dielectric layers were recalculated using the numerical Poisson solver considering the captured electrons.

B. TSCIS MEASUREMENT AND SIMULATION
The TSCIS charging condition should be carefully chosen to avoid any trap generation during the charging period. Negligible differences were observed in fully discharged VTH initial state VTH and the subthreshold swing values with VCHRG up to 6.1 V and tCHRG up to 10 3 s for channel-side TSCIS (CS-TSCIS), which confirmed a negligible trap generation in the BE-TOX layer and at the O1/CH interface during the charging period [20]. Gate-side TSCIS (GS-TSCIS) also observed minimal trap generation with VCHRG up to -6.5 V.     3 shows the measured VTH shifts (∆VTH, CHRG) as functions of VCHRG and tCHRG for fresh and 1000-cycled cells, respectively. Initially, the ID-VG curve of the fresh cell was measured, and then VCHRG was applied to the gate during 0.01 to 2000 s. At the end of a charging time, the constant Vsense was biased to measure the drain current, which was transferred to ∆VTH, CHRG based on the initial ID-VG curve. Before increasing VCHRG, VG was grounded to relax electron traps. In GS-TSCIS, the same procedure was performed except that the negative VCHRG was applied to the gate, as shown in Fig. 3(c) and (d). The insets in Fig. 3(a) and (c) show the profiled regions that were determined by VCHRG and tCHRG in TSCIS technique. Fig. 4 shows the trap maps obtained via the CS-TSCIS technique. The energy level of the trap was calculated from the conduction band (EC_N1) of N1. The red-yellow region shows the maximum trap density for a fresh cell. Notably, as P/E stress was applied, the trap density (DT) with the energy levels of 1.3 to 1.5 eV increased in the N1 region, and negligible trap creation in other O1/N1 regions was observed. Fig. 5(a) shows the average trap density (DT_AVG) as a function of the distance from the O1/Poly-Si interface and the energy from EC_N1. The energy level was extracted by applying Gaussian fitting curves. For a fresh cell, the extracted peak value of DT_AVG was obtained as 2.4 × 10 18 cm -3 ·eV -1 with a 1.34 eV energy level by applying Gaussian fitting curves. The DT_AVG value was very similar to that of previous noise measurement results [21][22]. It can be seen that the P/E stress-cycling could increase the trap density and slightly change the energy level of the peak trap density.

III. RESULTS AND DISCUSSION
There are two main electron traps in a nitrogen-doped oxide (N1): ≡ Si 2 N • and ≡ SiO • [23]. The former is a shallow trap with an energy level of less than 1.0 eV from EC_N1, and the energy level of the latter is typically in the range of 1.3 to 1.9 eV from EC_N1 [23][24][25]. The energy level of the peak trap density is similar to that of ≡ SiO • , as shown in Fig. 5(a).
According to the following reaction, the trap generation in a stressed cell could be the break of a hydrogen (H) atom bound to ≡ SiOH [23,26].
≡ SiOH → ≡ SiO • + H (1) Fig. 5(b) shows the variation of ΔDT_AVG, defined as (DT_AVG,1000cycles -DT_AVG,fresh)/DT_AVG,fresh, with P/E stress. With 1000 cycles of P/E stress, the peak ΔDT_AVG of 48 % at 1.3 eV is obtained, which rapidly decreases as the trap level increases. The majority of the P/E stress-induced traps could be ≡ SiO • , located at approximately 1.3 eV using (1), and a significant cause of the degradation of retention in a stressed cell. Fig. 6 shows the variation in the accumulated total trap density (NT,N) as a function of the number of P/E cycles. Initial NT was obtained by integrating the Gaussian profile of DT_AVG. The tunneling current density (J) during P/E stresscycling was obtained using TCAD simulation. The P/E current densities through the BE-TOX layer became large as the P/E cycle increased, as shown in the inset of Fig. 6. Also, the J decreases continuously as time evolves in a P/E cycle.  CHRG as a function of tCHRG in (a) a fresh cell and (b) a 1000 cycled cell for CS-TSCIS, and in (c) a fresh cell and (d) a 1000 cycled cell for GS-TSCIS.

FIGURE 4. Trap spectroscopy in the BE-TOX layer of (a) a fresh, (b) a 500-cycled, and (c) a 1000-cycled cell.
This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. To correlate the trap generation in the BE-TOX layer with the P/E stress-cycling, the injected charge fluence ((Qinj,N(l)), the newly created traps (∆NT,N(l)) and the NT,N for N th P/E cycle were modeled under current stress conditions as follows [27,28]: , ( ) + , −1 ( ) (4) where l is a counter from l= 0 to l= L= tPGM/∆t in a P/E step, N is the number of P/E cycles, Kpr is a constant depending on the dielectric thickness and processing conditions, Jstress,N is the simulated tunneling current density flowing through the BE-TOX layer,  and  are the dielectric quality evaluation parameters.
For the program and erase stress, αpr = 0.6, βpr = 0.23, and Kpr = 1.2×10 21 and αer = 0.50, βer = 0.65, and Ker = 3.93×10 21 were extracted, respectively. These values were very similar to those found in previous results [27,28]. Fig. 7 shows the trap maps with P/E stress for the high-k dielectric in the blocking layer. The DT value of approximately 10 18 cm -3 ·eV -1 was obtained in a fresh cell. The extracted traps were almost uniformly distributed along the trap energy axis. As shown in Fig. 7(b), the P/E stresscycling did not affect trap generation in the high-k blocking layer.

IV. CONCLUSION
After P/E stress-cycling, the trap generation in both the BE-TOX and block layers was characterized using the   TSCIS technique, revealing that traps in the BE-TOX layer were intensively generated at 1.3 eV in N1 and increased by 48% in the fresh cell. Among several trap candidates in the nitrided layer, the neutral ≡ SiO • trap could be a major one considering the energy from the trap profiles. The quantitative model of trap generation was also evaluated based on the stress conditions and quality of dielectric layers. In the blocking layer, negligible trap generation was characterized with the P/E stress-cycling.