A New Six-Level Transformer-Less Grid-Connected Solar Photovoltaic Inverter With Less Leakage Current

This paper presents a novel structure of the transformer-less grid-connected inverters. The proposed inverter is combined with six power switches and two power diodes which can generate six voltage levels at the output. Furthermore, the proposed inverter can overcome the leakage current issue in the photovoltaic (PV) system, which is the major problem in grid-tied PV applications. Additional significant features include- reduced filter size, lower total harmonic distortion (THD) of the injected current to the grid, and voltage boosting ability. Moreover, the proposed topology provides full reactive power support to the grid. A control strategy is designed and implemented to provide a voltage boost ability without using any additional dc-dc boost converter. Finally, the performance of the proposed inverter is validated by the 770 $W$ laboratory prototype.


I. INTRODUCTION
Owing to the massive shortage of conventional fuelbased sources, environmental pollution, and government power regulation incentives, the use of renewable energy sources (RES) like photovoltaic (PV) modules has been more attractive in the novel power conversion systems. In the lowscaled single-phase grid-connected topologies, a PV panel can be tied to a power converter directly with a single power conversion stage or two stages. Single-stage power conversion systems prevent wasting extra energy and power losses [1], [2].
On the other hand, inverters without transformers are very important for achieving the proper voltage gain from The associate editor coordinating the review of this manuscript and approving it for publication was Jahangir Hossain . relatively low solar panels and providing the power grid's proper voltage peak. The grounding issue point is the main challenge in developing a property transformer-less grid-connected inverters.
Higher efficiency, lower cost, proper power density, and meeting some grid code necessities of numerous distributed generation systems are the merits of the transformer-less inverters over the transformer-based systems [1]- [8]. Voltage fluctuation across the stray capacitor, which emerges between the photovoltaic (PV) panel and the ground, generates the leakage current [9]- [11]. The mentioned injected leakage current produces a noisy dc offset to the grid, so it is essential to control the same magnitude. Variation in common-mode voltage (CMV), which emerges across the stray capacitor, leads to leakage current. So, by keeping the common-mode voltage constant, the leakage current can be mitigated. For the constant CMV, a bipolar pulse width modulation (PWM) method or half-bridge (HB) inverter instead of the full-bridge (FB) inverter could be used [5], [12], [13]. In [9], the CMV is almost fixed under any condition of loading performance; however, due to the low quality of injected power, the output voltage is not able to face strict grid code standards.
Furthermore, an additional front-end boost converter in HB-based inverters leads to high cost, low power density, and a less efficient system. The unipolar PWM method can mitigate dv/dt, filter size, and power losses, but it causes CMV variation with the switching frequency. Variable high-frequency CMV emerges by producing a zero voltage level at the inverter's output [14], [15]; however, to remove the leakage current and electromagnetic interference (EMI), the PV module should be disconnected from the ac grid during the freewheeling mode. In order to achieve this goal, H5 [16], optimized H5 (OH5) [17], various families of H6 [18], [19], and HB-ZVRB [20] have been presented by adding some additional switches to the conventional FB topology and isolation between the photovoltaic source and the grid in dc or ac side during the freewheeling period. In [21], the highly efficient and reliable inverter concept (HERIC) topology was presented to reduce the power loss and the leakage current. This structure generates zero voltage level at the ac side through a bidirectional switch and therefore not only the power loss reduces but also improves the reliability of the system. However, the HERIC topology cannot control the reactive power. The constant CMV across the parasitic capacitors can be achieved using the neutral point clamp (NPC) or active neutral point clamp inverters [22]- [25]. The central point of two capacitors connected across the PV cells is linked to the neutral/ground terminal of the grid leads to a constant common-mode voltage at each interval of time. But the main disadvantage of this technique is the additional dc-dc topologies requirement to increase the output voltage range to connect with the ac grid [13]. The use of those inverters based on common grounded topologies play an important role to maintain the system from the leakage current issue [26]. Two bipolar-PWM-based transformer-less inverters have been introduced inverters by employing the extra inductors common grounding method [27], [28]. When the solar cell's negative terminal is directly linked to the grid's null, the total CMV is appropriately bypassed and presented as a virtual dc link [29]. Recently, to further improve the quality of the injected current to the grid by these common grounded transformer-less inverters, some modified versions of the three-level and fivelevel based topologies have been introduced, which are based on the flying capacitor (FC) and switched-capacitor (SC) structures [2], [30]- [32]. In [30], [31], to balance the voltage of the FC cell, the additional charge balancing control circuits should be applied.
Applying the switched capacitor strategy to the conventional gird-tied inverters can provide a voltage boosting capability while the charging and discharging operation of the utilized capacitors can be inherent [2], [32].
Another classification of the SC-based MLI topologies are the common grounded inverters that have received more attention from researchers due to CMV reduction feature. In the common grounded inverters, the null of the grid is directly tied to the negative terminal of the input dc source. To establish the common point between the ac side and dc side of the inverter, the presented topology utilizes an electrolytic capacitor to create the concept of virtual dc-bus. Note that, during both positive and zero levels the virtual dc-bus is charged to the input voltage. By reversing the polarity of the virtual dc-bus the negative voltage level will be generated. It should be noted that in the negative half cycle of the output voltage waveform the input dc power supply is not used to supply the output load. So that, the negative polarity of the input dc source can remain tied to the null of the power grid. In all of the common-grounded SC-based structures, the input dc source is isolated from the output in the negative half cycle. Also, the output voltage levels in the negative half cycle are created only by discharging the switched capacitors. The ripple voltage of switched capacitors can increase the harmonic distortion of the output voltage waveform in the negative half cycle.
Recently, some transformer-less common grounded grid-tied inverters eliminate leakage current and provide voltage boosting feature during single-stage power conversion [33]- [38]. Also, a new switched capacitor-based common grounded grid-tied five-level inverter has been presented in [39]. This topology can operate with a dynamic voltage conversion and a wide input voltage range. Another kind of SC-MLI topology that integrates SC with T-type inverter [40] NPC-based inverter to overcome to dc offset problem during reducing high-frequency CMV has been presented in [41]. A new SC-based five-level inverter is presented in [42]. Note that, this topology cannot generate the zero-level of the output voltage waveform. Ref [43] presents a new switched capacitor seven-level NPC-based by adding a flying capacitor to the five-level switched-capacitor NPC-based presented in [41]. Also, some switched-capacitor NPC-based topologies are introduced in [44] and [45]. The NPC-based or T-type switched-capacitor inverters provide the best performance compared with other structures. The mentioned topologies utilize a single dc source for producing a seven-level output voltage in both single-phase and three-phase states. The feature of high-frequency CMV reduction without any change in the output voltage waveform is very important. This paper introduces a novel NPC-based transformer-less grid-connected inverter using the switched-capacitor concept, which provides a six-level voltage through a simple structure. The attractive merits of the proposed inverter are boosting output voltage, reducing leakage current capabilities, filter size, and total harmonic distortion (THD) in grid-connected PV applications. The proposed grid-tied inverter's main goal is to reduce filter size and total harmonic distortion (THD) in grid-connected PV applications. Moreover, the leakage current issue is the main problem in grid-tied PV applications,  which is solved in the proposed inverter. Indeed, the leakage current on circuits causes unnecessary and irregular tripping and also mainly leads to a rise in voltage on accessible conductive parts; thus, it should be solved.
The paper is organized as follows: Section II shows the circuit topology of the proposed grid-connected inverter. Section III discusses the operational principles of the presented inverter. Analyses of the proposed inverter are presented in Section IV. Section V introduces a control scheme and power loss analysis and compares the proposed topology with existing transformer-less grid-connected inverters presented in Section VI and VII, respectively. To validate the proposed grid-tied inverter's performance, the experimental results are presented in Section VIII and finally concludes is in Section IX. Fig. 1 shows the proposed inverter's circuit schematic, consisting of two power diodes, four capacitors, and six power switches. V dc is the input voltage, and the switches S 1 , S 2 , S 3 , and S 4 are power switches that are located on two legs, and the S 5 is the bi-directional power switch. The proposed inverter consists of two switch-legs. The first switch-leg includes switches S 1 , S 2 , and the second switch-leg consists of S 3 and S 4 . The capacitors C 1 and C 2 are connected to the input source, which are charged to 0.5 V dc spontaneously. Also, C 3 and C 4 are associated with the second switch-leg and are charged to V dc .

II. CIRCUIT TOPOLOGY OF THE PROPOSED INVERTER
The bidirectional switch S 5 is located between the midpoint of C 1 , C 2 , and the first leg. The operation of each switching state, diode, and charging/discharging modes of the capacitors is mentioned in Table 1. In this table, ''1'' and ''0'' show the switches and diodes' in on and off-state, respectively. Also, the non-connecting, charging, and discharging states of the C 3 and C 4 are indicated by ''-'', ''↑'' and ''↓'', respectively.

III. OPERATIONAL PRINCIPLES OF THE PROPOSED INVERTER
As indicated in Fig. 2, the proposed grid-connected inverter has six operational modes to generate six different voltage levels (±0.5 V dc , ±1 V dc and ±1.5 V dc ). This figure shows the reactive current path, active current path, and capacitor charging path with green, red, and blue dashed lines. Since C 1 and C 2 in the first leg are linked to the input voltage, they are charged to 0.5 V dc (V C1 = V C2 = 0.5 V dc ) in the whole of the operational modes. The corresponding switching states are discussed in detail as follows: ModeI: In this mode, the capacitor C 3 in the second leg is charged to V dc , and C 4 is disconnected as D 2 is reversed biased, as seen in Fig. 2(a). Furthermore, C 1 supplies the grid power, and 0.5 V dc is developed at the output by turning on switch S 3 . The related equations of this mode can be written as: Considering Fig. 2(a), the power switches S 1 , S 4, and S 5 are in off-state, the voltage stress of these switches can be calculated as follows: ModeII: In this mode, the C 3 is discharged to supply the grid power as shown in Fig. 2(b). However, C 4 at the end of the mode is connected to start charging in the third operational mode. The output voltage in this mode can be written as: During this operating mode, the power switches S 1 , S 2, and S 4 are in Off-state. The voltage stress of these power switches can be given as follows: ModeIII: As illustrated in Fig. 2(c), the series connection of C 1 and C 3 supply the power to the grid. By turning on S 1 and turning off S 5, voltage level 1.5 V dc is generated at the inverter output. The equation of this mode can be written as: The voltage stress of the involved switches of this mode can be calculated as follows: ModeIV: In Fig. 2(d), C 3 is disconnected, and C 4 is charging. Besides, grid power is provided by C 2 in this mode. According to Fig. 2(d), -0.5 V dc is provided at the output by turning on switch S 4 . The related equations of this mode can be written as: ModeV: This operational mode of the proposed inverter is illustrated in Fig. 2(e). Considering this figure, the stored energy of the C 4 is discharged to the grid. Moreover, by turning off S 1 and turning on S 5 output voltage reaches -V dc . Mode VI: This operation mode of the proposed inverter is shown in Fig. 2(f). During this mode, the switches S 2 and S 4 are in on-state. By turning on the switch S 2 , the capacitor C 3 is connected to the input source in series. Therefore, the capacitor C 3 is in charging mode and C 4 in discharging mode. Thus, a series connection of C 2 and C 4 supply the power to the grid. In this mode, the output voltage level can be obtained as: So, the output voltage of the inverter can be written as: Also, during this operational mode, the switches S 1 , S 3 , and S 5 are in off-state; therefore, the voltage stress of switch S 3 can be calculated as follows: From the above-obtained equations, it can be understood that the maximum blocked voltage (MBV) of the switches and total standing voltage (TSV) of the proposed inverter can be written as: (17) Besides, the duty cycle of the different operational modes of the proposed topology is calculated in (18) to (27). The positive half cycle of the output voltage waveform of the inverter and grid voltage with three operational zones (Zone 1 ∼ Zone 3) of the inverter is depicted in Fig. 3. Regarding this figure, the control technique of the proposed topology can be provided. The maximum switching frequency of the inverter is f S , and also the sampling frequency is f SA . It should be mentioned that the sampling frequency is two times the maximum switching frequency. By implementing the inductor volt-second balanced (IVSB) law to the inductor's voltage in a full operation period (T S ), the switching duty cycle of the three mentioned zones of the inverter is calculated in (18) to (27). It should be noted that, V out and V g are the output voltages of inverter and grid, respectively. The equations for voltage and current of the grid can be written as (18) and (19). Zone 1: Considering Fig. 3, the inverter's output voltage is between −0.5 V dc and 0.5 V dc during this zone. Therefore, by applying the IVSB principle for the voltage across the output inductor during zone 1 for the switching period, the switching duty cycle of the inverter (d 1 ) can be obtained as (20)- (22).
By substituting (18) in (21), the duty cycle of zone 1 can be written as: The average value of d 1 (t) can be calculated as follows: Zone 2: Regarding Fig. 3, it can be seen that during zone 2 the output voltage of the inverter is between 0.5 V dc and V dc . By applying the IVSB rule for the voltage across the inductor filter during zone 2 for the switching period, the switching duty cycle of the inverter (d 2 ) can be calculated as (24)- (26).
Considering (22), the equation (26) can be rewritten as: The average value of d 2 (t) can be calculated as follows: Zone 3: As shown in Fig. 3, in zone 3 the inverter's output voltage is between V dc and 1.5 V dc . Therefore, by using the IVSB law for the voltage across the inductor filter during zone 3 for the switching period, the switching duty cycle of the inverter (d 3 ) can be written as (28)-(29).
The average value of d 3 (t) can be calculated as follows: Considering (25), the equation (29) could be written as: The equations of t 1 and t 2 can be obtained as:

IV. ANALYSIS OF THE PROPOSED INVERTER A. LEAKAGE CURRENT AND THE VOLTAGE ACROSS THE STRAY CAPACITOR
According to Fig. 1 and 2, the voltage across the stray capacitors is equal to the voltage across C 1 and C 2 . Therefore, the voltage across stray capacitors is calculated in the following: where I mg is the maximum value of the grid current waveform. It is to be noted that (ω = 2πf g ) in equation (36). According to equation (34), the voltage across the capacitor is combined of ac (ripple) and dc component.
calculation of the leakage current as given in (37). By putting equation (36) into (37), the expression of the leakage current can be written as: As given in equation (38), the leakage current is not affected by the dc component but is affected only by the ac component. Considering that C pv1 and C pv2 are smaller than C 1 and C 2 , and because the ac element fluctuates with grid frequency, the leakage current in the proposed grid-tied inverter is negligible.

B. DESIGN OF PASSIVE UTILIZED CIRCUIT COMPONENTS
In this section, the capacitance of the capacitors and output inductor filter is calculated. The capacitors C 1 and C 2 regarding equations (34)-(36) and considering maximum voltage ripple across C 1 and C 2 in the first leg (| V C1 | = | V C2 |), are calculated as: The capacitance values of capacitors (C 3 and C 4 ) in the proposed inverter are calculated based on each capacitor's longest discharging cycle (LDC). The LDC happens during the positive and negative half-cycles for utilized capacitors C 3 and C 4, respectively. The peak discharging value of each capacitor during the mentioned LDC can be calculated as: It should be noted that the output voltage waveform has only odd order of harmonics. So that, the LDC for capacitors (C 3 and C 4 ) will be the same. Regarding Fig. 3, if t 2 ≤ t ≤ T 2 − t 2 the current passing through the capacitor C 3 will be equal to injected grid current (i g (t)). Therefore, the equation (41) can be written as: (41) The value for capacitor C 3 can be obtained as follow: where, V is the maximum permissible value of the capacitor C 3 voltage ripple, and it can be defined as: With respect to equations (42) and (44), the value of capacitor C 3 can be written as: Also, the capacitance of capacitor C 4 is calculated in the same way as capacitor C 3 . The current of the output filter inductor can be calculated as follows: Also, the current ripple of the inductor can be calculated as: Therefore, using (29), the final value of L f can be calculated as: (48) The value of L f for maximum value of the inductor current ripple could be calculated as:

V. CONTROL SYSTEM OF THE PROPOSED INVERTER
A peak current controller method is used to trigger the gate of power switches to control both active and reactive powers.
The control system block diagram of the proposed grid-tied inverter is illustrated in Fig. 4. A phase-locked loop (PLL) as the synchronous block is utilized to find the local grid's proper amplitude and phase, as shown in Fig. 4. In the suggested control system, a filter-based phase-locked loop system like second-order generalized integrator (SOGI) [46] or enhanced phase-locked loop (E-PLL) [29] is suggested.
Regarding Fig. 4, the unit generates the peak value of the injected current into the grid (I mg ), which depends on the reference value of active and reactive power injected into the grid. Also, by block tan −1 Q ref P ref , the value of the phase angle of the injected current to the grid is produced. The PLL unit generates the angular velocity of the grid. Also, by multiplying the peak value of injected current to the grid in the unit sin (ωt − ϕ), the reference value of injected current to the grid (i ref ) is generated. Finally, the reference value of injected current to the grid, the injected current to the grid, and the grid voltage are sent to the current controller block, which generates the required PWM gate pulses of the power switches of the proposed inverter. Note that, in the control system the required amplitude and phase angle of the reference current (i ref ) are calculated according to the reactive and active power values. The measured instantaneous slope of the inductor L f current, named L-type filter, is compared with the current waveform reference. In the current controller unit, the switching pattern of the implemented power switches has been achieved by comparing the reference current with the measured grid current. The reference and measured current waveforms with the generated gate pulses have been illustrated in Fig. 5. Considering this figure, the performance of the proposed inverter is affected by the polarity of the instantaneous value of the grid voltage (v g ) and instantaneous value of the injected grid current (i g ).
In addition, Fig. 6 shows the logic-based circuit diagram of the applied peak current controller for generating the gate pulses of switches. Also, Table 2 shows the applied peak current controller operation pattern of switching pulses. To investigate the accurate performance of the applied control system, a number of simulation results have been performed in MATLAB/Simulink software and are shown in Fig. 7 and Fig. 8. Fig. 7(a) and Fig. 7(b) show the output voltage along with the injected current to the grid under applied current step change at unity PF and lag PF, respectively. Based on these figures, as the amplitude of injected current to the grid increases from 2.5 A to 5 A the injected power increases from 380 W to 770 W in Fig. 7(a) and 380 VA to 770 VA in the Fig. 7(b). Fig. 7(c) and Fig. 7(d) illustrate the output voltage and injected grid current under PF changing such as unity PF to lag PF and lead PF to lag PF, respectively. Considering these figures, the amplitude of injected current to the grid is constant. So that, the amplitude of the injected power to the grid is constant. The simulation results of the grid voltage and injected current to the grid waveforms are presented in Fig. 8. Figs. 8(a) and (b) show that by applying the step change in the amplitude of the injected current to the grid (from 2.5 A to 5 A) the injected power to the grid can follow this step change under unity PF and lag PF. Furthermore, Fig. 8(c) and Fig. 8(d) indicate the grid voltage and injected grid current under PF changing such as unity PF to lag PF and lead PF to lag PF, respectively. With respect to Fig. 7 and Fig. 8, it can be concluded that the applied control system can performed good under different step changes such as amplitude step change and PF changing.

VI. POWER LOSS ANALYSIS OF THE PROPOSED INVERTER
Here, switching and conduction power losses of the utilized power switches are calculated by analyzing their current stresses. To calculate the power losses of the proposed inverter, the injected current to the grid can be considered as Fig. 9(a) and can be written as follows: To calculate the RMS current of the grid in each of the operating intervals, Fig. 9 The times t 1 and t 2 can be calculated from (32) and (33). The number of switching times from moment zero to π 2 can be calculated as follows: where, T s is the switching period time and can be written as: where, f s is the switching frequency of the proposed inverter.
Because each switch has different losses in different operating intervals, so the power losses of each switch in different intervals are calculated separately. The current equation of switch S 3 during interval (0 , ωt 1 ) in the positive half cycle is calculated as follows: This operating interval happens twice during a full cycle of the grid current. Therefore, the RMS current value of switch S 3 can be calculated as follows: The switching loss and conduction loss of the switch S 3 during interval (0 , ωt 1 ) can be calculated as: In this interval(ωt 1 , ωt 2 ), switch S 3 is in on-state continuously. Therefore, the switching losses of this switch are zero, and it has only conduction losses. The current equation of switch S 3 in this interval can be calculated as follows: The RMS current value of switch S 3 during interval (ωt 1 , ωt 2 ) can be calculated as follows: The conduction losses of switch S 3 can be calculated as: In this interval, the switch S 3 is in on-state continuously. So, the switching losses of switch S 3 are zero, and it has only conduction loss. The current equation of switch S 3 in this interval can be calculated as follows: The RMS current value of switch S 3 during interval (ωt 2 , π 2) can be calculated as follows: The conduction losses of switch S 3 during this interval can be calculated as: In the negative half cycle of the grid voltage, the switch S 3 is in on-state only during the interval(π, π + ωt 1 ). In this interval, the current equation of switch S 3 can be calculated as: The RMS current value of switch S 3 during interval (π, π + ωt 1 ) can be calculated as follows: The switching and conduction power losses of the switch S 3 during interval (π, π + ωt 1 ) can be calculated as follows: The total power loss of the switch S 3 during a full period cycle of grid voltage waveform can be obtained as: P S 3 = P SW ,S 3 ,(0,ωt 1 ) + P SW ,S 3 ,(π,π+ωt 1 ) + P Con,S 3 ,(0,ωt 1 ) + P Con,S 3 ,(ωt 1 ,ωt 2 ) + P Con,S 3 ,(ωt 2 ,π / 2) + P Con,S 3 ,(π,π+ωt 1 ) Also, the losses of other switches and diodes are calculated in the same way. The detailed values of switching and conduction losses of used semiconductors in the proposed topology under different output power (100 W ∼1900 W )  are presented in Table 3. Fig. 10(a) illustrates the pie chart of the semiconductors' power losses, and capacitor's power losses distribution. Also, the simulation, calculation and experimental efficiency curves of the proposed inverter versus output power can be illustrated in Fig. 10(b). Regarding this figure, it can be seen that at output powers 500 W and 800 W , the maximum values of experimental efficiency are around 97.5% and 97%, respectively.

VII. COMPARISON
An extensive comparison between the suggested inverter and other previous grid-connected inverters to demonstrate the advantages of the proposed grid-tied structures is shown in Table 4. As seen, these topologies are compared with different aspects such as the number of passive and active elements, input voltage, the value of leakage current, number of on-state switches, number of generated voltage levels, reactive power support capability, the value of the output filter elements, reported efficiency and voltage boosting ability. As evident from Table 5, all conventional topologies, except [3] and [29], lack voltage boosting ability and require additional power conversion stages to boost the output voltage. Regarding the points mentioned above, the input of the active neutral point clamp inverter requires more than 750 V dc voltage, while the other topologies request 400 V dc voltage. Furthermore, all the mentioned grid-connected inverters except common ground type inverters introduced in [3], [26], [29] cannot eliminate the unpleasant leakage current totally and only can reduce it. Hence, the proposed inverter without an extra dc-dc stage has a boosting ability of 1.5 times the input voltage. Also, the proposed grid-connected inverter can generate six voltage levels and mitigate the leakage current. Moreover, the reported efficiency of the proposed inverter is acceptable in comparison with other topologies. Hence, the proposed inverter exhibits more merits than the conventional inverter in terms of voltage boost ability, minimizing leakage current, reactive power supporting ability, reducing the required dc-link voltage, and reducing the voltage stress on the devices. In addition, Table 5 provides comparison results of the proposed topology with some other conventional grid-tied inverters. Considering Table 5, it can be seen that the comparison is done in terms of total cost ($), cost/P out (PU), output power (P out ), total volume (cm 3 ), power density (W /cm 3 ), voltage stress and current stress of utilized switches. Based on this table, the per-unit value of total cost (P.U.) is less than all of the compared topologies except topologies [18], [19] and [50]. Therefore, compared to other proposed structures, the proposed topology is cost-effective. Compared other presented topologies in Table 5 except [3], [17], [18], [33]   and [37], the proposed topology has the best value of the power density. Although the power density of the proposed topology is lower than topologies [3], [17], [18], [33] and [37], it nevertheless has a higher overall efficiency.
Although the power density of the proposed structure is less than structures [17], [18] and [29], but in comparison with these structures the proposed structure can eliminate the leakage current. Also, the proposed structure, unlike structures [18] and [19], can provide voltage boosting feature.
Although the power density of the proposed topology is lower than that of structures [3] and [37], it nevertheless has high efficiency. Also, unlike topology [37], the proposed topology can provide voltage boosting capability.

VIII. EXPERIMENTAL RESULTS
In this part, to confirm the suggested grid-tied inverter's operation, the experimental results according to a 770 W laboratory prototype have been provided, as shown in Fig. 11. VOLUME 10, 2022 FIGURE 11. Experimental prototype of the proposed grid-tied inverter. A 267 V input voltage source has been employed as the inverter's voltage source in this laboratory prototype. Table 6 illustrates the specifications of the implemented laboratory prototype. At 770 W output power, the peak value of output current is 5 A. Also, capacitors C 1 and C 2 are charged to half the input voltage or 133 V . Taking into account 6% voltage ripple for each of the capacitors, using equation (44) their capacitance is calculated as follows: ; 1000 µF Capacitors C 3 and C 4 are each charged to the input voltage. Using equations (40) and (45) and considering the 6% voltage ripple for these capacitors, their capacitance is obtained as: Equations (46) to (49) have explained how to design the output filter inductor value. As mentioned in the paper, the maximum ripple of the output inductor current occurs at a unity power factor and ωt = π 2 . According to (49), considering 10% of the current ripple value, the output filter inductance is calculated as follows: (75) Fig. 12 (a) indicates the output six-level voltage with 400 V peak value and the sinusoidal grid injected current with the unity power factor. Therefore, in this respect, the maximum amplitude of the injected current to the grid is approximately 5 A. Moreover, Fig. 12(b) indicates the grid's voltage waveform plus the six-level output voltage of the suggested grid-connected inverter. As illustrated, the system tracks the reference current through the filter-side inductor correctly. Therefore, the proposed inverter and its corresponding peak current controller method are capable of operating together properly. Utilizing the NPC-based method makes more limitations of leakage current. The voltages of utilized capacitors are indicated in Fig. 12    Based on this figure, it can be seen that the voltage stress of this switch consists of both positive and negative half cycles. Therefore, the switch S 5 is a bidirectional switch.
In the PV systems, the total value of the parasitic capacitor is around 100 nF/1 kW. In the proposed inverter, the capacitance value of each parasitic capacitor is considered 50 nF. The leakage current of parasitic capacitors C PV 1 and C PV 2 are illustrated in Fig. 15(a). Regarding this figure, the amplitude of I CPV 1 and I CPV 2 is less than 5 mA. Based on the IEEE standard (VDE 0216-1-1 IEEE), the maximum allowed value of leakage current for transformer less grid-tied inverters is 300 mA. So that the proposed inverter can pass the leakage current limitation of IEEE standard. Figs. 15(b)-(d) show the current stress of utilized power switches. Fig. 15(b) shows the current stress of the switches S 1 and S 2 . Considering this figure, it can be seen that these switches pass the injected grid current along with the capacitor charging current (I S1 = I S2 = I mg + I ch ). Regarding this figure, peak value of capacitor charging current is 14 A and peak value of injected grid current is 5 A. Therefore, the capacitor charging current is limited to 2.8 times the injected grid current. The current stress of the switches S 3 and S 4 are VOLUME 10, 2022  presented in Fig. 15(c). Based on this figure, the peak value of the current stress of these switches is equal to the peak value of injected grid current. The current stress of the switch S 5 is shown in Fig. 15(d). Considering this figure, it can be seen that the switch S 5 passes the injected grid current. To further investigate the performance of the proposed grid-tied inverter and its applied control system, the injected current into the grid, and the grid voltage at different values of the injected power to the grid have been measured. Regarding Figs. 16(a)-(c), the proposed inverter's injected power into the grid is 310 W , 460 W and 620 W , respectively. To investigate the dynamic performance of the proposed structure, step changes of the reference current (i ref ) have been applied. Based on Fig. 16(d), the step change of the injected grid current is a change from 2.5 A to 5 A. So that, the injected power changes from 380 W to 770 W . Concerning Fig. 17(a), the step change of the injected grid current is a change from 5 A to 2.5 A. Based on this step change, the amplitude of active power decreases from 770 W to 380 W . Fig. 17(b) shows the inverter output voltage along with the injected current to the grid under step change of the reference current. Considering this figure, the step change of the injected grid current is a change from 2.5 A to 5 A. Therefore, the injected active power increases from 380 W to 770 W . Fig. 17(c) illustrates the inverter output voltage and the injected current to the grid waveform under step change of the injected grid current is a change from 5 A to 2.5 A.
Regarding Fig. 17(c), it can be seen that the injected power to the grid decreases from 770 W to 380 W . The inverter output voltage and injected grid current under step change of the input voltage have been illustrated in Fig. 17(d).The step-change of the input voltage changes from 240 V to 300 V . Since the proposed topology has a voltage gain of 1.5, by applying this step change, the peak value of output voltage will increase from 360 V to 450 V .  The applied step change will affect the injected grid power, and the output power changes from 620 W to 770 W . In order to validate the step change in the reactive power operation of the proposed inverter, the related experimental results are presented in Fig. 18. Regarding Fig. 18(a), the amplitude of the reference current increase from 3.2 A to 5 A. Therefore, the value of the injected power to the grid increases from 500 VA (at PF=0.95 lag) to 770 VA (at PF=0.81 lag).
Considering Fig. 18(b), the amplitude of the reference current decrease from 5 A to 3.2 A. So that, the value of the injected power to the grid decreases from 770 VA (at PF = 0.81 lag) to 500 VA (at PF = 0.95 lag). Based on Fig. 18, it can be concluded that the proposed topology provides reactive power support to the grid under step change conditions. Furthermore, Fig. 19 shows the harmonic spectrum with THD of injected current to the grid at 770 W output power. According to this figure, the THD of injected current into the grid is about 2.05%. Based on IEC 61000-3-2 and IEEE 1547.2-2008 standards the limit of THD of injected current to the grid is less than 5%. Therefore, the proposed structure can pass these mentioned standards.

IX. CONCLUSION
A novel transformer-less six-level grid-connected inverter with reduced leakage current abilities is presented in this paper. The proposed inverter's advantages can be mentioned as reduced leakage current, voltage boosting ability, reactive power supporting feature, and high efficiency. Without an extra dc-dc stage, the proposed inverter has a boosting ability of 1.5 times the input voltage and reduces the system's overall weight, loss, and cost. Moreover, this topology generates six levels of voltages, including ±0.5 V dc , ±1 V dc , and ±1.5 V dc , which reduces the size of the filter and total harmonic distortion. To control both active and reactive powers, the PCC strategy is applied. Besides, using the PCC method, the injected grid current has a suitable quality under any PF conditions. The design of utilized circuit components is developed in this paper. Also, in order to highlight the benefits of the proposed inverter, it has been compared with some other grid-connected inverters. Finally, to validate the characteristics mentioned above and the proposed inverter's performance, experiments are carried out using a 770 W laboratory prototype.
MILAD GHAVIPANJEH MARANGALU was born in Urmia, Iran, 1992. He received the B.Sc. degree and the M.Sc. degree in power electrical engineering from Urmia University, Urmia, in 2014 and 2018, respectively. He is currently pursuing the Ph.D. degree with the Electrical and Computer Engineering Department, University of Tabriz, Tabriz, Iran. He has been a Visiting Researcher with the Department of Electrical Engineering and Mechatronics, Tallinn University of Technology, Tallinn, Estonia. He has authored and coauthored 20 journals and conference papers. His current research interests include multilevel inverters, grid-tied photovoltaic inverters, high step-up power electronic converters, control systems for multilevel inverters, and renewable energy systems.
SHAMIM MOHAMMADSALEHIAN was born in Mahabad, Iran, in 1993. She received the B.Sc. degree in power electrical engineering from the University of Tabriz, Tabriz, Iran, in 2015, and the M.Sc. degree in power electronics and electrical machines from Mohaghegh Ardabili University, Ardabil, Iran, in 2018. Her research interests include the design and analysis of power electronic converters/inverters and their specific applications, and also the interconnection of renewable energies with power electronic converters and their control methods.